155results about "Electric/magnetic signal storage" patented technology

A communication system including a transmitter, a receiver, and a TMDS-like link, in which video data and auxiliary data are transmitted from the transmitter to the receiver, or in which video data are transmitted over the link from the transmitter to the receiver and auxiliary data are transmitted from the receiver to the transmitter (or from the transmitter to the receiver and also from receiver to the transmitter), a transmitter or receiver for use in such a system, and methods for sending auxiliary data and video data over such a link, synchronizing such auxiliary data with such video data, and generating clocks having frequency closely matching the rate at which the auxiliary data are transmitted. Typically, the auxiliary data include one or more streams of audio data. In some embodiments the transmitter transmits a video clock to the receiver over a video clock channel, at least one of the transmitter and receiver transmits at least one stream of auxiliary data to the other one of the transmitter and the receiver, and at least one of the transmitter and the receiver transmits over the video clock channel at least one auxiliary clock for the auxiliary data.

A clock synchroniser, and clock and data recovery apparatus incorporating the clock synchroniser, are described, together with corresponding clock synchronisation methods. The clock synchroniser incorporates an elastic buffer. A received clock signal is used to clock data into the buffer, and a locally generated clock is used to clock data out of the buffer. The local clock is synthesised using a PLL, and a fill-level signal from the elastic buffer is used to control to local clock frequency to maintain a desired average quantity of data in the buffer, thereby achieving synchronisation of the received and local clocks. In preferred embodiments the fill-level signal is used to control a variable divider in the feedback path of the PLL, which is supplied with a highly stable reference signal. A synchronised, and low-jitter local clock is thus produced. Preferably, the elastic buffer employs counters of relatively wide word width, and a storage array of much reduced depth, read and write pointers being provided by just a few of the least significant bits of the words.

A system and method of transmitting a data stream from a data source over a baseband wireless communication system to one or more receivers. The receivers simultaneously recover the data and clock signals of the original data stream from the wireless transmitted data so that the data stream can be provided by the receivers to a data sink at the same rate as the original data stream, with low jitter performance.

A display driver comprising: a high-speed serial interface circuit which receives a packet from a host device through a high-speed serial bus using differential signals, and outputs a command or data included in the received packet; a driver circuit which drives a main display panel based on the output command or data; and a low-speed serial interface circuit which outputs a command or data to a sub display driver through a low-speed serial bus when the packet received from the host device includes the sub display driver command or data. And the display driver inserts dummy data to the packet to adjust the difference of the transfer rate by inserting a dummy the dummy data. And the display driver adjust the difference of the transfer rate

A clock rate used in rendering broadcast streaming audio/video data is adjusted to converge on a clock rate associated with broadcasting the streaming data. The clock rate is adjusted by monitoring the buffer depth associated with a receive buffer that stores the incoming streaming data. The buffer depth provides an estimate of clock drift between the two clock rates. From the estimate of clock drift, the clock rate used in rendering broadcast streaming data is adjusted to avoid the clock drift causing skips or pauses in the rendered audio/video data.

An apparatus for managing data transmission in a telecommunications system, including a buffer unit arranged to receive data from one or more sources of data and to forward the data to a transmitter for transmission. The buffer unit is configured to delay the transmission of the data by storing the data for a time before forwarding it to the transmitter. The buffer unit is also configured to forward the stored data to the transmitter for transmission when an amount of data stored in the buffer unit reaches a predefined threshold.

A baud rate generator includes a first counter, a timer and a baud rate correcting circuit. The first counter is configured to count bits of an inputted serial data. The timer is configured to measure a time for which the first counter counts a predetermined number of bits based on a reference clock signal. The baud rate correcting circuit is configured to output a baud rate correction value based on the measurement time by the timer such that a baud rate in a serial communication is corrected based on the baud rate correction value.

A switchboard device and methods of operation of same are disclosed. Embodiments of the invention may provide a flexible means of interconnecting wideband and narrowband communications interfaces, where wideband communications interfaces may transfer wideband data sampled at a higher sampling rate, and narrowband communication interfaces may transfer narrowband data sampled at a lower sampling rate. Data streams sampled at different sampling rates can be combined and the sampling rate of the result adjusted as needed by the destination interface. Methods of operating embodiments of the present invention are included. An additional aspect of the present invention may include machine-readable storage having stored thereon a computer program having a plurality of code sections executable by a machine for causing the machine to perform the foregoing.

In various embodiments, a method (900) for controlling the operation of a transmitter circuit is provided, the method (900) including: detecting (902) a state of a message field within a data message to be sent by the transmitter circuit indicating a bit rate to be used for transmission by the transmitter circuit and switching (904) the mode of operation of the transmitter circuit from a first data transmission mode to a second data transmission mode depending on the state of the message indication field, wherein in the first data transmission mode a first circuit configured to transmit data may be used and wherein in the second data transmission mode a second circuit configured to transmit data may be used. Further, a corresponding controlling circuit is provided.

A WLAN transmitter capable of transmitting data signals modulated in accordance with an individual one of at least two different modulation schemes and corresponding methods and integrated circuit chips are provided. The WLAN transmitter contains a front end section having a low-IF topology and including a digital front end unit and an analog front end unit. The digital front end unit contains a first signal processing branch for processing transmission data signals modulated in accordance with a first one of said at least two different modulation schemes. The digital front end unit further contains a second signal processing branch for processing transmission data signals modulated in accordance with a second one of said at least two different modulation schemes. The analog front end unit contains one single signal processing branch for processing transmission data signals modulated in accordance with any one of said at least two different modulation schemes.

The invention provides a novel scheme to match the clock rates along a single transmission channel.

The rate matching aspect of this invention receives a character stream synchronized by a first clock and buffers the character streams. Buffered characters are then transmitted over an output channel synchronized by a second clock. The rate matching system removes one or more filler or removable characters from the output channel if an overflow condition is detected and inserts one or more filler or removable characters in the output channel if an underflow condition is detected.

A wireless communication terminal comprises: a packet receiving unit for receiving a packet from a wireless base station; module for obtaining a transmission rate and a required transmission time from the received packet; module for calculating a time required to perform a packet transmission/reception procedure on the basis of the required transmission time; an analysis unit that functions as module for recognizing the existence of other terminal by decoding a destination MAC address described in the packet when the obtained transmission rate is equal to or lower than a transmission rate used by the wireless communication terminal; and a same-cell terminal list creation unit and band use time period scheduling unit for setting a band use time period that is equal to or greater than the time required to perform the packet transmission/reception procedure, for a time period, within a predetermined period corresponding to a packet generation period, regarding the other terminal and the wireless communication terminal, in order from the terminal having the lowest transmission rate.

An input/output data rate synchronization system includes a first data buffer that receives input data at a first rate, that temporarily stores the input data, and that outputs the input data at a second rate. A data processing module receives the input data from the first data buffer and outputs processed data at a third rate. A second data buffer receives the processed data from the data processing module at the third rate, temporarily stores the processed data, and outputs the processed data at a fourth rate. The data processing module temporarily stops receiving the input data and generating the processed data when the second data buffer exceeds a first predetermined capacity. The data processing module increases the second rate when the first data buffer exceeds a second predetermined capacity and decreases the second rate when a difference between the second and first rates is greater than a predetermined rate.

A method and a data-transmission system for transmitting data encoded in a signal between a transmitting user and a receiving user of the data-transmission system via a network structure of the data-transmission system. The data encoded in the signal are serially transmitted bit-by-bit in data frames having a defined structure. Each bit of the data encoded in the signal is sampled in the receiving user. Due to the transmission via the network structure, the signal is delayed asymmetrically. To compensate for the asymmetrical delay on the physical layer in the transmission channel, it is provided that the asymmetrical delay of the signal is determined at at least one point in the network structure, and is at least partially compensated prior to the receiving user sampling the bits of the data encoded in the signal. A measuring and compensating device is provided to measure and compensate for the asymmetrical delay.

What is disclosed is a method of operating a wireless communication device. The method includes accessing a wireless access system to receive a communication service, determining a service operator of the wireless access system, and selecting a data rate based on the service operator of the wireless access system. The method also includes requesting the selected data rate for the communication service from the wireless access system, and receiving the communication service at the selected data rate from the wireless access system.

An apparatus for modulating a digital input signal having a pre-assigned symbol rate and having a baseband carrier frequency by using a single sample clock signal. The pre-assigned symbol rate is selected from the group consisting of a plurality of symbol rates. The apparatus in a baseband mode comprises: (a) an Interpolate_by_2_Nyquist Filter block configured to double the pre-assigned symbol rate, to perform Nyquist filtering operation, and configured to output an Inphase (I) and a Quadrature (Q) components of the pre-assigned signal having the double symbol rate; (b) a Complex Shaper block configured to pre-compensate the spectrum of I and Q components of the signal having the double symbol rate in advance for a spectrum distortion caused by the apparatus; ©) a Cascaded Integrated Comb (CIC) Interpolator filter configured to increase by an interpolation R factor the sample rate of the signal as compared with a sample rate of the baseband carrier; (d) a Phase Shifter configured to compensate a phase of interpolated by R signal for a known quadrature error; (e) an Inphase (I) channel and Quadrature (Q) channel Gain blocks configured to pre-compensate the I and Q components of the interpolated by R signal for a known gain difference circuit between the I and Q channel gains; (f) an I and Q channel DC offset blocks configured to pre-compensate I and Q components of the interpolated by R signal for a known DC offset difference circuit between I and Q channel DC offset blocks; and (g) a Controller block configured to supply a plurality of control signals to the apparatus. In the passband mode, I and Q channel Gains are set to one, and I and Q channel DC offsets are set to zero.

A rate adjustment scheme. Two pairs of slightly oversized buffers are utilized as jitter buffers. While a pair of buffers are dispensing and gathering audio input and audio output samples, another pair of buffers function as encoder/decoder input and output buffers. The input and output sample buffers work in sample based time scale by accepting and discharging one sample at a time. The encoder/decoder buffers are utilized in frame based scale where an entire block of samples is read or written for encoding or decoding. On every frame clock derived from an external source, the uplink buffers (i.e., the audio input and the encoder input buffers) are swapped. The downlink buffers (i.e., the audio output and the decoder output buffers) are also swapped. The rate adjustment takes place seamlessly in the act of buffer swapping.