Clock synchroniser and clock and data recovery apparatus and method

a clock synchroniser and data recovery technology, applied in multiplex communication, baseband system details, instruments, etc., can solve the problems of inability to recover small amounts of jitter, inability to accept data error rates in received data, and inability to add additional jitter in the data stream, so as to avoid data loss, reduce jitter, and reduce jitter
US20050220240A1Inactive Publication Date: 2005-10-06WOLFSON MICROELECTRONICS LTD
16 Cites 74 Cited by

Patent Information

Authority / Receiving Office
US · United States
Current Assignee / Owner
WOLFSON MICROELECTRONICS LTD
Publication Date
2005-10-06
Estimated Expiration
Not applicable · inactive patent

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

A clock synchroniser, and clock and data recovery apparatus incorporating the clock synchroniser, are described, together with corresponding clock synchronisation methods. The clock synchroniser incorporates an elastic buffer. A received clock signal is used to clock data into the buffer, and a locally generated clock is used to clock data out of the buffer. The local clock is synthesised using a PLL, and a fill-level signal from the elastic buffer is used to control to local clock frequency to maintain a desired average quantity of data in the buffer, thereby achieving synchronisation of the received and local clocks. In preferred embodiments the fill-level signal is used to control a variable divider in the feedback path of the PLL, which is supplied with a highly stable reference signal. A synchronised, and low-jitter local clock is thus produced. Preferably, the elastic buffer employs counters of relatively wide word width, and a storage array of much reduced depth, read and write pointers being provided by just a few of the least significant bits of the words.
Need to check novelty before this filing date? Find Prior Art

Description

FIELD OF THE INVENTION

[0001] The present invention relates to clock synchronisers and to clock and data recovery apparatus and methods. Particular embodiments are concerned with methods and circuits for recovering a low jitter clock and data from jittered data (e.g. a jittery data stream). BACKGROUND TO THE INVENTION

[0002] FIG. 1 shows a data link comprising two systems each clocked by a respective PLL. The transmitter transmits data at a given rate and the receiver clocks the data in using its local clock. However the two clock frequencies may not be exactly the same, either short-term or long-term.

[0003] Short-term variations in frequency will arise in each clock from thermal noise or external interference, and can be considered as jitter in the respective clocks. Additional jitter in the data stream may be introduced by inter-symbol interference due to the finite bandwidth of the transmission channel or by crosstalk between adjacent cables.

[0004] For general data links, increa...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More