Clock synchroniser and clock and data recovery apparatus and method

Abstract

A clock synchroniser, and clock and data recovery apparatus incorporating the clock synchroniser, are described, together with corresponding clock synchronisation methods. The clock synchroniser incorporates an elastic buffer. A received clock signal is used to clock data into the buffer, and a locally generated clock is used to clock data out of the buffer. The local clock is synthesised using a PLL, and a fill-level signal from the elastic buffer is used to control to local clock frequency to maintain a desired average quantity of data in the buffer, thereby achieving synchronisation of the received and local clocks. In preferred embodiments the fill-level signal is used to control a variable divider in the feedback path of the PLL, which is supplied with a highly stable reference signal. A synchronised, and low-jitter local clock is thus produced. Preferably, the elastic buffer employs counters of relatively wide word width, and a storage array of much reduced depth, read and write pointers being provided by just a few of the least significant bits of the words.

Description

FIELD OF THE INVENTION [0001] The present invention relates to clock synchronisers and to clock and data recovery apparatus and methods. Particular embodiments are concerned with methods and circuits for recovering a low jitter clock and data from jittered data (e.g. a jittery data stream). BACKGROUND TO THE INVENTION [0002]FIG. 1 shows a data link comprising two systems each clocked by a respective PLL. The transmitter transmits data at a given rate and the receiver clocks the data in using its local clock. However the two clock frequencies may not be exactly the same, either short-term or long-term. [0003] Short-term variations in frequency will arise in each clock from thermal noise or external interference, and can be considered as jitter in the respective clocks. Additional jitter in the data stream may be introduced by inter-symbol interference due to the finite bandwidth of the transmission channel or by crosstalk between adjacent cables. [0004] For general data links, increa...

AI Technical Summary

Benefits of technology

[0069] The clock and data recovery circuit may be incorporated in a data receiver. The receiver provides the advantage that it attenuates jitter in the received data (the received data stream) down to low jitter frequencies to ensure low-distortion reproduction, and also avoids loss of data due to the jittery input clock and the clean output clock (the local clock) slipping past each other. That is, short-term (above audio frequency) and medium-term (audio frequency) variations in the received data rate are smoothed by the receiver to give a constant frequency output, but the long-term frequency of the regenerated clock and data are, generally, exactly equal to the received data rate. The received data rate, and the output data and clock rate are synchronised. The receiver achieves this by ensuring that the average local clock frequency matches the average rece...

Problems solved by technology

Additional jitter in the data stream may be introduced by inter-symbol interference due to the finite bandwidth of the transmission channel or by crosstalk between adjacent cables.

For general data links, increasing amounts of jitter may only cause problems if they lead to unacceptable data error rates in the received data.

However for audio data links, even small amounts of jitter may be important, since the digital audio signal will eventually be reproduced as an analogue waveform by a digital-analogue converter (DAC).

For high quality reproduction of the digital audio a significant amount of jitter will impair the performance.

Long-term, both crystals will have a frequency error (possibly 500 ppm) and there may also be an error in the frequency generated by the PLL at either end.

If the transmitter clock is faster than the receiver clock, data will occasionally be lost: if the receiver clock is faster than the transmitter clock occasional bits will be sampled and clocked out twice.

Even a few ppm difference on a 12 MHz data stream could give missing bits several times a second, which would be completely unacceptable for both digital audio data or indeed more general data streams.

However, in this implementation the elastic buffer is used merely to absorb the short- and medium-term jitter and no effort is made to synchronise the local clock to the remote clock, i.e. no measures are taken to ensure the respective data rates are the same long term, to avoid loss of data.

However for systems with no IDLE data t...

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