393 results about "Write pointer" patented technology

Update data to a non-volatile memory may be recorded in at least two interleaving streams such as either into an update block or a scratch pad block depending on a predetermined condition. The scratch pad block is used to buffered update data that are ultimately destined for the update block. Synchronization information about the order recording of updates among the streams is saved with at least one of the streams. This will allow the most recently written version of data that may exist on multiple memory blocks to be identified. In one embodiment, the synchronization information is saved in a first block and is a write pointer that points to the next recording location in a second block. In another embodiment, the synchronization information is a time stamp.

Disclosed is a memory device which is not easily deteriorated and a memory managing method which does not easily deteriorate a memory device. A physical address is given to a memory area of a flash memory (11) page by page. When supplied with to-bewritten data and a logical address where the data is to be written, a CPU (121) writes this data in a page indicated by a write pointer. The correlation between the physical address and the logical address of the page is stored in a RAM (123) in the form of BPT (Block Pointer Table). At the time of reading, the CPU (121) that has been supplied with the logical address searches the BPT to specify a physical address associated with that logical address and reads data from that page which is given the specified physical address. Flash erasing of a block is executed when the number of empty blocks becomes equal to or smaller than a predetermined number.

In a memory system with a file storage system, a scheme for allocating memory locations for a write operation is to write the files substantially contiguously in a memory block one after another rather than to start a new file in a new block. In this way, they are more efficiently packed into the blocks by being written contiguously one after another. In a preferred embodiment, an incrementing write pointer points to the write location in memory for the next data for a file, which is independent of the offset address of the data within the file. When a current write block becomes filled with file data, an erased block is allocated, and the write pointer is moved to this block. Similarly a relocation pointer is used for data relocation during garbage collection or data compaction operations.

An improved descriptor system is provided in which read pointers indicate to a host and a peripheral the next location to read from a queue of descriptors, and write pointers indicate the next location to be written in a queue. The system also allows an incoming descriptor to point to a plurality of data frames for transfer to the host processor, wherein the peripheral need not read a new descriptor each time a frame is to be transferred to the host.

A system and method for compensating for differences between a recovered receive clock and an internal transmit clock in an elastic buffer and thereby preventing corruption of data. In one embodiment, the system comprises a circularly accessed buffer coupled to read and write logic. The read and write logic read and write to locations within the circular buffer as indicated by respective read and write pointers. The system further comprises control logic which compares the pointers to determine whether the buffer is approaching an underflow or overflow condition and adds or deletes fill words between frames of data to compensate for the underflow or overflow condition. In one embodiment, the system includes fill word logic which is configured to add a fill word bit to each received word and to set or clear the fill word bit to indicate whether or not the corresponding word is a fill word.

A clock synchroniser, and clock and data recovery apparatus incorporating the clock synchroniser, are described, together with corresponding clock synchronisation methods. The clock synchroniser incorporates an elastic buffer. A received clock signal is used to clock data into the buffer, and a locally generated clock is used to clock data out of the buffer. The local clock is synthesised using a PLL, and a fill-level signal from the elastic buffer is used to control to local clock frequency to maintain a desired average quantity of data in the buffer, thereby achieving synchronisation of the received and local clocks. In preferred embodiments the fill-level signal is used to control a variable divider in the feedback path of the PLL, which is supplied with a highly stable reference signal. A synchronised, and low-jitter local clock is thus produced. Preferably, the elastic buffer employs counters of relatively wide word width, and a storage array of much reduced depth, read and write pointers being provided by just a few of the least significant bits of the words.

A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.

A method and apparatus for operating a memory is presented. Information is stored in the memory based on a first time domain and information is read from the memory based on a second time domain. A cooperative relationship is maintained between a write pointer which points to memory locations, where data will be stored and a read pointer which points to memory locations, from which data will be read. A FIFO memory is presented which has memory locations and a register array is presented which stores a bit array that has bit locations. Each bit location in the bit array corresponds to a memory location in the memory. As the write pointer points to a memory location and data is stored in the memory location, a bit (e.g. flag) is set in the bit array. The Flag designates whether the data stored in the memory location is available for reading. Prior to reading information from the memory location, a test is made of the bit location that corresponds to the memory location. The bit value denotes whether the data stored in the memory location is valid data and available for reading.

Method for managing a queue in host memory for use with a peripheral device. Roughly described, the host makes a determination of the availability of space in the queue for writing new entries, in dependence upon historical knowledge of the number of queue entries that the host has authorized the device to write, and the number of entries that the host has consumed. In dependence on that determination, the host authorizes the device to write a limited number of new entries into the queue. The device writes entries into the queue dependence upon the number authorized. The host maintains a read pointer into the queue but does not need to maintain a write pointer, and the peripheral device maintains a write pointer into the queue but does not need to maintain a read pointer.

Method and apparatus for retrieving buffer descriptors from a host memory for use by a peripheral device. In an embodiment, a peripheral device such as a NIC includes a plurality of buffer descriptor caches each corresponding to a respective one of a plurality of host memory descriptor queues, and a plurality of queue descriptors each corresponding to a respective one of the host memory descriptor queues. Each of the queue descriptors includes a host memory read address pointer for the corresponding descriptor queue, and this same read pointer is used to derive algorithmically the descriptor cache write addresses at which to write buffer descriptors retrieved from the corresponding host memory descriptor queue.

Methods, systems, and software are provided herein that allow a user to store and retrieve data records. In one example, a method of storing data records is provided. The method includes initializing a shared write pointer to a first location in a shared memory of a data storage system, and receiving a plurality of data records transferred by a plurality of data sources for storage in the shared memory. The method also includes, beginning with a first of the plurality of data sources, writing in a cyclic sequence one of the plurality of data records for each of the plurality of data sources based on the shared write pointer, and incrementing the shared write pointer after each writing, and updating at least a header portion of the shared memory with the shared write pointer responsive to each writing.

One embodiment facilitates a write operation in a shingled magnetic recording device. During operation, the system receives, by the storage device, data to be written to the storage device and access-frequency information associated with the data, wherein the storage device includes a plurality of concentric tracks. The system distributes a plurality of spare sector pools among the plurality of concentric tracks. The system selects a track onto which to write the data based on the access-frequency information, wherein data with a highest access-frequency is written to an outer track. The system appends the data at a current write pointer location of the selected track, thereby facilitating an enhanced data placement for subsequent access in the storage device.

The present invention relates to a queuing system, implemented in the memory of a computer by the execution of a program element. The queuing system includes a queue with a plurality of memory slots, a write pointer and a read pointer. The write pointer permits to enqueue data elements in successive memory slots of the queue. The read pointer permits to dequeue data elements from the queue memory slots for processing, where these data elements are potentially non-dequeuable. Upon identifying a non-dequeuable data element in a particular memory slot of the queue, the read pointer is capable to skip over the particular memory slot and move on to a successive memory slot.

Systems and methods implement queues that perform write operations in a re-circulating sequential manner. The nature of the queue systems of the present invention allow writes to the queue to occur independently of read operations therefrom. A current event counter is updated by the queue logic to keep track of a count value that corresponds to the total number of data events written to the queue. Preferably, the current event counter is capable of counting an amount greater than the total number of addressable storage locations of the queue. A write pointer may be derived from the count value stored in the event counter from which a select addressable storage location of the queue can be determined for queuing each new data event. Read operations from the queue may be performed according to any prescribed manner, including random access thereto. Moreover, read operations can be performed in a first manner when no overflow is detected, and in a second manner in response to overflow.

The invention provides a data-caching access method and a data-caching controller and relates to the field of data processing, in particular to data caching. According to the data-caching access method and the data-caching controller, a segment of continuous storage space is distributed in a shared storer and used for conducting first-in-first-out data caching, a head address pointer of the controller points to a head address of the storage space, a tail address pointer points to a tail address of the storage space, the value of a write pointer is the value of the head address pointer, the value of a read pointer is the value of the head address pointer, and the storage space is initialized into a data-caching queue; read-write units are the minimal units of read-write operation of the storage space, and the length of the storage space is the number of the read-write units in the storage space. The controller can be well adapted to different program development and operation requirements, and storer resources can be utilized sufficiently.

The embodiment of the invention discloses a method for realizing a ring buffer, which comprises the following steps: when reading data, judging whether the value of a current read pointer of the ring buffer is equal to the value of the current write pointer, if so, returning to null, otherwise reading data in the storage space pointed by the current read pointer of the ring buffer, and adding 1 to the value of the current read pointer after the read operation is carried out; and when writing data, subtracting the value of the current write pointer of the ring buffer from the value of the current read pointer, and judging whether the difference after the subtraction is less than the maximum storage value of the ring buffer, if so, writing the data into the storage space pointed by the current write pointer of the ring buffer and adding 1 to the value of the current write pointer after the write operation is carried out, otherwise returning to full. The invention can maximally utilize the message space of the ring buffer without degrading the system performance.

Different sampling rates between a playout unit and a capture unit are compensated for via a system, method and computer program product. The playout unit receives samples from a computational unit, and the capture unit sends samples to the computational unit. A playout FIFO buffer operates in a playout time domain, and a capture FIFO buffer operates in a capture time domain. The computational unit is synchronized to a common clock. A first relationship is calculated between the common clock and a playout fifo buffer read pointer, and a second relationship is calculated between the common clock and a capture FIFO buffer write pointer. For each sample in the playout time domain a corresponding sample in the samples from said computational unit is found and sent to the playout FIFO buffer. For each sample in the common clock time domain the corresponding sample in the capture time domain is found and sent to the computational unit.

A slice decoder control circuit sequentially supplies the parameter of the picture layer and the write pointer of a first slice to a first slice decoder, the parameter of the picture layer and the write pointer of a second slice to a second slice decoder, and the parameter of the picture layer and the write pointer of a third slice to a third slice decoder, and causes the slice decoders to decode the respective parameters and write pointers. On the basis of the input of signals indicating the completion of decoding processing inputted from the slice decoders, the slice decoder control circuit supplies the write pointer of a fourth slice to the second decoder and causes the second slice decoder to decode the write pointer at timing A, and supplies the write pointer of a fifth slice to the third decoder and causes the third slice decoder to decode the write pointer at timing B. Subsequently, the similar processing is repeated until the last slice is decoded. The operations of a plurality of slice decoders are thus controlled.

The invention provides a method and system for synchronously displaying images with the UHD resolution ratio. The method includes the first step of obtaining subimage signals corresponding to signal channels, wherein the subimage signals are image signals obtained through segmentation of image signals, requiring to be displayed, with the UHD resolution ratio, the second step of carrying out synchronization on read-write pointers, subjected to frame rate conversion processing, of the signal channels and read-write pointers, subjected to frame buffer processing, of the signal channels, and processing the subimage signals according to the synchronized read-write pointers, and the third step of carrying out image merging on the processed subimage signals of the signal channels and carrying out display on a tiled display device. Through the method and system, the synchronous display of the images with the UHD resolution ratio is achieved, and cost is reduced.