398 results about "Write pointer" patented technology

Method and apparatus for retrieving buffer descriptors from a host memory for use by a peripheral device. In an embodiment, a peripheral device such as a NIC includes a plurality of buffer descriptor caches each corresponding to a respective one of a plurality of host memory descriptor queues, and a plurality of queue descriptors each corresponding to a respective one of the host memory descriptor queues. Each of the queue descriptors includes a host memory read address pointer for the corresponding descriptor queue, and this same read pointer is used to derive algorithmically the descriptor cache write addresses at which to write buffer descriptors retrieved from the corresponding host memory descriptor queue.

Methods and systems are provided for managing the application of one or more XML data mappings or one or more XML schema files to a spreadsheet application workbook. One or more XML schema files for associating to the spreadsheet workbook are obtained. Each schema file is iterated to determine if one or more additional schema files are identified in each of the obtained schema files. Each obtained schema is parsed to determine data definitions, elements, attributes, structure, and simple data content required by each schema file for valid XML data. All obtained schema files are combined to create a unified schema definition. A single root element is selected to serve as a root element for the generalized instance structure. A generalized instance structure of the unified schema definition is built representing all available elements, attributes or simple data content of the unified schema definition that may be applied to the spreadsheet application workbook. A tree view of the generalized instance structure is displayed for providing a visual representation of the instance structure of the unified schema definition representing elements, attributes, structure, and simple data content of the XML defined by the unified schema definition that may be validly applied to the spreadsheet workbook according to the generalized instance structure. Writing pointers to the XML map object expresses a relationship between workbook locations and XML elements.

A clock synchroniser, and clock and data recovery apparatus incorporating the clock synchroniser, are described, together with corresponding clock synchronisation methods. The clock synchroniser incorporates an elastic buffer. A received clock signal RCK is used to clock data into the buffer, and a locally generated clock LCK is used to clock data out of the buffer. The local clock is synthesised using a PLL, and a fill-level signal from the elastic buffer is used to control to local clock frequency to maintain a desired average quantity of data in the buffer, thereby achieving synchronisation of the received and local clocks. In preferred embodiments the fill-level signal is used to control a variable divider in the feedback path of the PLL, which is supplied with a highly stable reference signal. A synchronised, and low-jitter local clock is thus produced. Preferably, the elastic buffer employs counters of relatively wide word width, and a storage array of much reduced depth, read and write pointers being provided by just a few of the least significant bits of the words.

A processor (1700) including a pipeline (1710, 1740) having a fetch pipeline (1710) with branch prediction circuitry (1840) to supply respective predicted taken target addresses for branch instructions, an execution pipeline (1740) with a branch execution circuit (1870), and storage elements (in 1860) and control logic (2350) operable to establish a first-in-first-out (FIFO) circuit (1860) with a write pointer WP1 and a read pointer RP1. The control logic (2350) is responsive to the branch prediction circuitry (1840) to write a predicted taken target address to a storage element (in 1860) identified by the write pointer (WP1) and the predicted taken target address remains stationary therein. The FIFO circuit (1860) bypasses a plurality of pipestages between the branch prediction circuitry (1840) and the branch execution circuit (1870). The control logic (2350) is operable to read a predicted taken target address (PTTPCA) from a storage element (in 1860) identified by the read pointer RP1.