134 results about "Write pointer" patented technology

The invention discloses a PCIe switch multicast processing system and method giving consideration to efficiency and resources, and the system comprises a unicast control module which is used for receiving the target port information of a unicast TLP packet, a TLP indication signal, TLP header information and TLP load data, and transmitting a unicast request; the multicast control module is used for receiving a target port list of a multicast TLP packet, a TLP indication signal, TLP header information and TLP load data, and sending a multicast request; the target port arbitration module is used for receiving a unicast request and a multicast request, and sending a request packet corresponding to the unicast request or the multicast request to the sending cache module; and the sending cache module is used for receiving the authorized unicast TLP packet or multicast TLP packet, caching the unicast TLP packet or multicast TLP packet, and sending and outputting the unicast TLP packet or multicast TLP packet to the egress end of the target port. According to the invention, the processing of the multicast packet is centralized at the ingress end of the PCIe port, the unicast packet and the multicast packet are separately processed, meanwhile, two parallel processing channels are opened up in the multicast control module, and the copying of the multicast packet is realized through a roll back FIFO read-write pointer mode, so that the design is simplified, the resources are saved, and the efficiency is improved.

The invention discloses a real-time data receiving and transmitting system and method based on a kernel bypass, and the method comprises the steps: processing the received data when the data receiving and transmitting system receives the data, and achieving the high-level data with complete semantics; updating a write pointer through atomic operation, and writing high-level data into a lockless annular queue in the shared memory module; the upper-layer application module reads the lock-free annular queue in the shared memory; when the data receiving and transmitting system transmits data, upper-layer data to be transmitted is transmitted to the shared memory module, and a write pointer is updated; the upper layer data in the shared memory is read in a polling or interruption mode, a read pointer is updated, the upper layer semantic data is segmented according to the format, a UDP data packet is obtained, the UDP data packet is written into a network card in the polling or interruption mode, and data sending is achieved. Through the data receiving and transmitting system disclosed by the invention, microsecond-level ultra-low delay of data certainty is realized, and efficient decoupling and stable throughput are realized.

The invention discloses a low-power FIFO (First In First Out) module, which comprises an FIFO memory and an FIFO controller, the FIFO memory comprises a writing unit, a memory unit and a multiplexer, the FIFO controller comprises a writing pointer register, a reading pointer register, a first adder and a second adder, the FIFO controller further comprises a mux selection register and a third adder, the third adder enables a mux selection pointer signal output by the mux selection register to increase by 1 only when valid data is cached in the storage unit or new valid data is to be cached while the storage unit outputs the last valid data; and when the read signal is high, the multiplexer selects the data on the corresponding address from the storage unit according to the mux selection pointer signal and outputs the data. According to the invention, the problem of invalid flipping caused by invalid data output is solved, so that the power consumption is reduced.

A method of controlling a storage device includes grouping one or more memory blocks in which physical addresses are continuous, among a plurality of memory blocks included in the device, generating a plurality of zones by mapping continuous physical addresses to continuous logical addresses, controlling sequential write operations using write pointers indicating a logical address of a region in which data is to be written in a next order in each of the plurality of zones, determining invalid zones in which all stored data is invalid data, among the plurality of zones, determining a utilization rate of a storage space of the storage device, determining a write pointer threshold based on the utilization rate, determining a target zone in which a write pointer value is greater than the write pointer threshold, among the invalid zones, and controlling the storage device to erase all memory blocks included in the target zone.

An integrated circuit, a data transmission method across clock domains, an electronic device, and a storage medium. The integrated circuit includes a first clock domain and a second clock domain. The first clock domain includes a first pointer control module, and the second clock domain includes a second pointer control module. The first pointer control module includes a first synchronous pointer control module, and the first synchronous pointer control module is configured to: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determine a first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determine the first pointer control signal as a first value, so that the first read pointer and the first write pointer increase by the first value in each clock period of the first clock signal.

The invention discloses a method for realizing accurate synchronization of a time sequence in a simulator based on a shared memory, which relates to the technical field of simulator development and cross-process communication, and comprises the following steps: constructing a standardized three-layer layout comprising a head control region, an annular data region and a compact storage unit, the annular data area circularly accesses, and the compact storage unit binds data and a time sequence; cross-platform zero-leakage resource management is realized through a global singleton handle manager, and interface multiplexing is provided or a shared memory is created and mapped; the sending end encodes data, binds a time sequence and atomically updates a write pointer, and the receiving end reads the data, calibrates the time sequence and atomically updates a read pointer; and executing time sequence precision, transmission delay, throughput and stability verification. According to the method, the lock competition overhead is eliminated, the cross-process data transmission efficiency is greatly improved, the time sequence synchronization accuracy is guaranteed, and the hardware bus refinement requirement is met.

Methods, systems, and devices for zoned random write operations are described. A memory system may receive a set of write commands associated with respective logical block addresses (LBAs) that may be in a sequential order, where the respective LBAs may be associated with a zone. The memory system may write first data to a first physical block address (PBA), where the first data may be associated with a first LBA of the respective LBAs. The memory system may determine whether a second LBA associated with second data is sequential relative to a write pointer associated with the zone. The memory system may write the second data to a second PBA that may be sequential to the first PBA in response to determining that the second logical block address is non-sequential relative to the write pointer and on a value of a bitmap corresponding to the second LBA.

The invention relates to the technical field of data processing and provides a device and a method for high-speed input and output. In one embodiment, an apparatus includes a cross-clock-domain transmission logic to periodically receive N beats of input data of single N bits according to a write clock signal, and to individually write the input data bitwise to the cross-clock-domain transmission logic according to a value of each bit in the N-bit write enable control signal, and to transmit the input data to the cross-clock-domain transmission logic according to a value of each bit in the N-bit write enable control signal. Reading as output data according to a read enable control signal; and the cross-clock-domain sending control logic is used for writing a write enable control signal into the cross-clock-domain sending control logic, reading as a gating signal according to the read clock signal, and gating the read clock signal according to the gating signal to obtain a read enable control signal, and the frequency ratio of the read clock signal to the write clock signal is N. Therefore, cross-clock-domain interaction of the read-write pointers is avoided, the logic depth and the chip complexity are reduced, and the speed can be increased and the power consumption can be reduced.

The invention provides a control word digital adjustment circuit and a retimer based on a decimal N frequency division phase-locked loop. The control word digital adjustment circuit comprises a digital low-pass filtering module and a control word adjustment module, wherein the digital low-pass filtering module is used for filtering high-frequency jitter and part of low-frequency jitter in an initial control word so as to generate a filtering control word; the control word adjusting module is used for adjusting the filtering control word based on a writing pointer and a reading pointer of a first-in first-out buffer in the retimer so as to generate an adjusting control word; the adjustment control word is used for replacing the initial control word to serve as input of a transmitter fractional N frequency division phase-locked loop in the re-timer. According to the invention, the problem of frequency deviation jitter of RX Clock and TX Clock easily caused by wrong reading numerical value of an asynchronous interface of the FCW in the existing scheme can be effectively solved.

The invention provides a redundant array management method and system based on a ZNS solid state disk, and the method comprises the steps: sequentially writing to-be-written data into a corresponding data block for each strip under the condition of receiving a write request, and carrying out the coverage updating of verification data of a verification block; positioning a logic actual write pointer to the tail position of the data block in which the data is continuously and successfully written, generating metadata corresponding to each data block, and writing the metadata into a standby area; the logic actual writing pointer is used for pointing to a next writable position in the logic area; under the condition that a fault occurs, repositioning the logic actual write pointer based on the metadata in the standby area; and on the basis of repositioning of the logic actual write pointer after the fault, discarding the data blocks outside the logic actual write pointer, recovering the data blocks inside the logic actual write pointer, and recalculating to generate verification data, thereby completing redundant array management of the ZNS solid state disk.

A processing device writes file system data to a first area of a memory zone of a zoned block memory device based on a current position of a write pointer within the memory zone. The file system data comprises data files contained within a file system and file structure metadata describing a file structure of the file system. The processing device detects a write event based on the write pointer advancing past a predetermined memory address within the memory zone that corresponds to a checkpoint. The checkpoint is a second area within the memory zone that is designated for storing write event data. Based on detecting the write event, the processing device writes write event data to the checkpoint, the first write event data indicating a most recent memory address of a root node of the file structure within the memory zone.

The invention discloses a multi-module communication method and device for a string type energy storage converter. The multi-module communication method comprises the following steps: respectively connecting a power module and a centralized control module through a dual-port random access memory; four independent buffer areas A1, A2, B1 and B2 are divided for each storage monomer, A1 and A2 serve as double buffer areas of the power module, and B1 and B2 serve as double buffer areas of the centralized control module; the method for writing and reading the independent buffer areas A1 and A2 and the independent buffer areas B1 and B2 comprises the following steps of: initially setting a read-write pointer, and finishing a flag bit and a memory barrier. According to the main technical scheme and the main effects, high-speed and low-delay data transmission is achieved, a dual-port random access memory array is adopted to replace traditional bus communication, the data transmission delay can be reduced from the millisecond level to the microsecond level, and the real-time acquisition requirement of the power module at the interval of 250 microseconds is met.

The invention provides an interface system and an operation method thereof. An interface system may include a first interface device and a second interface device. The first interface device may include a first buffer. The second interface device may include a second buffer. The first interface device may compare a write pointer corresponding to the first buffer of the second interface device with a read pointer corresponding to the first buffer of the first interface device, and update the read pointer based on a result of the comparison. Each of a write pointer of the first buffer and a read pointer of the first buffer may include a data bit indicating an address of the first buffer and a data bit indicating a reset signal. The first interface device may selectively update the read pointer according to a reset signal of the write pointer of the first buffer.

The embodiment of the application provides a PXIe-based DMA data transmission processing method, system and device, and belongs to the technical field of data transmission. The method first sends a DMA data read request to a host controller, the host controller is used for applying a ring buffer area to a main memory, and the ring buffer area is used for storing key information corresponding to DMA data; then, a DMA data read instruction sent by the host controller is received, a read difference between a read pointer and a write pointer pointing to the ring buffer area is determined based on the DMA data read instruction, wherein the read difference is obtained by the host controller by calculating the difference between the read pointer and the write pointer; target key information corresponding to target DMA data is read from the ring buffer area according to the read difference, and the read pointer is updated, so that the read pointer points to the latest read key information. The application can improve the efficiency of DMA data transmission while improving the performance of the host control.

The invention provides a communication method and device, electronic equipment, a chip and a storage medium, and relates to the field of communication, and the method comprises the steps: receiving a first write pointer sent by a first communication node; the first write pointer is used for indicating a write-in position of the IP packet information in the first message queue; reading the IP packet information from the first message queue according to the first write pointer so as to update a first read pointer of the first message queue; carrying the IP data packet associated with the IP packet information to obtain a carrying result; writing the carrying result into a second message queue to update a second write pointer of the second message queue; and synchronizing the carrying result, the second write pointer and the first read pointer in the second message queue to the first communication node. Therefore, the carrying result obtained by carrying the IP data packet this time and the two pointers are synchronized to the first communication node together, the first communication node does not need to actively obtain the data through cross-bus in a multi-time interaction mode, and the data transmission efficiency can be improved.

The application discloses a multi-core debugging method, device and system and a storage medium, relates to the technical field of testing, and discloses a multi-core debugging method, which comprises the following steps: a BSP determines a currently started AP in an AP in a multi-core CPU; the BSP determines a first target AP in the started AP and determines a first information buffer area corresponding to the first target AP; the BSP acquires a target write pointer and a target read pointer corresponding to the first information buffer area; if the target read pointer is smaller than the target write pointer, the BSP reads target data in a two-dimensional array of the first information buffer area based on the target read pointer; the BSP stores the target data into an information set buffer area based on the first target AP; and the BSP outputs data in the information set buffer area based on a preset rule. The application realizes that all cores can output debugging information in parallel, so that the debugging of multi-core business logic in a UEFI environment is facilitated.

A storage device according to some example embodiments comprises a non-volatile memory including a first memory including a plurality of zones configured to sequentially store data based on a write pointer, the write pointer indicating a position to write the data, and a second memory configured to store preliminary data to be written in the plurality of zones, and a storage controller configured to receive a plurality of operation requests, each of the plurality of operation requests including a logical block address, a write command, and write data, and store first write data corresponding to a first operation request in the second memory as first preliminary data, if the position of a first logical block address corresponding to the first operation request among the plurality of operation requests and the write pointer does not match.

The invention belongs to the field of remote direct memory access, and discloses a bitmap-based RDMA (Remote Direct Memory Access) data packet out-of-order receiving circuit and method, a bitmap checking module verifies the validity of a data packet and outputs a bitmap switching identifier, and a bitmap management module maintains pointer information through three states of order, out-of-order and bitmap updating; the bitmap information storage module is used for storing bitmap information, calculating the offset of a bitmap writing pointer in an out-of-order state and starting a fragmentation timeout mechanism, generating a window sliding enable signal when the bitmap state is updated, the bitmap information storage module responds to the enable signal to execute bitmap writing and window sliding updating, and the bitmap pointer storage module manages a multi-queue bitmap state identifier and a pointer in an RAM (random access memory) structure. By adopting the circuit, the bandwidth waste and congestion risk caused by retransmission can be obviously reduced; the tail delay jitter is reduced; and the adaptive capacity to multi-path network disorder is enhanced, so that the bandwidth utilization rate and the transmission reliability are comprehensively improved.

A kind of DAS signal adaptive demodulation method and system based on FPGA, wherein, the method comprises: obtaining the in-phase component signal and quadrature component signal of DAS signal;When the address of write pointer occurs incremental change, the historical in-phase component signal and historical quadrature component signal in the preset history sampling window are read;The instantaneous amplitude energy of each time stamp is calculated, and the instantaneous amplitude energy sequence is obtained;The amplitude energy mean and variance eigenvalue of DAS signal are calculated;Adaptive gain factor is generated;The in-phase component signal and quadrature component signal are compensated and iteratively demodulated by adaptive gain, and the phase output value and demodulation module length value are obtained;The module length deviation amount of demodulation module length value and preset standard module length is calculated, and when the cumulative value is greater than preset locking threshold, the correction coefficient is calculated according to the current amplitude energy mean and module length deviation amount;The storage value of index address is updated based on correction coefficient.The application can improve the reliability of DAS system.

The application belongs to the technical field of electronic evidence, and particularly relates to a full-link adaptive parallel data stream acceleration method and device and a storage medium, which comprises the following steps: monitoring the data stream state of a multi-protocol interface in real time; adopting an intelligent prefetch engine and an asynchronous decoupling pipeline to perform data reading scheduling; performing hardware parallel analysis on the data from different protocol interfaces in the physical layer and the link layer, extracting effective data load and address information, and reconstructing into a unified format data descriptor; storing the unified format data descriptor into a cache matrix; if the output rate of a device connected with the protocol interface is greater than the processing rate of a host, dynamically expanding the cache capacity of the cache matrix; when detecting that the host side is idle, initiating burst data transmission according to the maximum effective bandwidth of a PCIe interface connected with the host, and simultaneously adopting a write pointer lag control strategy to smoothly output the data stream; and through a DMA mechanism, directly writing the burst transmission data stream into the host memory bypassing the host CPU. The scheme realizes efficient electronic evidence.

The embodiment of the invention discloses a data storage method, relates to the technical field of data storage, and is used for improving the security of WORM storage equipment. The method is applied to the storage device, the storage device comprises a tape reel, the tape reel comprises a controller, the controller comprises a one-time programmable module, and the method comprises the steps that a write instruction is obtained, and the write instruction carries a first write pointer; if a first identifier is stored in the one-time programmable module, security verification is carried out on the first write pointer, and the first identifier is used for identifying the storage device as a WORM device; and if the security verification is passed, writing data carried in the write instruction into a storage space provided by the tape disk.

The invention discloses a multi-core debugging method, device and system and a storage medium, and relates to the technical field of testing, and the multi-core debugging method comprises the steps that a BSP determines a currently started AP in APs in a multi-core CPU; the BSP determines a first target AP in the started APs, and determines a first information buffer area corresponding to the first target AP; the BSP obtains a target write pointer and a target read pointer corresponding to the first information buffer area; if the target read pointer is smaller than the target write pointer, the BSP reads the target data in the two-dimensional array of the first information buffer area based on the target read pointer; the BSP stores the target data to an information set buffer area based on the first target AP; and the BSP outputs the data in the information set buffer area based on a preset rule. According to the method and the device, all the Core can output the debugging information in parallel, so that the debugging of the multi-core service logic in the UEFI environment is realized.

Provided are a data compression storage device and a method thereof based on a ZNS standard. A method for processing an IO command is provided, comprising: a host providing a first command for writing data to a first storage area (Zone) to a storage device; the storage device allocating a first logical address index for data to be written by the first command according to a write pointer (WP) of the first storage area, the first logical address index and a first size of the data to be written by the first command defining a first logical address space; compressing the data to be written by the first command to obtain compressed data; storing the compressed data; recording an address of storing the compressed data in association with the first logical address index; and providing the first logical address index to the host; and the host recording a first host logical address (HLBA) accessed by the first command in association with the first logical address index.

The invention relates to the technical field of smart card communication, in particular to a smart card communication queue implementation device, which is characterized in that a read pointer and a write pointer are arranged in a global queue cache; an interrupt module is utilized to generate a predicted position of a write pointer according to the business data and the position of the current write pointer, the business data are written into a global queue cache according to the predicted position of the write pointer, and the global queue cache can circularly write the business data; and reading the service data from the global queue cache by using the main program according to the current positions of the read pointer and the write pointer, and after the service data is processed, moving the position of the read pointer. According to the technical scheme, the problem of data interaction between the interrupt module and the main program during communication of the intelligent card is solved, and data interaction can be achieved even if the system is continuously triggered to be interrupted under the condition that signals are not good in the SWP communication process.

A memory sub-system comprises a controller managing memory devices. The controller is configured to: maintain a write pointer referencing a next data item position within a log buffer; maintain a log retrieval pointer referencing a data retrieval position within the log buffer; store at a log buffer position specified by the write pointer, a data item reflecting a state of the system; advance the write pointer by a size of the data item; responsive to receiving, from a host, a log retrieval request, retrieve log data starting from the position within the log buffer referenced by the log retrieval pointer; transmit the retrieved log data to the host; advance the log retrieval pointer by a size of the retrieved log data; and responsive to determining that at least a part of log data has been overwritten in the log buffer, set the log retrieval pointer to match the write pointer.

The application discloses a real-time collection and intelligent processing method of communication data, which comprises the following steps: immediately storing the data received by a bottom interrupt service program into a bottom temporary data buffer area in a first-in first-out order; setting a double circular buffer area in an application layer, and adopting a read-write pointer separation mechanism to avoid resource competition; reading the bottom data by the application layer through a periodic task, and storing the data into a first circular buffer area after frame boundary detection and integrity check; carrying out packet sticking segmentation, packet recombination and secondary check on the data in the first circular buffer area, and storing the effective data into a second circular buffer area for use by an upper layer. The system corresponds to a bottom interrupt module, a bottom temporary data buffer area and an application layer module comprising a double circular buffer area and a data processing unit. The application eliminates the processing delay of a traditional method, avoids resource competition during multi-task access, significantly improves the real-time performance and reliability of data reception, has good universality and expansibility, and is easy to realize in an embedded system.

The invention provides a heterogeneous computing system, a server and a heterogeneous computing method. The system comprises a server and a computing device, the server and the computing device share a data queue, and a shadow variable is arranged in the server; the server comprises n threads; when K threads in the n threads concurrently add messages to the data queue, the K threads are configured as follows: the K threads seize shadow variables through atomic operation respectively, when any one thread in the K threads successfully seize the shadow variables through the atomic operation, the shadow variables are updated, and when the shadow variables are not successfully seized through the atomic operation, the shadow variables are updated; the thread which successfully preempts the shadow variable can write the message into a sequence queue, and after the message is written into the data queue, the value of a write pointer of the data queue is updated according to the updated shadow variable; a thread in a computing device is configured to read a message from a data queue for processing, and after reading the message, update a value of a read pointer of the data queue. The performance of the heterogeneous computing system can be improved.

The application relates to a used ring updating method and module, a backend device, a medium, a device and a chip, and comprises the following steps: when receiving packet updating information of any queue, storing the packet updating information into a storage unit; if the number of the packet updating information of the queue in the storage unit is equal to n, generating a first write request and a second write request according to the n packet updating information, and sequentially sending the first write request and the second write request to a DMA processing module, so that the DMA processing module writes pointer values and data packet lengths of the n packet updating information into the used ring table according to the first write request, and writes the index of the last received packet updating information in the n packet updating information into the used ring table according to the second write request. According to the application, the data packet receiving speed is improved.

The present disclosure provides a data transmission method of a laser processing system, comprising: generating processing data of the laser processing system according to parameters of the laser processing system and a preset processing task; receiving writable state processing data in an alternating manner through multiple receiving buffers, wherein at any time, only one receiving buffer in the writable state multiple receiving buffers is in a writable state, and the other receiving buffers are in a readable state; writing the processing data in the receiving buffer in the readable state into sequentially arranged storage units, the writable state sequentially arranged storage units are provided with a write pointer and a read pointer, and the writable state write pointer and the writable state read pointer automatically return to the starting end when reaching the end of the storage unit sequence; reading the processing data from the writable state sequentially arranged storage units and processing the same to drive the laser processing system to process. The present disclosure realizes the coordinated matching between the processing data receiving process and the processing execution process.