Data-caching access method and data-caching controller

A data cache and controller technology, applied in the field of data processing, can solve the problems of limited memory capacity and high memory price, and achieve the effect of utilizing memory resources

Active Publication Date: 2015-12-23
FUZHOU ROCKCHIP SEMICON
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In the process of realizing the present invention, the inventor found that the following problems exist in the prior art, the above-mentioned memory is relatively expensive
With the refinement of industrial division of

Method used

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Embodiment Construction

[0048] In order to explain in detail the technical content, structural features, achieved goals and effects of the technical solution, the following will be described in detail in conjunction with specific embodiments and accompanying drawings. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. It may be evident, however, that such aspects may be practiced without these specific details.

[0049] Here is a list of some terms:

[0050] FIFO: Abbreviation of FirstInputFirstOutput, first in first out queue

[0051] r_clk: read clock signal

[0052] read_ReadAddr_done: read read address completion signal

[0053] read_data_done: data read completion signal

[0054] readAddr_valid: read address valid signal

[0055] readAddr: read address signal

[0056] read_int: read interrupt signal

[0057] w_clk: write clock signal

[0058] read_writeAddr_done: Read and wr...

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Abstract

The invention provides a data-caching access method and a data-caching controller and relates to the field of data processing, in particular to data caching. According to the data-caching access method and the data-caching controller, a segment of continuous storage space is distributed in a shared storer and used for conducting first-in-first-out data caching, a head address pointer of the controller points to a head address of the storage space, a tail address pointer points to a tail address of the storage space, the value of a write pointer is the value of the head address pointer, the value of a read pointer is the value of the head address pointer, and the storage space is initialized into a data-caching queue; read-write units are the minimal units of read-write operation of the storage space, and the length of the storage space is the number of the read-write units in the storage space. The controller can be well adapted to different program development and operation requirements, and storer resources can be utilized sufficiently.

Description

technical field [0001] The invention relates to the field of data processing, and in particular to data cache. Background technique [0002] FIFO (First In First Out Queue) is a device widely used in electronic systems. How FIFO works is available figure 1 To represent. Please refer to figure 1 , the usual FIFO device includes a dedicated memory and FIFO read and write control circuit, the size of the memory is allocated and set in the early stage of hardware design, the read and write control circuit is used to generate full signal and read and write data in the memory according to the address. During the process of implementing the present invention, the inventors found that the prior art has the following problems, the price of the above-mentioned memory is relatively high. With the refinement of industrial division of labor, hardware design and software design are usually completed by different institutions or company organizations, so the memory capacity at the init...

Claims

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Application Information

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IPC IPC(8): G06F12/08
Inventor 罗宁
Owner FUZHOU ROCKCHIP SEMICON
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