19 results about "Virtual Output Queues" patented technology

Devices, systems, methods, and processes for fabric congestion management are described herein. At each ingress switch, virtual output (“VO”) queues are created for egress ports based on identifiers, state indicators, and encapsulation values of the egress ports received via an Ethernet Virtual Private Network (“EVPN”) control plane. When a data packet is received at the ingress switch, an egress port for the data packet is determined, an identifier and an encapsulation value of the egress port are added to the data packet, and the data packet is stored in a corresponding VO queue. The data packet remains at the ingress switch until an egress switch is available. At the egress switch, one or more tags are added in the data packet based on the encapsulation value, whereas the destination egress port is identified based on the identifier. Thus, a quick egress through the egress switch is achieved.

The invention discloses a multi-input multi-output routing scheduling device, which comprises an input port module used for acquiring transaction data in real time, analyzing the transaction data to obtain a destination address, and caching the transaction data to a corresponding virtual output queue according to the destination address of the transaction data, when the transaction data volume cached in any virtual output queue reaches a preset data sending threshold value, a transmission request is sent to an output port module matched with the virtual output queue; the output port module is used for arbitrating at least one transmission request sent by each input port module in a set time interval to obtain a target virtual output queue located on a target input port module, and continuously reading a set number of complete data sequences from the target virtual output queue on the target input port module and sending the complete data sequences. According to the device disclosed by the invention, the utilization rate of cache resources is improved, and the condition of data congestion is effectively relieved.

The invention discloses a multi-channel intermediate frequency signal high-speed acquisition and storage system, relates to the technical field of high-speed signal acquisition, and aims at acquiring and storing high-speed multi-channel intermediate frequency signals, redirecting frames to a management side virtual port, combining strict priority queuing, preferentially transmitting through a virtual output queue and eliminating the problem of queue head blockage. Dynamically adjusting a priority threshold and phase correction by means of a fuzzy reasoning model by using a queue slope and a synchronous drift index; if the adjustment coefficient exceeds a preset threshold value, the latest cache configuration is applied and an exception is reported, so that the stability and high fidelity of data acquisition and storage are ensured; the flow capturing precision is improved through micro-burst detection, hard isolation is achieved through control frame redirection, abnormal accumulation is prevented through a virtual output queue, meanwhile, the reliability is enhanced through a self-healing mechanism, and the timeliness of a control frame and the stability of the overall performance can be guaranteed in high-speed data processing.

A Network on Chip (NoC) includes a plurality of shared buffers configured to manage arriving flits with a plurality of logical queues, each of the plurality of logical queues configured to manage the arriving flits according to a virtual channel of an input port associated with the arriving flits and an output port corresponding to the arriving flits. A first set of arbitration logic is configured to output arbitration of flits from the plurality of logical queues to a second set of arbitration logic. The second set of arbitration logic is configured to arbitrate output flits from the first set of arbitration logic to the output port. Additionally, the configuration of the shared buffers with two-set of arbitration logic provides efficient arbitration of data transmission.

A network device includes a switching system for directing packets between ingress ports and egress ports of the network device. The network device also includes a switching system manager that makes an identification of a state change of a virtual output queue of the switching system; and performs an action set, based on the state change, to modify a latency of the virtual output queue to meet a predetermined latency in response to the identification.

The invention provides a packet loss statistical method and equipment. According to the method, virtual output queues VOQ with the number equal to the priority queue number N are created for each physical port in sequence; recording a physical port mapped by each VOQ and a priority queue; reserving M * (M * N) counter entries of the hardware statistical engine; sequentially distributing each segment of M * N continuous counter entries of all reserved counter entries to each physical port and binding one VOQ one by one; setting a packet loss count matching condition of each VOQ, and setting the packet loss count matching condition of each VOQ to each counter entry which is bound one by one; locating a counter entry segment corresponding to the dropped message that arrives at the physical port; in the positioned counter entry segment, counter entries corresponding to the VOQ caching the discarded message are reversely checked; the packet loss reason of the discarded message is consistent with the packet loss counting matching condition of the counter entry of the reverse check, and the current counting value of the counter entry of the reverse check is added by one.

This invention discloses a user-space virtual output queue and traffic weaving scheduling method and system, belonging to the field of network switching and programmable data plane technology. It generates a set of scheduling attributes through data plane classification, maps them to virtual output queue identifiers, constructs corresponding queues in user space to complete enqueueing, and executes scheduling and allocation according to a preset strategy. It supports switching between multiple modes, including bypass, shadow observation, and active scheduling, and simultaneously realizes hot update state migration and gray-scale switching of data plane module chains. It also dynamically optimizes operating parameters based on statistical feedback. This invention solves the core problems of existing technologies, such as strong reliance on hardware queues for scheduling capabilities, disconnect between software queues and data plane classification, poor consistency of hot updates of data plane modules, and high risks associated with deploying new strategies. It significantly reduces hardware dependence, achieves fine-grained traffic scheduling on ordinary network interface cards, and improves the deployment flexibility, online security, and operational stability of data plane systems. It is suitable for various scenarios such as edge switching, quality of service control, and traffic isolation.

This application provides a forwarding method and apparatus. The method includes: receiving a first original message sent by a first server, the first original message including a first destination IP address; obtaining a first forwarding table entry from a first forwarding table based on the first destination IP address, the first forwarding table entry including a system interface identifier; obtaining a first virtual output queue list entry from a virtual output queue list based on the system interface identifier, the first virtual output queue list entry including a first outgoing interface, the first interface indicated by the first outgoing interface being a first virtual output queue identifier; storing the first original message in a first virtual output queue indicated by the first virtual output queue identifier; and broadcasting a first service message, including a system interface identifier, to multiple NCFs through the first virtual output queue when the first virtual output queue is currently in a polling cycle.

The invention belongs to the technical field of satellite communication and network switching, particularly relates to a low-orbit constellation high-speed switching method based on an FPGA (Field Programmable Gate Array), and aims to solve the problems of low cache utilization rate, difficulty in scheduling time sequence convergence and single event upset dead lock of spaceborne switching equipment in a resource limited and intense radiation environment. The method is applied to a switching system constructed by an FPGA (Field Programmable Gate Array), the switching system comprises an input module, an output module and a switching core, and the switching core adopts a data and control separation architecture of a local shared data pool and a virtual output queue. After the data frame is subjected to verification and fixed-length slicing, dynamic multiplexing of storage resources is realized through address pointer circulation; an availability mask is introduced into an exchange core, and cycle-by-cycle continuous output of a scheduling decision is realized through a three-stage assembly line; and the self-healing controller triggers hierarchical reset through state verification, so that deadlock is avoided. The method does not need to depend on external storage, on-chip resource consumption is reduced, line-speed forwarding is achieved, logic soft errors can be automatically repaired, the throughput performance, scheduling timeliness and on-orbit survivability of a low-orbit satellite network are remarkably improved, and the method adapts to satellite-borne environment harsh constraints.

Techniques and architecture are described for a method, implemented within a Clos configured backend network of a web scale network includes registering, with a distributed service control plane, a plurality of egress endpoints and status of the egress endpoints, and distributing, by the service control plane to a plurality of ingress virtual output queues (VOQs), registration information relating to the plurality of egress endpoints. The method also includes based at least in part on the distributing, scheduling packets for transmission from the plurality of ingress VOQs to the plurality of egress endpoints and forwarding, by the plurality of ingress VOQs to the plurality of egress endpoints, packets. The method may also include updating the registration information.

Technology for a device includes a plurality of digital signal processors (DSPs) and a plurality of analog crossbars in communication with the DSPs. The DSPs dynamically adjust queues to optimize data flow based on traffic conditions, latency, and resource availability. Queues may include input queues, output queues, virtual output queues, or hybrid configurations, supporting techniques such as priority scheduling and time-division multiplexing (TDM). The DSPs facilitate flow control through granular backpressure signaling, managing congestion between DSPs and endpoints. Synchronization of queues during crossbar reconfiguration ensures seamless traffic flow and prevents data loss. Advanced mechanisms, such as dynamic queue depth adjustment and adaptive prioritization, enable efficient resource sharing while maintaining high throughput. The device leverages these features to provide scalable, energy-efficient networking solutions for complex environments, such as data centers and telecommunication system

The embodiment of the invention discloses a shared cache switching structure-oriented self-adaptive feedback regulation system and electronic equipment. According to one specific embodiment, the system comprises a credit overtime monitoring component which is deployed at an output port and is used for performing credit overtime monitoring on PCIe messages; the threshold value dynamic self-adaptive component is used for dynamically adjusting a threshold value parameter corresponding to the credit overtime monitoring component; the queue dynamic speed regulation assembly comprises a dynamic speed reduction assembly and a dynamic acceleration assembly, and the queue dynamic speed regulation assembly is deployed at the input port and is used for performing dynamic sending rate control on a virtual output queue corresponding to the input port in the shared cache exchange structure; the dynamic speed reduction assembly is used for slowing down the sending rate of the virtual output queue, and the dynamic acceleration assembly is used for accelerating the sending rate of the virtual output queue. According to the embodiment, advanced sensing and processing of the head-of-queue congestion are realized.

The invention relates to the technical field of data switches, and discloses a data center and cloud computing switching method and a switch, and the method comprises the steps: analyzing east-west data traffic to obtain traffic feature information, and deploying a Spine layer controller, a Leaf layer controller and a ToR layer controller of a data center network; performing virtual output queue mapping based on a tenant identification field in the traffic feature information to obtain a bandwidth quota scheme; in the Spine layer controller, east-west flow prediction is carried out in combination with a bandwidth quota scheme, and a global path planning scheme is obtained; a scheduling instruction is created in the Leaf layer controller according to the global path planning scheme, the scheduling instruction is sent to the ToR layer controller for synchronization, and a cooperative exchange control result is obtained, the problems of single-point faults and expansibility of a centralized controller are solved, state synchronization of a distributed control system is ensured, and global convergence and optimality are ensured.

A controller for performing command scheduling, a storage device including the same, and an operating method of the same are provided. The storage device communicates with a host device that generates an original data packet. The storage device includes a memory device and a controller, the memory device including a die having a plurality of planes. The controller includes an operation checker that receives the original data packet indicating a simultaneous parallel work request occupying at least two planes among the plurality of planes, wherein the operation checker sets a simultaneous parallel identifier associated with the original data packet to generate a modified data packet, an operation allocator that stores the modified data packet in at least one virtual output queue in a virtual queue cluster, and a scheduler that transmits the modified data packet to at least one plane occupied by the simultaneous parallel work request among the plurality of planes according to a scheduling policy.

This invention proposes a high-efficiency multi-port parallel shared cache management system for switches. It supports the formation of an SRAM array from m SRAM controllers, with unified management and allocation of page base addresses to achieve shared cache. It fully utilizes multiple read / write ports of multiple SRAMs, enabling the switch's input / output ports to access multiple SRAMs in parallel. The total bandwidth is calculated as: SRAM bit width × frequency × utilization rate × m. This invention includes a dynamic non-blocking polling master-slave state machine, allowing it to query other ports without blocking while serving one port, improving overall efficiency. It also includes a priority virtual output queue organized in a linked list format. All output ports share descriptor linked list nodes, achieving 100% utilization of the shared cache. Ports needing to store more descriptors can request more descriptor linked list nodes, while idle nodes are used by other ports, improving shared cache utilization and reducing resource waste.

In one embodiment, the quasi-output-queue behavior of a packet switch is implemented using virtual output queue (VOQ) ordering determined independently for each particular output queue (OQ), including using maintained latency information for the VOQs of a particular OQ. In one embodiment, all packets from all VOQs with the same port priority destination experience similar latency within a particular time window, similar to the packet service provided by an output-queue switch fabric. In one embodiment, all input ports sending traffic to the same output port priority receive bandwidth proportional to their bandwidth demand divided by the total bandwidth. Existing methods to simulate the performance of an OQ switch fabric require complex and time-consuming scheduling determinations, and do not scale. Independently determining the order in which to send packets from the VOQs associated with each particular OQ provides quasi-output-queue behavior to a system that is scalable and implementable.

A networking device controls transmission to an egress port with a virtual output queue using credits received from an egress scheduler. Credits may be requested at various rates based on the size of the virtual output queue. To optimize latency and prevent unused credits, the thresholds for changing the requested credit rates is determined based on the credit rate and the round-trip time from the virtual input queue to the egress scheduler. This ensures that when incoming data to the virtual output queue ends, the scheduler does not issue credits faster than the virtual output queue can signal changes to the effective credit rates.

The invention discloses an extensible high-concurrency data cache management system, solves the problem of how to realize extensible, high-concurrency and non-blocking cache, and belongs to the crossing field of integrated circuit design and computer network communication technology. The system comprises a plurality of input port service subsystems and a plurality of output port service subsystems which are independently parallel, and configurable expansion of the number of the input port service subsystems and the number of the output port service subsystems is realized through independent chip selection signal control enabling; the input port service subsystem is used for receiving a data stream from a physical port and carrying out preprocessing and protocol analysis; the scheduling subsystem is used for being responsible for scheduling decision and virtual output queue management of the data packets and realizing multi-level QoS (Quality of Service) scheduling; the cache subsystem is used for data packet storage, address allocation, multicast support and memory recovery; and the output port service subsystem is used for reading the data from the cache and sending the data to the physical port. The method supports an error checking and correcting mechanism.