Embodiments of the present invention provide an optical network and switch architecture that provides non-blocking routing from an ingress router to an egress router in the network on a port-to-port basis. The present invention provides routing for fixed and variable length optical data packets of varying types (including Internet Protocol (IP), data, voice, TDM, ATM, voice over data, etc.) at speeds from sub-Terabit per second (Tbps), to significantly in excess of Petabit per second (Pbps). The present invention includes the functionality of both large IP routers and optical cross-connects combined with a unique, non-blocking optical switching and routing techniques to obtain benefits in speed and interconnected capacity in a data transport network. The present invention can utilize a TWDM wave slot transport scheme in conjunction with a just-in-time scheduling pattern and a unique optical switch configuration that provides for non-blocking transport of data from ingress to egress.One embodiment of the present invention includes a router comprising an ingress edge unit with one or more ports and an egress edge unit with one or more ports connected by a switch fabric. The ingress edge unit can receive optical data and convert the optical data into a plurality of micro lambdas, each micro lambda containing data destined for a particular egress edge port. The ingress edge unit can convert the incoming data to micro lambdas by generating a series of short-term parallel data bursts across multiple wavelengths. The ingress edge unit can also wavelength division multiplex and time domain multiplex each micro lambda for transmission to the switch fabric in a particular order. The switch fabric can receive the plurality of micro lambdas and route the plurality of micro lambdas to the plurality of egress edge units in a non-blocking manner. The router can also include a core controller that receives scheduling information from the plurality of ingress edge units and egress edge units. Based on the scheduling information, the core controller can develop a schedule pattern (i.e., a TWDM cycle) to coordinate the time domain multiplexing of micro lambdas at the plurality of ingress edge units and non-blocking switching of the micro lambdas at the switch fabric.