13results about How to "Save bandwidth" patented technology

The application relates to the technical field of semiconductor chip packaging, and discloses a lead frame structure and a packaging structure for SOW10 packaging of a Hall current sensor chip, which comprises a lead frame base island, the thickness of the lead frame base island is greater than that of a conventional SOW16 lead frame base island, so as to compensate for the loss of the cross-sectional area of the original side current path caused by the reduction in the number of pins in a first pin group; the lead frame pins comprise a first pin group and a second pin group; the first pin group is directly arranged on the lead frame base island and is electrically connected to the lead frame base island, is located at the opposite side of the side where the protruding part is located, and is used for leading in and out the original side current; the second pin group is connected to a die through a lead wire; an isolation device is arranged between the die and the lead frame base island, and the isolation device completely covers the area where the lead wire passes through the lead frame base island on a projection plane. The application provides the lead frame structure with lower conduction resistance, and the structure has lower conduction impedance.

The application discloses an interactive form design method and system based on a language large model, and belongs to the technical field of human-computer interaction and form automatic generation. In view of the problems that a traditional form design tool is tedious to operate, highly depends on manual experience, and an existing method based on a large model has high training cost, weak interaction ability and difficulty in real-time collaboration, the following scheme is used for improvement: defining a JSON Schema specification of a form and constructing a visual form designer, integrating a language large model interaction entrance in an interface, dynamically assembling a request containing user instructions, a JSON Schema specification and existing form data according to whether the form is empty, and submitting the request to the language large model; receiving a response in a streaming manner, and real-time analyzing and progressively updating a form designer preview interface, so that a user can directly generate or modify a form through natural language instructions, and multi-round interaction and manual subsequent adjustment are supported. The method is mainly used for reducing a form design threshold, improving design efficiency and intelligent collaboration level.

The application relates to the technical field of computers, in particular to the field of artificial intelligence, and provides a message forwarding method and device, electronic equipment and a storage medium. The method comprises the following steps: based on forwarding information of a to-be-processed message, querying a matched address table entry in a first address table of an initial board card in a network device; in the case that no address table entry is queried in the first address table, based on the forwarding information, querying a matched address table entry in a second address table of a switching network board in the network device; in the case that the matched address table entry is queried in the second address table, forwarding the to-be-processed message through a target forwarding port in the matched address table entry. Since the switching network board of the application can also be used for address table entry query, flooding forwarding is reduced, system bandwidth is further saved, and the hardware resource utilization rate is improved.

The application discloses a point cloud information processing method, device and equipment and a storage medium, and comprises the following steps: acquiring current point cloud frame data, wherein the current point cloud frame data comprises three-dimensional coordinate information of a plurality of point clouds; performing two-dimensional space mapping processing on the three-dimensional coordinate information of the plurality of point clouds to obtain a current depth image corresponding to the current point cloud frame data; comparing the current depth image with a previous depth image to obtain a frame difference image, wherein the previous depth image is a depth image corresponding to previous point cloud frame data adjacent to the current point cloud frame data; determining a target sending image from the current depth image and the frame difference image with smaller data quantity; and sending the target sending image to an image rendering module. The application can effectively reduce the data quantity of point cloud data, facilitate the storage and sending of point cloud data, and ensure real-time transmission of point cloud data.

This invention discloses a wafer-level chip, board, and electronic device. The wafer-level chip includes multiple computing blocks, each computing block including a switching node and multiple computing nodes distributed around the switching node. The multiple computing nodes in the computing block and the switching node are interconnected through a first network, which includes a ring network and a star network. The multiple computing nodes in the computing block are interconnected through the ring network, and the switching node in the computing block is interconnected with the multiple computing nodes through the star network. The switching nodes of the multiple computing blocks are interconnected through a second network. The bandwidth of the first network is less than the bandwidth of the second network. The wafer-level chip provided by this invention can achieve a balance between bandwidth and latency under the premise of high bandwidth and low latency, and can significantly improve robustness in the event of node failure.

This invention proposes a message uploading method and a distributed switch stacking system, relating to the field of communication technology. The CPU of the slave device's MPU card determines the destination board based on the load parameters of all LPU cards and SFU cards of the master device and returns the information to the switching chip of the slave device's source LPU. The switching chip of the slave device's source LPU card adds a private encapsulation to the message to be processed using the destination board's information and a preset identifier, and determines the outgoing port according to the forwarding path table pre-issued by the slave device's MPU card CPU. The message is then forwarded across cards via the data channel until it reaches the switching chip of the destination board. The switching chip of the destination board decapsulates the encapsulated protocol message to recover the message to be processed, and the destination board's CPU uploads it to the master device's MPU card CPU. This allows the message to be processed from the slave device to reach the master device's MPU card CPU with only one CPU-to-CPU forwarding, reducing latency, saving control channel bandwidth and CPU resources, and improving the overall system performance.

This invention relates to the fields of medical informatics and data communication technology, specifically a CRRT online acquisition and intelligent monitoring system based on HL7. The system includes: a protocol cleaning and state mapping step: parsing the private protocol binary stream based on a virtual device state machine model to extract the device operating status and monitoring value vectors; a differential semantic analysis step: calculating the rate of change and deviation vector of the monitoring value vector relative to the historical time window; an adaptive message encoding step: selectively generating incremental maintenance messages or full semantic messages based on the comparison results of the rate of change and semantic fluctuation threshold; and a hybrid channel transmission step: dynamically allocating transmission channels and error correction coding strategies according to the message type to execute transmission. This invention solves the transmission contradiction between the real-time nature of high-frequency vital sign data and the redundancy of standardized protocols, balancing standard compatibility and real-time alarm capabilities under limited network conditions.

This utility model discloses a millimeter-wave broadband impedance modulation power amplifier based on a bandpass structure, including a microwave composite board, signal input terminals VIN+ and VIN-, a first MOSFET 5XM1, a second MOSFET 5XM1, a first neutralizing capacitor CN, a second neutralizing capacitor CN, a first signal output terminal Vout-, and a second signal output terminal Vout+. The signal input terminals VIN+ and VIN- are electrically connected to the gates of the first MOSFET 5XM1 and the second MOSFET 5XM1, respectively. The two ends of the first neutralizing capacitor CN are electrically connected to the gate of the first MOSFET 5XM1 and the drain of the second MOSFET 5XM1. The two ends of the second neutralizing capacitor CN are electrically connected to the gate of the second MOSFET 5XM1 and the drain of the first MOSFET 5XM1. The first signal output terminal Vout- is electrically connected to the drain of the first MOSFET 5XM1, and the second signal output terminal Vout+ is electrically connected to the drain of the second MOSFET 5XM1. The technical solution of this utility model can achieve the goals of Ku / Ka band relative bandwidth ≥15%, 6dB backoff efficiency ≥25%, and cost reduction of more than 30%.

The embodiment of the application provides a data encapsulation processing method and device, a storage medium and an electronic device. The method comprises the following steps: determining the positional relationship between a GSE fragment and a sending unit; obtaining an optimization field in the GSE fragment according to the positional relationship; reducing part of the fields in the GSE header of the GSE fragment according to the optimization field to obtain a target GSE fragment after reduction; and encapsulating the target GSE fragment. The method can solve the problems in the related art that the same packet header compression is required to save the transmission link bandwidth, the packet header in the transmission frame needs to have the same encapsulation structure, and a PDU data needs to be sent by multiple sending units. By reducing part of the fields in the GSE header of each sending unit of the PDU, the length of the GSE header of each sending unit can be reduced, thereby saving the transmission link bandwidth.

This application provides a hardware device and method for memory management based on address monitoring. The CPU encapsulates the preset storage address of the pre-received data or the storage address of the already stored data in memory, along with other data information, into a descriptor, and stores the descriptor in memory via the system bus. The system bus can monitor and record the write address signals of the descriptors in memory. The DMA controller can monitor the write address signals of the descriptors recorded on the system bus, determine the number of descriptors based on the monitored write address signals, and update the number of descriptors in the register set. The processing module can retrieve the corresponding descriptor from memory based on the updated number of descriptors and perform data writing or data reading based on the descriptor. In this scheme, the DMA controller can monitor the write address of the memory descriptors through the system bus to know the accurate allocation of descriptors, ensuring that the descriptors have been allocated before updating the register set and triggering the descriptor retrieval operation.

A basic memory cell management circuit and a basic memory cell management method are disclosed. The basic memory cell management circuit includes a receiving circuit, a transmitting circuit, a first buffer, and an idle basic memory cell controller. The first buffer stores a bit table, wherein the bit table includes a plurality of first bits, each corresponding to a plurality of basic memory cells, and each of the plurality of first bits is used to indicate whether a corresponding basic memory cell is an idle basic memory cell. The idle basic memory cell controller is coupled to the receiving circuit, the transmitting circuit, and the first buffer, and is used to manage the bit table stored in the first buffer, and to process at least one basic memory cell corresponding to at least one packet received by the receiving circuit or transmitted by the transmitting circuit according to the bit table.

The application discloses a reconfigurable target detection coprocessor and method based on RISC-V, relates to the technical field of embedded artificial intelligence and computer architecture, and is connected with a RISC-V main processor and a system on chip (SoC) memory, wherein the reconfigurable target detection coprocessor based on RISC-V, the RISC-V main processor and the SoC memory are integrated in a system on chip (SoC) chip; the application generates hardware configuration information through the RISC-V main processor, combines a dynamically reconfigured programmable data exchange network, realizes software definition of a hardware data path, enables a single hardware platform to efficiently accelerate support for multiple target detection algorithms with different structures, and improves flexibility and versatility of multi-target detection; and the data path dynamically reconfigured by the control unit ensures close coupling between basic computing units, eliminates idle resources caused by data flow mismatch in a fixed architecture, and significantly improves utilization of the basic computing units.