Adaptive router in NoC (network-on-chip) on basis of virtual output queue mechanism

A technology of virtual output queue and network on chip, which is applied in the application field of integrated circuit chip design, and can solve problems such as head blocking

Inactive Publication Date: 2016-08-17
HEFEI UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the network is not congested, the NoC uses VOQ routers and there is no head blocking problem. However, when the network is congested, even if VOQ routers are used, there is still a certain degree of head blocking problems in the network.

Method used

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  • Adaptive router in NoC (network-on-chip) on basis of virtual output queue mechanism
  • Adaptive router in NoC (network-on-chip) on basis of virtual output queue mechanism
  • Adaptive router in NoC (network-on-chip) on basis of virtual output queue mechanism

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Embodiment Construction

[0059] The network on chip is a two-dimensional grid structure composed of several routing nodes, several resource nodes and several routing channels. figure 1 Shown is a two-dimensional grid structure network on chip with a topology scale of 3*3;

[0060] Take the routing node on any vertex of the on-chip network as the origin O, such as figure 2 As shown, the two routing channels connected to the routing node on the vertex are X-axis and Y-axis respectively, and the coordinate system OXY is established; and the positive direction of the X-axis is the E direction, and the negative direction of the X-axis is the W direction, The positive direction of the Y axis is the N direction, the negative direction of the Y axis is the S direction; the direction connected to the resource node is the L direction; and the area between the N direction and the E direction is defined as the first quadrant; the N The area between the direction and the W direction is defined as the second quad...

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Abstract

The invention discloses an adaptive router in an NoC (network-on-chip) on the basis of a virtual output queue mechanism. The adaptive router comprises five input ports, a port selection module, a valve judgment module, a storage module, an or-onward routing computation module, a header fit modification module, a crossbar switch judgment module, a crossbar switch and five output ports; the input ports partition an input buffer space according to output directions of data packets so as to form virtual output queues; an idle bit of a header fit of each data packet is used for parenthetically propagating congestion information of the network; any one virtual channel is equally divided into two storage spaces each of which is respectively provided with one set of read-write pointer; on a routing computation hierarchy, the output ports are adaptively selected; and in one single virtual channel, the data packet is adaptively read. According to the invention, by adaptation of two hierarchies, traffic distribution of the whole network is balanced and congestion is relieved, so that a possibility of generating HOL (head of line) blocking is reduced; and when the HOL blocking is generated, influence of the HOL blocking is eliminated, so that delay of the network is reduced and throughput of the network is improved.

Description

technical field [0001] The invention belongs to the application technical field of integrated circuit chip design, in particular to an adaptive router based on a virtual output queue mechanism in an on-chip network. Background technique [0002] With the increasing demand for computing power in the system, more and more computing modules are embedded on a single chip, and the communication between modules needs to be supported by a high-bandwidth, low-latency interconnection network. Network-on-chip (NoC, Network- on-Chip) came into being. Due to the limitation of on-chip resources, the design of NOC faces many challenges, and congestion management is one of them. However, congestion itself is not a problem. The worst impact is the head-of-line blocking (HoL) problem caused by congestion. Only when the impact of head-of-line blocking is completely eliminated, the performance of the network can be guaranteed. [0003] To deal with the head blocking problem in NOC, it is nec...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/803G06F15/78
CPCG06F15/7807H04L47/125
Inventor 欧阳一鸣陈静雯蒋哲远黄正峰梁华国姜兆能李建华易茂祥
Owner HEFEI UNIV OF TECH
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