833 results about "Networks on chip" patented technology

The invention belongs to the field of switching chips, and relates to a message processing and transmitting device on a CXL switching chip, which comprises a CXL switching interface unit module, an annular topological network on chip and a CXL management unit module, the CXL switching interface unit module is used for receiving and analyzing messages of two sub-protocols, namely. Cache and. Mem, sent by CXL equipment directly connected to a CXL switching chip, then converting and packaging the messages into a message format conforming to the standard of the network on the circular topology chip, and further transmitting the messages through the network on the circular topology chip; and meanwhile, the CXL switching interface unit module also needs to receive the message from the ring topology network-on-chip, converts and packages the message into a corresponding CXL sub-protocol message format, and then distributes the message to other CXL equipment. The method has the characteristics of high bandwidth, low delay and multi-channel concurrency, and provides an efficient transmission channel for a large amount of memory data access scene; and the method has the advantages of high expandability, friendliness to chip back-end physics and the like.

Disclosed embodiments provide techniques for a networking with a network-on-chip (NoC) interface with subtopologies. A system-on-chip (SoC) is accessed. The SoC includes a plurality of logic blocks. A NoC topology is created. The NoC topology includes one or more subtopologies. The one or more subtopologies are based on a physical location of the plurality of logic blocks. Each subtopology includes at least one router. A location of the one or more subtopologies is optimized. The one or more subtopologies are coupled based on one or more communications protocols. A protocol running on the plurality of logic blocks is translated to the one or more communications protocols. Data is sent from a sending subtopology within the one or more subtopologies to a receiving subtopology within the one or more subtopologies.

The invention discloses a large model calculation acceleration chip architecture, and relates to the field of large models. Comprising a normalized network-on-chip, an interconnection transmission system, a storage control system and a calculation acceleration core, the storage control system is connected with the Memory video memory group and the external SSD memory based on different built-in storage controllers; the normalized network-on-chip reads on-chip model parameters of a target position based on the storage control system, sends the on-chip model parameters to the calculation acceleration core for calculation, restores on-chip model data, carries out off-chip interaction with an external management server based on the interconnection transmission system, receives an instruction task, reads and restores external model parameters, and sends the external model parameters to the calculation acceleration core for calculation. And performing inter-chip interaction with other computing acceleration chips based on an interconnection transmission system, and reading and restoring inter-chip model parameters. According to the scheme, the hybrid video memory computing chip architecture supports multi-parallel SSD direct connection access, the capacity is expanded at low cost under the condition of keeping the bandwidth, and high cost performance is kept for both large-scale parallel tasks and small-sized low-cost all-in-one machines.

The invention discloses an ANN accelerator system based on multi-core storage and calculation integration and a control method, and the system comprises an on-chip network module which serves as an interconnection channel between storage and calculation integration cores and is used for combining calculation results of the multiple storage and calculation integration cores; the synchronous main controller is used for sending an instruction to the decoder according to the process that the network-on-chip module combines the calculation results of the plurality of storage and calculation integrated cores; the decoder is used for receiving an instruction of the synchronous main controller and converting the instruction into a configuration parameter; the configuration register is used for storing configuration parameters and transmitting the configuration parameters to the asynchronous control module, the on-chip routing module and the storage and calculation integrated core; and the asynchronous control module is used for receiving the configuration parameters transmitted by the configuration register and performing time sequence control on the process of merging the calculation results by the network-on-chip module according to the configuration parameters. According to the method, storage and calculation integrated data flow control with reconfigurable parallelism is optimized, and the efficiency of neural network reasoning is greatly improved.

The embodiment of the invention provides a network-on-chip routing method and device, a storage medium and electronic equipment, and relates to the technical field of computers, and the method comprises the steps: determining a neighbor node of a first node according to a relation between the first node and a destination node; the first node is a sender of a data packet, and the destination node is a receiver of the data packet; and acquiring congestion information of the neighbor node, and selecting a transmission path of a data packet according to the congestion information. Therefore, the related neighbor nodes are selected according to the relationship between the first node and the target node, and the transmission path of the data packet is selected based on the congestion condition of the neighbor nodes, so that the network congestion problem is relieved through dynamic sensing and path selection, the path diversity is improved, the congestion is reduced, and the network congestion rate is improved. Therefore, the communication efficiency and the working performance of the network-on-chip are improved.

The embodiment of the invention provides a multi-core network-on-chip transaction processing system, method, device, medium and product, the multi-core network-on-chip transaction processing system comprises a plurality of clusters, each cluster comprises four processing cores, a slave node and a master node, each processing core is provided with a cache, each slave node is provided with a slave node, and each slave node is provided with a slave node; the slave node is provided with a private cache, and the slave node comprises a four-stage pipeline architecture; the slave node is used for processing a request transaction through the four-stage pipeline architecture and generating a target response message or target response message data under the condition that the request transaction is received, and the four-stage pipeline architecture is constructed based on different clock periods and is used for periodically processing the request transaction.

The embodiment of the invention provides a path sharing method, a network-on-chip and electronic equipment, the path sharing method is applied to the network-on-chip, the network-on-chip comprises a plurality of routing nodes, and each routing node is connected with at least one routing node. The two connected routing nodes are connected based on a data transmission path in a single transmission direction; the path sharing method comprises the following steps: in response to transmission data received by a current routing node, determining a next routing node of the current routing node in a plurality of routing nodes; wherein the current routing node is any routing node, which receives the transmission data, in the plurality of routing nodes, and the transmission data is entity data used for information transmission or configuration data used for parameter configuration; and transmitting the transmission data to the next routing node through the data transmission path based on a data transmission channel between the current routing node and the next routing node.

A tool is disclosed for using custom subnetwork description during generation and synthesis of the network, such as a network-on-chip (NoC). The tool allows for incremental synthesis and transformation of a deadlock-free NoC. The NoC topology is translated into an existing segment; reusing the existing segment in a new route and generating the deadlock-free NoC topology. The tool includes a machine learning model that is trained for synthesis and generation of the NoC and is capable of providing incremental synthesis. The model can also receive feedback from past or previous synthesis for further training of the model.

The embodiment of the invention provides a data transmission method and device based on a network-on-chip, electronic equipment and a readable storage medium. The method comprises the steps that a data packet is received, and a target routing node corresponding to the data packet is determined; determining a next-hop routing node corresponding to the routing node from the tree topology structure according to the receiving direction of the data packet and the position of the routing node in the tree topology structure; the tree topology structure is a structure for connecting configuration channels of the routing nodes; and sending the data packet to the next-hop routing node, so that the next-hop routing node determines the corresponding next-hop routing node until the next-hop routing node is the target routing node, sending the data packet to the target routing node, so that the target routing node performs configuration according to the data packet, and sending the configured data packet to the next-hop routing node, so that the next-hop routing node determines the corresponding next-hop routing node until the next-hop routing node is the target routing node. The bandwidth utilization rate during data transmission is improved, and the real-time performance of data transmission is improved.

The invention discloses a self-adaptive dynamic routing method and system for an NoC (Network on Chip), and relates to the technical field of routing management. Comprising the steps that the local congestion degree of each routing node is collected through a communication link, the global congestion degree is generated through a weighted average mechanism, each routing node integrates delay counters in the east direction, the west direction, the south direction and the north direction according to a local router, the delay counters are used for monitoring the time interval when adjacent data packets leave a buffer area in real time, and the global congestion degree is generated; taking a time interval of leaving a buffer area of adjacent data packets as output delay, spreading the output delay to neighbor routing nodes, calculating local congestion degree and global congestion degree of the routing nodes, generating all possible shortest paths and a candidate direction set corresponding to output directions according to addresses of a source routing node and a destination routing node, and sending the candidate direction set to the destination routing node; screening an optimal path through the local congestion degree and the global congestion degree in sequence; and when a plurality of equivalent paths exist, the routing direction is randomly selected to balance the network load.

The embodiment of the invention provides a simulation method and device of a network-on-chip, electronic equipment and a storage medium, and relates to the technical field of the network-on-chip. The method comprises the steps of obtaining network simulation structure parameters, task simulation distribution parameters and performance optimization conditions; acquiring a simulation task of the network-on-chip; acquiring the simulation scale of the network-on-chip; and based on a solver of the satisfiability model theoretical model, obtaining an optimal node physical topology simulation result corresponding to the simulation task in the simulation scale under the condition that the network simulation structure parameters, the task simulation distribution parameters and the performance optimization conditions are satisfied. On one hand, the design difficulty of the network-on-chip can be reduced; and on the other hand, the optimal node physical topology simulation result obtained through the solver of the satisfiability model theoretical model has relatively high accuracy, has relatively strong reference significance for the design of the network-on-chip, and is beneficial to improving the design efficiency of the network-on-chip and improving the design accuracy of the network-on-chip.

The embodiment of the invention provides a data transmission method and device of a network-on-chip, electronic equipment and a storage medium. The method comprises the following steps: dividing at least two computing nodes with spatial topology into multicast domains; determining a target node for receiving the first message; according to a target multicast domain to which the target node belongs, adding a multicast control field in the first message to obtain a target message; determining a first routing path outside the target multicast domain according to the multicast control field and a routing algorithm; transmitting the target message to the target multicast domain based on the first routing path; determining a second routing path in the target multicast domain according to the intra-domain mask field; and sending the target message to the target node based on the second routing path. In the embodiment of the invention, the routing path of each message can be directly determined according to the multicast control field added in the message, so that the design complexity of the network-on-chip is reduced, and the data payload proportion and the data transmission efficiency of the network-on-chip are improved.

The invention discloses a network architecture based on multi-core transmission, and relates to the field of integrated circuits. The network-on-chip module comprises at least one node ring consisting of M pipeline cascade routing nodes; adjacent routing nodes in adjacent node rings are cascaded according to a longitudinal depth pipeline to form a node matrix; n sending buffers and N receiving buffers are respectively arranged on the node ring on the outermost layer of the node matrix, and each sending buffer and each receiving buffer are respectively connected with the corresponding IP core through directly connected routing nodes; a routing algorithm based on a node matrix is built in the network configuration unit, a target IP core is determined according to data sent into the sending buffer by source IP core data, a node matrix is controlled to plan and generate a data transmission path, and data transmission is executed. The data buffer is added in the network-on-chip architecture, so that the data transmission path is shortened, the feedback is more timely, and the network bandwidth is larger; a routing node adds a data replication realization function to realize multicast and broadcast modes; and the interface complexity of the whole node matrix is reduced.

A self-optimizing and self-programming computing system (SOSPCS) design framework that achieves both programmability and flexibility and exploits computing heterogeneity [e.g., CPUs, GPUs, and hardware accelerators (HWAs)] is provided. First, at compile time, a task pool consisting of hybrid tasks with different processing element (PE) affinities according to target applications is formed. Tasks preferred to be executed on GPUs or accelerators are detected from target applications by neural networks. Tasks suitable to run on CPUs are formed by community detection to minimize data movement overhead. Next, a distributed reinforcement learning-based approach is used at runtime to allow agents to map the tasks onto the network-on-chip-based heterogeneous PEs by learning an optimal policy based on Q values in the environment.

The invention discloses a network-on-chip routing method and device, routing nodes, equipment, a medium and a product, and relates to the technical field of network-on-chip, and the method comprises the steps: firstly, screening the routing nodes through employing the input direction of a message, and limiting the selection range of the next-hop routing node; the relative position of the target routing node relative to the current routing node is determined, the routing nodes are further screened according to the relative position, and candidate routing nodes are determined; and determining a next-hop routing node according to the cache capacity and the input direction of the candidate routing node, and transmitting the message to be transmitted to the next-hop routing node to complete routing. The problem that the routing of the network-on-chip is easy to cause network message blockage or link failure of the network-on-chip can be solved. According to the method, an input direction is adopted to limit a selection range of a next-hop routing node, a relative position is adopted to determine candidate routing nodes, the next-hop routing node is determined in the candidate routing nodes based on cache capacity, and self-adaptive deadlock-free routing is realized.

The invention belongs to the technical field of routers, and particularly relates to an efficient SRAM (Static Random Access Memory) cache allocation and management system of an on-chip network router, which comprises an input decoding module, a buffer module, a data writing module, an SRAM module and a data reading module, the data writing module is used for writing the data packet into the SRAM module according to a chain table number distribution and recovery strategy; the SRAM module is used for storing the data packet in a specified memory block according to a memory allocation and recovery strategy; the data reading module is used for reading a corresponding data packet from the SRAM module according to a priority queue arbitration strategy; and the signal is transmitted to the output port. The priority queue arbitration strategy is adopted to ensure the priority output of high-priority data packets, the throughput and response time of the system are improved, and the method is particularly suitable for a high-load, multi-port and high-concurrency network environment.

The invention discloses a pulse neural network hardware accelerator and a data processing method, and the accelerator is characterized in that a low-power-consumption three-stage pipeline CPU module is used for receiving input data, scheduling an SNN network acceleration instruction, and sending the input data to an asynchronous edge SNN hardware accelerator module through a coprocessor interface; the asynchronous edge SNN hardware accelerator module comprises a pulse data encoding and decoding module, L neuromorphic kernels and an on-chip network, the pulse data encoding and decoding module encodes input data into a pulse form and sends the pulse form into the neuromorphic kernels, and the neuromorphic kernels are used for performing calculation based on the data in the pulse form; the network-on-chip is used for communication between the neuromorphic kernels, and the connection between neurons before and after synapses in the neuromorphic kernels is realized by adopting a synaptic cross array. According to the invention, the data processing acceleration performance can be greatly improved.

Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

The invention provides a network-on-chip transmission information arbitration method and related equipment, and belongs to the technical field of computers, and the method comprises the following steps: determining a request to be sent by a target node in each input direction in a current round of arbitration period, and obtaining a target set; determining a weight value corresponding to each to-be-sent request in a target set according to a fault state of a node closest to a target node in a message transmission path of the target request, a space idle number of a flit size, a historical request number in the same transmission direction and a historical weight value; the historical weight value is a corresponding weight value when the target node sends each to-be-sent request in the last round of arbitration period; and sorting the to-be-sent requests in the target set according to a sequence of the weight values from high to low so as to respond to the sorted to-be-sent requests by using a crossbar switch on the target node. According to the method, the technical problem that the flow load of the network-on-chip is unbalanced in the related technology can be solved.

The invention discloses a method for processing asynchronous pipeline control adventure based on a lock mechanism, which is characterized in that a processor adopts a three-stage pipeline processor, an external interrupt of the processor transmits interrupt information to a data processing center through a network-on-chip, and a processor core exchanges data with the network-on-chip through the data processing center; in the processor core, lock registers are arranged between instruction prefetching and decoding, between decoding and execution and between execution and memory access, the result of the first-stage lock register is realized based on a click asynchronous controller, and the input end of the first-stage lock register is AND with a pmt signal after XOR; and other levels of lock registers adopt branch structures, after the remaining instructions in the assembly line are executed, the site is saved, then all locks are opened, and at the moment, the instructions fetched in advance enter a decoding stage normally. The asynchronous clock-free circuit design is adopted, the problems of clock skew and the like are avoided, normal instructions in an assembly line are not affected, the value taking time is saved, and the potential of low power consumption and high performance is achieved.

The embodiment of the invention provides a congestion control method and device, electronic equipment and a storage medium, and relates to the technical field of congestion control. The method is applied to a network-on-chip, and the network-on-chip comprises a back pressure signal generator and a plurality of routing nodes. The routing node comprises a plurality of output ports and a plurality of input ports, and the method comprises the following steps: under the condition that a first output port of a first routing node is congested, a back pressure signal generator obtains a data main input port corresponding to the first output port from a link flow table of the first routing node; transmitting the back pressure signal from the main input port to a second routing node adjacent to the first routing node; based on the link flow tables of the second routing node and the other routing nodes, the back pressure signals are sent to the corresponding source routing nodes in sequence; and on the basis of the back pressure signal, the packet sending behavior of the equipment corresponding to the output port, receiving the back pressure signal, of the source routing node is subjected to flow limiting, and the congestion control speed is higher and more accurate.

The invention relates to the technical field of integrated circuit system-on-chip communication, and relates to a network-on-chip transmission method and device based on a dynamic parallel mechanism, and a medium. The method comprises the following steps: carrying out parallel transmission by adopting a control link and a data link which are separated; the control link and the data link are respectively provided with an independent packing module and an independent unpacking module; different transaction types are adapted through a dynamic message structure; dynamic subpackaging is carried out according to the data size during data link packaging; when the control link is unpacked, parameters are split through the Controldec module and are sent to the parameter receiving module; and when the data link is unpacked, the data link is controlled by a state machine, and the split data is transmitted into a data storage module. The invention aims to effectively reduce congestion, reduce power consumption and improve the transmission efficiency and the overall performance of the network on chip through parallel transmission architecture design, double-link parallel packet processing logic design and a composition structure of a dynamic message.

Techniques for interfacing electronics are disclosed. A system-on-chip is accessed. The system-on-chip includes a network-on-chip (NoC) topology. The NoC sub-topologies are based on a physical location of the plurality of logic blocks. A first sub-topology is coupled to a receiving block, wherein the coupling includes inserting an interfacing block. The interfacing block includes a digital PLL (DPLL). The first sub-topology sends to the interfacing block data and a first clock. The first clock is input to the DPLL and used as a reference clock. The DPLL generates a second clock that is used to save the data that was sent. The interfacing block forwards to the receiving block the second clock and the data that was saved. The second clock is used as the internal clock in the receiving sub-topology. The NoC communications includes packets. Additional interfacing blocks are instantiated as necessary.

The invention discloses a cross-chip communication method, a direct connection module and a system, which consumes virtual channel credit during arbitration and packet reorganization, supplements the virtual channel credit when unpacked and uploaded to a network-on-chip, ensures that packets are correctly interacted in cross-chip communication through the channel credit, and reorganizes the packets according to a CXS protocol in an arbitration mode. According to the invention, ordered transmission of a plurality of packets in one physical channel is realized, 'starvation 'can be effectively prevented, the packet of a certain virtual channel is effectively prevented from being indefinitely delayed, the bandwidth utilization rate is improved, and the delay and congestion risks of cross-core-particle communication can be reduced.

The invention discloses a server, a network-on-chip system and a message processing device and method, and is applied to the technical field of computers, the message processing device is arranged in the network-on-chip system, and the network-on-chip system further comprises a scheduling device and N processor cores serving as N request nodes; the scheduling device is respectively connected with the message processing equipment and the N request nodes; a cache is arranged in each of the N request nodes; n is a positive integer, and the message processing equipment comprises an addressing device, a directory control device, a message loading device, a message processing device and a message generating device, so as to form a five-stage pipeline structure. According to the scheme of the invention, the message processing equipment with a five-stage pipeline structure is arranged, so that the message processing efficiency among the multi-core processors can be effectively improved, the delay is reduced, and meanwhile, the cache consistency is also ensured.

The invention provides a post-silicon verification system and a post-silicon verification method. The post-silicon verification system comprises a first chip, a second chip and an off-chip memory bank, the first chip comprises a first on-chip network, a target module needing to be verified in a post-silicon verification stage, and a first inter-chip high-speed interface; a debugging interface is configured in the target module and is used for summarizing all debugging signals needing to be verified in the post-silicon verification stage in the target module; the first inter-chip high-speed interface is connected with a debugging interface of each target module through the first network-on-chip; the second chip comprises a second inter-chip high-speed interface and a second on-chip network; the second inter-chip high-speed interface is connected with the first inter-chip high-speed interface, and the second inter-chip high-speed interface is also connected with the off-chip memory bank through the second on-chip network; wherein the first chip is used for sending a debugging signal of each target module to the off-chip memory bank for storage through the second chip in a post-silicon verification stage.

The invention provides a processor chip with adjustable power consumption, which is integrated with a plurality of functional cores and a plurality of routers, all the routers are mutually connected to form an on-chip network, all the functional cores are mounted on the on-chip network to realize mutual communication, and the chip further comprises a power consumption management module, all the functional cores and all the routers are configured to be subjected to clock frequency adjustment by a power consumption management module, and the power consumption management module is used for adjusting the clock frequency of the processor chip based on a received frequency raising request from the functional cores and / or the routers; the clock frequency of the processor chip is adjusted based on a self-configured adjusting mechanism; wherein the power consumption management module is configured to support unified adjustment of clock frequencies of all the functional cores and / or all the routers, and independently adjust the clock frequencies of each functional core and each router; and the power consumption management module is mounted on the network-on-chip to realize communication with each router and each functional core.

A collaborative Network-on-Chip (NoC) development environment (CNDE) is accessed. The CNDE is based on cloud-native software. The CNDE enables graphical design of a NoC topology within a database. A first NoC sub-topology within the NoC topology is created within the CNDE. The creating includes coupling a first network initiator, a first router, and a first network target. A second NoC sub-topology within the NoC topology is generated within the CNDE. The generating includes coupling a second network initiator, a second router, and a second network target. An interfacing block is inserted within the CNDE, enabling two-way communication between the first NoC sub-topology and the second NoC sub-topology. The NoC topology is validated. The validating ensures that the first network initiator is coupled to the first and second network targets, and that the second network initiator is coupled to the first and second network targets.

The embodiment of the invention provides a memory access method and related equipment, and the method comprises the steps: obtaining a prefetch request which is a prediction request generated by a processor and an extraction request obtained by extracting a request sent to a network-on-chip by the processor; wherein the prefetching request at least comprises a memory address and control information; sending the prefetching request to a prefetching network; based on the prefetching request, reading prefetching data corresponding to the prefetching request from the memory; judging whether the memory address of the access request sent to the memory by the processor is matched with the memory address of the prefetching request or not; and if the memory address of the access request sent to the memory by the processor is matched with the memory address of the prefetching request, returning the prefetching data to the access request. The embodiment of the invention can improve the data transmission efficiency.

An integrated circuit includes logic circuits and a network-on-chip in a region of the integrated circuit. The network-on-chip is configurable to transmit at least two of user data, configuration data, and emulation data to the logic circuits. The network-on-chip is configurable to transmit the user data to and from the logic circuits during a user mode of the integrated circuit. The network-on-chip is configurable to transmit the configuration data to the logic circuits for configuring the logic circuits during a configuration mode of the integrated circuit. The network-on-chip is configurable to transmit the emulation data to and from the logic circuits during an emulation mode of the integrated circuit.