373 results about "Networks on chip" patented technology

A self-optimizing and self-programming computing system (SOSPCS) design framework that achieves both programmability and flexibility and exploits computing heterogeneity [e.g., CPUs, GPUs, and hardware accelerators (HWAs)] is provided. First, at compile time, a task pool consisting of hybrid tasks with different processing element (PE) affinities according to target applications is formed. Tasks preferred to be executed on GPUs or accelerators are detected from target applications by neural networks. Tasks suitable to run on CPUs are formed by community detection to minimize data movement overhead. Next, a distributed reinforcement learning-based approach is used at runtime to allow agents to map the tasks onto the network-on-chip-based heterogeneous PEs by learning an optimal policy based on Q values in the environment.

The invention discloses a pulse neural network hardware accelerator and a data processing method, and the accelerator is characterized in that a low-power-consumption three-stage pipeline CPU module is used for receiving input data, scheduling an SNN network acceleration instruction, and sending the input data to an asynchronous edge SNN hardware accelerator module through a coprocessor interface; the asynchronous edge SNN hardware accelerator module comprises a pulse data encoding and decoding module, L neuromorphic kernels and an on-chip network, the pulse data encoding and decoding module encodes input data into a pulse form and sends the pulse form into the neuromorphic kernels, and the neuromorphic kernels are used for performing calculation based on the data in the pulse form; the network-on-chip is used for communication between the neuromorphic kernels, and the connection between neurons before and after synapses in the neuromorphic kernels is realized by adopting a synaptic cross array. According to the invention, the data processing acceleration performance can be greatly improved.

The invention relates to the technical field of integrated circuit system-on-chip communication, and relates to a network-on-chip transmission method and device based on a dynamic parallel mechanism, and a medium. The method comprises the following steps: carrying out parallel transmission by adopting a control link and a data link which are separated; the control link and the data link are respectively provided with an independent packing module and an independent unpacking module; different transaction types are adapted through a dynamic message structure; dynamic subpackaging is carried out according to the data size during data link packaging; when the control link is unpacked, parameters are split through the Controldec module and are sent to the parameter receiving module; and when the data link is unpacked, the data link is controlled by a state machine, and the split data is transmitted into a data storage module. The invention aims to effectively reduce congestion, reduce power consumption and improve the transmission efficiency and the overall performance of the network on chip through parallel transmission architecture design, double-link parallel packet processing logic design and a composition structure of a dynamic message.

Techniques for interfacing electronics are disclosed. A system-on-chip is accessed. The system-on-chip includes a network-on-chip (NoC) topology. The NoC sub-topologies are based on a physical location of the plurality of logic blocks. A first sub-topology is coupled to a receiving block, wherein the coupling includes inserting an interfacing block. The interfacing block includes a digital PLL (DPLL). The first sub-topology sends to the interfacing block data and a first clock. The first clock is input to the DPLL and used as a reference clock. The DPLL generates a second clock that is used to save the data that was sent. The interfacing block forwards to the receiving block the second clock and the data that was saved. The second clock is used as the internal clock in the receiving sub-topology. The NoC communications includes packets. Additional interfacing blocks are instantiated as necessary.

The invention discloses a cross-chip communication method, a direct connection module and a system, which consumes virtual channel credit during arbitration and packet reorganization, supplements the virtual channel credit when unpacked and uploaded to a network-on-chip, ensures that packets are correctly interacted in cross-chip communication through the channel credit, and reorganizes the packets according to a CXS protocol in an arbitration mode. According to the invention, ordered transmission of a plurality of packets in one physical channel is realized, 'starvation 'can be effectively prevented, the packet of a certain virtual channel is effectively prevented from being indefinitely delayed, the bandwidth utilization rate is improved, and the delay and congestion risks of cross-core-particle communication can be reduced.

The invention provides a processor chip with adjustable power consumption, which is integrated with a plurality of functional cores and a plurality of routers, all the routers are mutually connected to form an on-chip network, all the functional cores are mounted on the on-chip network to realize mutual communication, and the chip further comprises a power consumption management module, all the functional cores and all the routers are configured to be subjected to clock frequency adjustment by a power consumption management module, and the power consumption management module is used for adjusting the clock frequency of the processor chip based on a received frequency raising request from the functional cores and / or the routers; the clock frequency of the processor chip is adjusted based on a self-configured adjusting mechanism; wherein the power consumption management module is configured to support unified adjustment of clock frequencies of all the functional cores and / or all the routers, and independently adjust the clock frequencies of each functional core and each router; and the power consumption management module is mounted on the network-on-chip to realize communication with each router and each functional core.

A collaborative Network-on-Chip (NoC) development environment (CNDE) is accessed. The CNDE is based on cloud-native software. The CNDE enables graphical design of a NoC topology within a database. A first NoC sub-topology within the NoC topology is created within the CNDE. The creating includes coupling a first network initiator, a first router, and a first network target. A second NoC sub-topology within the NoC topology is generated within the CNDE. The generating includes coupling a second network initiator, a second router, and a second network target. An interfacing block is inserted within the CNDE, enabling two-way communication between the first NoC sub-topology and the second NoC sub-topology. The NoC topology is validated. The validating ensures that the first network initiator is coupled to the first and second network targets, and that the second network initiator is coupled to the first and second network targets.

The invention provides an on-chip network router, and a transmission method and device for routing data in an on-chip network, and the router comprises a row module and a column module which are mutually independent physically, so as to achieve the dimension decoupling of a data flow; wherein each of the row module and the column module comprises a crossbar switch and an arbitration unit coupled with the crossbar switch; the arbitration unit is configured to execute an arbitration decision on only one request in a conflict-free request pair when the two input ports of the crossbar switch request to be connected to the two different output ports respectively to form the conflict-free request pair, and to execute an arbitration decision on the conflict-free request pair based on the result of the arbitration decision. A data path is automatically established for another request in the conflict-free request pair to achieve mirroring effect arbitration. The router adopts the row and column decoupling type architecture and is matched with a mirror effect arbitration mechanism, so that resource competition is effectively reduced, arbitration logic is simplified, and the throughput and efficiency of the network-on-chip router are improved.

A computer-implemented method includes loading a simplistic network-on-chip (NoC) topology that is fully routed, and performing reinforcement learning on the NoC topology to identify a sequence of topology transformations that will produce a more optimal NoC topology. Performing the reinforcement learning includes running a plurality of training sessions. Running each training session includes using a machine learning model to apply a set of transformations to the NoC topology according to a policy, computing a cost of the NoC topology after the set of transformations has been applied, and updating the policy in response to the cost.

The invention discloses an object routing node, a routing method and a network-on-chip. The object routing node comprises a first register and a second register, and the first register is configured to respond to the condition that a first message of a first type and a second message of a second type are received at the same time, select to store the first message and send the second message to the object routing node under the condition that a next routing node of the object routing node meets a scheduling condition. Providing the first message for a next routing node; the second register is configured to acquire the second message in response to the fact that the second message is not received by the first register and the anti-starvation mechanism is triggered, and the anti-starvation mechanism is configured to indicate that after the first register is vacant, the first register does not receive the first type of message until the second message is scheduled to the next routing node through the first register. According to the object routing node, the arbitration logic is reduced, and the resource overhead caused by the arbitration logic is greatly reduced.

The invention provides a node of a network-on-chip, a data transmission method of the node and the network-on-chip. A node of the network-on-chip comprises a control module, and a plurality of input ports and a plurality of output ports in east, south, west and north directions; the control module is configured to initiate a row broadcast through an east and / or west output port, wherein the row broadcast carries first data, a row broadcast identifier and a row storage mask; receiving a data packet of line broadcast initiated by other nodes through an east and / or west input port, forwarding the data packet, and determining whether to store data according to the line storage mask; initiating a column broadcast through a south and / or north output port, wherein the column broadcast carries second data, a column broadcast identifier and a column storage mask; and receiving a data packet of initiating column broadcast by other nodes through a south and / or north input port, forwarding the data packet, and determining whether to store data according to the column storage mask. According to the method, the efficiency of inter-network communication of the network-on-chip can be improved, the complexity of back-end implementation is reduced, and large-scale integration and optimization are facilitated.

The invention discloses an on-chip network system based on cache consistency, belongs to the technical field of computer network communication, and aims to solve the technical problems of global consistency flow overload, on-chip network scheduling delay, directory node load imbalance and too high core resource occupation of a traditional router architecture. Comprising a multi-core cluster, distributed directory nodes, a multi-channel network-on-chip and a hardware acceleration module, cores are connected through a bus, and local cache consistency is achieved based on an MSI protocol; a directory node divides a physical address space into a plurality of fragments based on an address hash fragmentation mechanism, each directory node maintains a sparse directory table, and when the length of a request queue of any directory node exceeds a set threshold value, a dynamic load balancing mechanism is triggered; the multi-channel network-on-chip provides a control channel, a data channel and a configuration channel, and each channel performs message scheduling based on a dynamic priority mechanism; and the hardware acceleration module is used for processing three types of consistent transactions.

A memory management communication interface for a network-on-chip and a DDR controller. The memory management communication interface is connected to a host by means of the network-on-chip, and is connected to a DDR memory chip by means of the DDR controller. The memory management communication interface comprises: a request processing module, configured to receive a request packet from the host by means of the network-on-chip, and verify the integrity of the data format of the request packet; a response processing module, configured to send an ID unlocking request to the request processing module; and an output control module, configured to receive a read acknowledgment packet from the request processing module and a response packet from the response processing module, and further configured to handle a situation where the read acknowledgment packet and the response packet are received simultaneously. The memory management communication interface can ensure the security of data during the transmission of requests of multiple hosts over the network-on-chip, thereby improving the performance of a multi-chiplet Internet system.

The invention discloses an on-chip network router implementation method based on a classification conflict-free bypass, and relates to the technical field of on-chip networks. Comprising the following steps: step 1, receiving a flit of a network on chip and extracting flit information; 2, performing classification bypass condition verification according to the extracted microchip information and the load condition, and outputting a path selection signal; step 3, processing a conflict-free microchip of which the bypass enable signal is equal to 1; 4, processing the microchip of which the bypass enable signal is equal to 0; according to the method, differentiated bypass admission rules are formulated by identifying the types of the data packets, the judgment strategy is dynamically adjusted in combination with the real-time network load, meanwhile, bypass state management is simplified, and efficient forwarding and power consumption optimization of conflict-free microchips are achieved.

A system-on-chip design method and apparatus, a system-on-chip, and an electronic device, the system-on-chip comprising: a network-on-chip, the network-on-chip comprising a network routing component, the network routing component being arranged in a top module; and a plurality of subsystem modules, wherein on-chip interconnection is realized among the plurality of subsystem modules through the network routing component.

The invention relates to the technical field of storage and calculation integration, in particular to a multi-core storage and calculation integration-oriented routing system and electronic equipment, the system comprises a plurality of storage and calculation integration cores, each storage and calculation integration core comprises a plurality of storage and calculation macro units, a plurality of direction output interfaces, an analysis network-on-chip and a router, and the storage and calculation macro units are bound with the direction output interfaces; the analysis network-on-chip analyzes the header information of the data packet to determine the target transmission direction of the data packet, and when the target transmission direction is the same as the position direction of the target core, the direction output interface outputs data to the target core; and the router is used for generating a target planning path according to the target transmission direction and the position direction of the target core when the target transmission direction is different from the position direction of the target core, and transmitting the data packet to the target core according to the target planning path. Therefore, the problems of congestion of high-parallel signal winding between the memory macro-cell and the route, blockage caused by improper matching of data transmission directions, low path planning efficiency and the like in the prior art are solved.

The invention provides a sparse adaptation circuit and a network-on-chip sparse data processing method, the sparse adaptation circuit is embedded between a network interface unit (NIU) and a router of an NoC system, and the sparse adaptation circuit comprises an input processing module, a compression engine and an output processing module; the sparse detection unit is used for performing real-time zero value detection on the data stream received from the network interface unit NIU to generate sparse identification information; the compression engine is coupled with the sparse detection unit and is used for carrying out dynamic compression coding on the data stream based on the sparse identification information; and the output interface is used for sending the processed data flow to a router in a format conforming to the network-on-chip protocol. In the network-on-chip, a hardware method is adopted to identify a data packet containing a large number of zero values in AI calculation and compress the data packet into a data packet only containing valid data, so that the problems of low transmission efficiency, waste of power consumption and the like caused by the fact that on-chip bandwidth is occupied by invalid data are avoided.

Network-on-chip (NoC) employing reinforcement learning (RL) operation (e.g., Q-routing) implemented in, or in part in, the routing elements of the NoC to improve the routing of data in the NoC using region-aware function and path-aware cost function, as estimates of congestion, that account for region contention, path contention, or a combination thereof. The routing elements beneficially consider the cost of a packet's remaining journey, which can improve local and global routing. The reinforcement learning agent at each router performs an update operation to share the global and regional congestion information with local neighbors.

The invention provides a method and a device for reducing power consumption of an on-chip network and electronic equipment. The method comprises the following steps: acquiring a current idle index of an on-chip network node based on multi-dimensional network state information of the on-chip network node in a current detection period; when the current idle index is in the first range, closing a clock of the on-chip network node after a preset time period; and when the current idle index is in the second range, directly closing the clock, predicting a future idle index of the on-chip network node in a future time period based on the historical idle index of the on-chip network node in the historical detection period, and adjusting the working parameter of the on-chip network node based on the future idle index. According to the invention, the power consumption of the network-on-chip can be reduced while the node operation of the network-on-chip is not influenced; the working parameters of the network-on-chip nodes are adjusted by predicting the future idle indexes of the network-on-chip nodes, and the power consumption of the network-on-chip can be further reduced.

The invention discloses a high-speed data transmission system based on a three-dimensional network-on-chip, and relates to the technical field of data transmission. In order to solve the problems of high diagonal communication delay, unreasonable node layout and poor heat dissipation of a traditional three-dimensional network on chip, the adopted scheme comprises a short connection 3D ScMesh topology module which is used for shortening the distance between nodes and reducing the communication delay through horizontal diagonal short connection and TSV vertical cross-layer interconnection on the basis of a 3D Mesh structure and matching an adaptive router and static routing algorithm; the SA-GA hybrid optimization algorithm module is used for completing position planning of the data acquisition nodes and the storage nodes through cooperation of SA and GA and finally realizing resource allocation optimization; and the layered heat dissipation layout module is used for deploying the storage nodes in a heat dissipation dominant area based on a heat distribution model, and solving the problem of heat accumulation of 3D NoC stacking. The method is suitable for scenes with high requirements on data transmission rate, delay and heat dissipation performance, such as a multi-core processor and a large-scale system-on-chip.

Method for transporting packets in a multi-cluster Network on Chip (NoC) interconnect with a transport protocol significantly enhance packet management in complex NoC chip architectures. This approach involves processing a packet within clusters to determine a destination cluster and a destination node, and executing a node lookup for the packet intended for different clusters. This lookup identifies an optimal path for transporting the packet out of the cluster. The multi-cluster NoC interconnect efficiently outlines cluster-to-cluster connections and manages global traffic, incorporating deadlock prevention techniques. Global bridges and boundary bridges facilitate effective traffic management between clusters. Each node includes a programmable path table that dynamically assigns efficient routes. This method significantly improves packet management across multi-cluster NoCs, offering a scalable, efficient, and reliable solution for complex computing environments.

Aspects of the present disclosure are directed to a method and a system for mapping flows of a Network-on-Chip (NoC). The method includes identifying hierarchically distinct flows across a plurality of instances of a sub-NoC, determining a unified route and Virtual Channel (VC) for each of the hierarchically distinct flows, and projecting the unified route and VC back to flow instances in each of the plurality of instances of the sub-NoC. By determining the unified route and VC for hierarchically distinct flows corresponding to flow instances of different instances of a sub-NoC, the method minimizes redundancy of mapping determination, and of resources during elaboration of NoC components.

The embodiment of the invention discloses a data transmission method and device of a network-on-chip, a routing node and a storage medium, and the method comprises the steps: confirming a target output direction of a data message under the condition that the data message sent by an upstream routing node is received; writing the data message into a target output register or a target backup register in the target output direction based on an arbitration result of the target arbiter in the target output direction for the data message, or sending a retransmission signal for the data message to an upstream routing node; sending a data message to a downstream routing node in the target output direction through the target output register or the target backup register, and temporarily storing the data message in the target backup register or the target output register before confirming that the downstream routing node receives the data message; and sending the data message to the downstream routing node from the target backup register or the target output register under the condition that a retransmission signal sent by the downstream routing node to the data message is received.

The invention discloses an NoC congestion control method based on redundant data merging, and relates to the technical field of general parallel computing and network-on-chip. Aiming at NoC congestion caused by redundant data transmission in a general parallel computing architecture and a bottleneck problem of a memory controller caused by the NoC congestion, an adopted scheme comprises the following steps of: marking cache requests from different SMs and aiming at the same cache block by integrating a grouping and merging unit in the memory controller; and after the memory controller accesses and obtains the cache blocks, injecting the cache blocks into the NoC according to the request marks, combining the cache blocks shared by the plurality of SM into a single data packet by utilizing the NoC characteristics, and sending the single data packet to each SM initiating the request through multicast routing. The method is applied to a general parallel computing architecture, and transmission of redundant data in the NoC can be avoided.

The invention discloses a data transmission device, which comprises an on-chip network interface module used for receiving messages sent by a first core grain in real time by taking data sub-packets as units and classifying each data sub-packet into a virtual channel matched with the on-chip network interface module according to the message type in each period, the on-chip network interface module internally comprises a plurality of parallel virtual channels; the interconnection control main body module is used for arbitrating and obtaining a target virtual channel in a plurality of virtual channels of the on-chip network interface module in each period, obtaining a data sub-packet from the target virtual channel, packaging a message frame, and sending the packaged message frame to the physical transmission layer module; and the physical transmission layer module is used for sending a message frame received in real time to the second core grain, and the device reduces the transmission delay of a complete message as much as possible on the premise of ensuring the correctness of data transmission between the core grains, and meanwhile, ensures the transmission efficiency and improves the transmission bandwidth.

A sliced router decomposes a router into a plurality of slices. Each slice has a subset of the input and output ports of the router. One or more of the slices may communicate with a network access point. Adjacent slices communicate with each other. In some example embodiments, there are dedicated physical channels between each slice and each adjacent slice for traffic coming in on or going out on ports of other slices. Within a slice, traffic may be arbitrated onto upstream or downstream channels going to the same output port. Each slice contains one or more crossbars, allowing data received on any input port to be routed to any output port of the slice. The crossbar of each slice is substantially smaller than the crossbar that would be used by a unified router.

The invention relates to a silicon substrate network physical topological structure and a silicon substrate chip architecture, the silicon substrate network physical topological structure comprises a central switch and a plurality of calculation core particle groups, each calculation core particle group is connected with the central switch, the central switch is arranged at the center of a wafer, and each calculation core particle group is arranged in a preset area around the central switch on the wafer; the central switch is used as a data routing node and provides a signal path for any two computing core particle groups; the calculation core particle group comprises a plurality of calculation core particles, all the calculation core particles are arranged in a two-dimensional grid form, all the calculation core particles are mutually connected through an on-chip network, and the calculation core particles are used for calculating data. By adopting the silicon substrate network physical topological structure, the balance between communication resources and computing resources can be ensured.

The invention provides a network-on-chip virtual channel management method, system and device and a storage medium, the network-on-chip virtual channel management method comprises the following steps: after an input port receives a to-be-processed flit, determining the flit type of the to-be-processed flit, and determining a buffer processing strategy according to the flit type; based on the buffer processing strategy, writing the to-be-processed microchip into a target slot located in a unified buffer structure; and determining a target virtual channel of the to-be-processed microchip, reading the to-be-processed microchip from the target slot position, and outputting the to-be-processed microchip based on the target virtual channel. The unified buffer structure is arranged, the to-be-processed microchips are cached in the unified buffer structure, and the problems that a traditional static buffer structure is low in utilization rate and poor in adaptability are solved.

Apparatus and methods for constructing Network on Chips (NoCs) by algorithmically elaborating one or more of Network on Chips (NoCs) through a hierarchical topology composed of instantiations of sub-NoCs and leaf components, and one or more connectivity definitions. Designing NoCs using one or more instantiations of sub-NoCs reduces overheads during chip backend processes, such as for timing closure.

System and methods for automatically generating control / status registers (CSR) based on configurations of components in a Network on Chip (NoC) include generating at least one repeatable field group from a plurality of defined fields, each of the plurality of defined fields defining portions of a register and NoC connectivity, generating at least one repeatable multi-register from the at least one repeatable field group, and generating at least one CSR group from the at least one repeatable multi-register, the at least one CSR group generated to be incorporated into a CSR bank. Such systems and methods of generating CSRs provides flexibility for designers / users to optimize the NoC for area consumption, reducing cost and complexity, parameterize configurations of the CSRs, and the like.