652 results about "Networks on chip" patented technology

The invention discloses a large model calculation acceleration chip architecture, and relates to the field of large models. Comprising a normalized network-on-chip, an interconnection transmission system, a storage control system and a calculation acceleration core, the storage control system is connected with the Memory video memory group and the external SSD memory based on different built-in storage controllers; the normalized network-on-chip reads on-chip model parameters of a target position based on the storage control system, sends the on-chip model parameters to the calculation acceleration core for calculation, restores on-chip model data, carries out off-chip interaction with an external management server based on the interconnection transmission system, receives an instruction task, reads and restores external model parameters, and sends the external model parameters to the calculation acceleration core for calculation. And performing inter-chip interaction with other computing acceleration chips based on an interconnection transmission system, and reading and restoring inter-chip model parameters. According to the scheme, the hybrid video memory computing chip architecture supports multi-parallel SSD direct connection access, the capacity is expanded at low cost under the condition of keeping the bandwidth, and high cost performance is kept for both large-scale parallel tasks and small-sized low-cost all-in-one machines.

The invention discloses an ANN accelerator system based on multi-core storage and calculation integration and a control method, and the system comprises an on-chip network module which serves as an interconnection channel between storage and calculation integration cores and is used for combining calculation results of the multiple storage and calculation integration cores; the synchronous main controller is used for sending an instruction to the decoder according to the process that the network-on-chip module combines the calculation results of the plurality of storage and calculation integrated cores; the decoder is used for receiving an instruction of the synchronous main controller and converting the instruction into a configuration parameter; the configuration register is used for storing configuration parameters and transmitting the configuration parameters to the asynchronous control module, the on-chip routing module and the storage and calculation integrated core; and the asynchronous control module is used for receiving the configuration parameters transmitted by the configuration register and performing time sequence control on the process of merging the calculation results by the network-on-chip module according to the configuration parameters. According to the method, storage and calculation integrated data flow control with reconfigurable parallelism is optimized, and the efficiency of neural network reasoning is greatly improved.

The embodiment of the invention provides a network-on-chip routing method and device, a storage medium and electronic equipment, and relates to the technical field of computers, and the method comprises the steps: determining a neighbor node of a first node according to a relation between the first node and a destination node; the first node is a sender of a data packet, and the destination node is a receiver of the data packet; and acquiring congestion information of the neighbor node, and selecting a transmission path of a data packet according to the congestion information. Therefore, the related neighbor nodes are selected according to the relationship between the first node and the target node, and the transmission path of the data packet is selected based on the congestion condition of the neighbor nodes, so that the network congestion problem is relieved through dynamic sensing and path selection, the path diversity is improved, the congestion is reduced, and the network congestion rate is improved. Therefore, the communication efficiency and the working performance of the network-on-chip are improved.

The embodiment of the invention provides a path sharing method, a network-on-chip and electronic equipment, the path sharing method is applied to the network-on-chip, the network-on-chip comprises a plurality of routing nodes, and each routing node is connected with at least one routing node. The two connected routing nodes are connected based on a data transmission path in a single transmission direction; the path sharing method comprises the following steps: in response to transmission data received by a current routing node, determining a next routing node of the current routing node in a plurality of routing nodes; wherein the current routing node is any routing node, which receives the transmission data, in the plurality of routing nodes, and the transmission data is entity data used for information transmission or configuration data used for parameter configuration; and transmitting the transmission data to the next routing node through the data transmission path based on a data transmission channel between the current routing node and the next routing node.

The embodiment of the invention provides a data transmission method and device based on a network-on-chip, electronic equipment and a readable storage medium. The method comprises the steps that a data packet is received, and a target routing node corresponding to the data packet is determined; determining a next-hop routing node corresponding to the routing node from the tree topology structure according to the receiving direction of the data packet and the position of the routing node in the tree topology structure; the tree topology structure is a structure for connecting configuration channels of the routing nodes; and sending the data packet to the next-hop routing node, so that the next-hop routing node determines the corresponding next-hop routing node until the next-hop routing node is the target routing node, sending the data packet to the target routing node, so that the target routing node performs configuration according to the data packet, and sending the configured data packet to the next-hop routing node, so that the next-hop routing node determines the corresponding next-hop routing node until the next-hop routing node is the target routing node. The bandwidth utilization rate during data transmission is improved, and the real-time performance of data transmission is improved.

The invention discloses a self-adaptive dynamic routing method and system for an NoC (Network on Chip), and relates to the technical field of routing management. Comprising the steps that the local congestion degree of each routing node is collected through a communication link, the global congestion degree is generated through a weighted average mechanism, each routing node integrates delay counters in the east direction, the west direction, the south direction and the north direction according to a local router, the delay counters are used for monitoring the time interval when adjacent data packets leave a buffer area in real time, and the global congestion degree is generated; taking a time interval of leaving a buffer area of adjacent data packets as output delay, spreading the output delay to neighbor routing nodes, calculating local congestion degree and global congestion degree of the routing nodes, generating all possible shortest paths and a candidate direction set corresponding to output directions according to addresses of a source routing node and a destination routing node, and sending the candidate direction set to the destination routing node; screening an optimal path through the local congestion degree and the global congestion degree in sequence; and when a plurality of equivalent paths exist, the routing direction is randomly selected to balance the network load.

The invention discloses a network architecture based on multi-core transmission, and relates to the field of integrated circuits. The network-on-chip module comprises at least one node ring consisting of M pipeline cascade routing nodes; adjacent routing nodes in adjacent node rings are cascaded according to a longitudinal depth pipeline to form a node matrix; n sending buffers and N receiving buffers are respectively arranged on the node ring on the outermost layer of the node matrix, and each sending buffer and each receiving buffer are respectively connected with the corresponding IP core through directly connected routing nodes; a routing algorithm based on a node matrix is built in the network configuration unit, a target IP core is determined according to data sent into the sending buffer by source IP core data, a node matrix is controlled to plan and generate a data transmission path, and data transmission is executed. The data buffer is added in the network-on-chip architecture, so that the data transmission path is shortened, the feedback is more timely, and the network bandwidth is larger; a routing node adds a data replication realization function to realize multicast and broadcast modes; and the interface complexity of the whole node matrix is reduced.

A self-optimizing and self-programming computing system (SOSPCS) design framework that achieves both programmability and flexibility and exploits computing heterogeneity [e.g., CPUs, GPUs, and hardware accelerators (HWAs)] is provided. First, at compile time, a task pool consisting of hybrid tasks with different processing element (PE) affinities according to target applications is formed. Tasks preferred to be executed on GPUs or accelerators are detected from target applications by neural networks. Tasks suitable to run on CPUs are formed by community detection to minimize data movement overhead. Next, a distributed reinforcement learning-based approach is used at runtime to allow agents to map the tasks onto the network-on-chip-based heterogeneous PEs by learning an optimal policy based on Q values in the environment.

The invention discloses a network-on-chip routing method and device, routing nodes, equipment, a medium and a product, and relates to the technical field of network-on-chip, and the method comprises the steps: firstly, screening the routing nodes through employing the input direction of a message, and limiting the selection range of the next-hop routing node; the relative position of the target routing node relative to the current routing node is determined, the routing nodes are further screened according to the relative position, and candidate routing nodes are determined; and determining a next-hop routing node according to the cache capacity and the input direction of the candidate routing node, and transmitting the message to be transmitted to the next-hop routing node to complete routing. The problem that the routing of the network-on-chip is easy to cause network message blockage or link failure of the network-on-chip can be solved. According to the method, an input direction is adopted to limit a selection range of a next-hop routing node, a relative position is adopted to determine candidate routing nodes, the next-hop routing node is determined in the candidate routing nodes based on cache capacity, and self-adaptive deadlock-free routing is realized.

The invention belongs to the technical field of routers, and particularly relates to an efficient SRAM (Static Random Access Memory) cache allocation and management system of an on-chip network router, which comprises an input decoding module, a buffer module, a data writing module, an SRAM module and a data reading module, the data writing module is used for writing the data packet into the SRAM module according to a chain table number distribution and recovery strategy; the SRAM module is used for storing the data packet in a specified memory block according to a memory allocation and recovery strategy; the data reading module is used for reading a corresponding data packet from the SRAM module according to a priority queue arbitration strategy; and the signal is transmitted to the output port. The priority queue arbitration strategy is adopted to ensure the priority output of high-priority data packets, the throughput and response time of the system are improved, and the method is particularly suitable for a high-load, multi-port and high-concurrency network environment.

The invention discloses a pulse neural network hardware accelerator and a data processing method, and the accelerator is characterized in that a low-power-consumption three-stage pipeline CPU module is used for receiving input data, scheduling an SNN network acceleration instruction, and sending the input data to an asynchronous edge SNN hardware accelerator module through a coprocessor interface; the asynchronous edge SNN hardware accelerator module comprises a pulse data encoding and decoding module, L neuromorphic kernels and an on-chip network, the pulse data encoding and decoding module encodes input data into a pulse form and sends the pulse form into the neuromorphic kernels, and the neuromorphic kernels are used for performing calculation based on the data in the pulse form; the network-on-chip is used for communication between the neuromorphic kernels, and the connection between neurons before and after synapses in the neuromorphic kernels is realized by adopting a synaptic cross array. According to the invention, the data processing acceleration performance can be greatly improved.

The invention provides a network-on-chip transmission information arbitration method and related equipment, and belongs to the technical field of computers, and the method comprises the following steps: determining a request to be sent by a target node in each input direction in a current round of arbitration period, and obtaining a target set; determining a weight value corresponding to each to-be-sent request in a target set according to a fault state of a node closest to a target node in a message transmission path of the target request, a space idle number of a flit size, a historical request number in the same transmission direction and a historical weight value; the historical weight value is a corresponding weight value when the target node sends each to-be-sent request in the last round of arbitration period; and sorting the to-be-sent requests in the target set according to a sequence of the weight values from high to low so as to respond to the sorted to-be-sent requests by using a crossbar switch on the target node. According to the method, the technical problem that the flow load of the network-on-chip is unbalanced in the related technology can be solved.

The embodiment of the invention provides a congestion control method and device, electronic equipment and a storage medium, and relates to the technical field of congestion control. The method is applied to a network-on-chip, and the network-on-chip comprises a back pressure signal generator and a plurality of routing nodes. The routing node comprises a plurality of output ports and a plurality of input ports, and the method comprises the following steps: under the condition that a first output port of a first routing node is congested, a back pressure signal generator obtains a data main input port corresponding to the first output port from a link flow table of the first routing node; transmitting the back pressure signal from the main input port to a second routing node adjacent to the first routing node; based on the link flow tables of the second routing node and the other routing nodes, the back pressure signals are sent to the corresponding source routing nodes in sequence; and on the basis of the back pressure signal, the packet sending behavior of the equipment corresponding to the output port, receiving the back pressure signal, of the source routing node is subjected to flow limiting, and the congestion control speed is higher and more accurate.

The invention relates to the technical field of integrated circuit system-on-chip communication, and relates to a network-on-chip transmission method and device based on a dynamic parallel mechanism, and a medium. The method comprises the following steps: carrying out parallel transmission by adopting a control link and a data link which are separated; the control link and the data link are respectively provided with an independent packing module and an independent unpacking module; different transaction types are adapted through a dynamic message structure; dynamic subpackaging is carried out according to the data size during data link packaging; when the control link is unpacked, parameters are split through the Controldec module and are sent to the parameter receiving module; and when the data link is unpacked, the data link is controlled by a state machine, and the split data is transmitted into a data storage module. The invention aims to effectively reduce congestion, reduce power consumption and improve the transmission efficiency and the overall performance of the network on chip through parallel transmission architecture design, double-link parallel packet processing logic design and a composition structure of a dynamic message.

Techniques for interfacing electronics are disclosed. A system-on-chip is accessed. The system-on-chip includes a network-on-chip (NoC) topology. The NoC sub-topologies are based on a physical location of the plurality of logic blocks. A first sub-topology is coupled to a receiving block, wherein the coupling includes inserting an interfacing block. The interfacing block includes a digital PLL (DPLL). The first sub-topology sends to the interfacing block data and a first clock. The first clock is input to the DPLL and used as a reference clock. The DPLL generates a second clock that is used to save the data that was sent. The interfacing block forwards to the receiving block the second clock and the data that was saved. The second clock is used as the internal clock in the receiving sub-topology. The NoC communications includes packets. Additional interfacing blocks are instantiated as necessary.

The invention discloses a cross-chip communication method, a direct connection module and a system, which consumes virtual channel credit during arbitration and packet reorganization, supplements the virtual channel credit when unpacked and uploaded to a network-on-chip, ensures that packets are correctly interacted in cross-chip communication through the channel credit, and reorganizes the packets according to a CXS protocol in an arbitration mode. According to the invention, ordered transmission of a plurality of packets in one physical channel is realized, 'starvation 'can be effectively prevented, the packet of a certain virtual channel is effectively prevented from being indefinitely delayed, the bandwidth utilization rate is improved, and the delay and congestion risks of cross-core-particle communication can be reduced.

The invention provides a processor chip with adjustable power consumption, which is integrated with a plurality of functional cores and a plurality of routers, all the routers are mutually connected to form an on-chip network, all the functional cores are mounted on the on-chip network to realize mutual communication, and the chip further comprises a power consumption management module, all the functional cores and all the routers are configured to be subjected to clock frequency adjustment by a power consumption management module, and the power consumption management module is used for adjusting the clock frequency of the processor chip based on a received frequency raising request from the functional cores and / or the routers; the clock frequency of the processor chip is adjusted based on a self-configured adjusting mechanism; wherein the power consumption management module is configured to support unified adjustment of clock frequencies of all the functional cores and / or all the routers, and independently adjust the clock frequencies of each functional core and each router; and the power consumption management module is mounted on the network-on-chip to realize communication with each router and each functional core.

A collaborative Network-on-Chip (NoC) development environment (CNDE) is accessed. The CNDE is based on cloud-native software. The CNDE enables graphical design of a NoC topology within a database. A first NoC sub-topology within the NoC topology is created within the CNDE. The creating includes coupling a first network initiator, a first router, and a first network target. A second NoC sub-topology within the NoC topology is generated within the CNDE. The generating includes coupling a second network initiator, a second router, and a second network target. An interfacing block is inserted within the CNDE, enabling two-way communication between the first NoC sub-topology and the second NoC sub-topology. The NoC topology is validated. The validating ensures that the first network initiator is coupled to the first and second network targets, and that the second network initiator is coupled to the first and second network targets.

The embodiment of the invention provides a memory access method and related equipment, and the method comprises the steps: obtaining a prefetch request which is a prediction request generated by a processor and an extraction request obtained by extracting a request sent to a network-on-chip by the processor; wherein the prefetching request at least comprises a memory address and control information; sending the prefetching request to a prefetching network; based on the prefetching request, reading prefetching data corresponding to the prefetching request from the memory; judging whether the memory address of the access request sent to the memory by the processor is matched with the memory address of the prefetching request or not; and if the memory address of the access request sent to the memory by the processor is matched with the memory address of the prefetching request, returning the prefetching data to the access request. The embodiment of the invention can improve the data transmission efficiency.

An integrated circuit includes logic circuits and a network-on-chip in a region of the integrated circuit. The network-on-chip is configurable to transmit at least two of user data, configuration data, and emulation data to the logic circuits. The network-on-chip is configurable to transmit the user data to and from the logic circuits during a user mode of the integrated circuit. The network-on-chip is configurable to transmit the configuration data to the logic circuits for configuring the logic circuits during a configuration mode of the integrated circuit. The network-on-chip is configurable to transmit the emulation data to and from the logic circuits during an emulation mode of the integrated circuit.

This disclosure provides systems, methods, and devices for enhancing data communication and computation efficiency in Systems on a Chip (SoC). In one aspect, a system is provided that uses a network on a chip (NOC) to route communications between chip components using a plurality of network interfaces linked by shared data connections. The system may be configured to route communications via multiple virtual channels along the shared connections, with credit restrictions for the channels. Additionally, the system may support mechanisms for maintaining both private and shared credit balances for these virtual channels. Additional aspects are also discussed.

The invention discloses a debugging method and device for a network-on-chip, electronic equipment and a readable storage medium, and relates to the technical field of the network-on-chip, and the method comprises the steps: automatically carrying out the function verification and performance debugging of the network-on-chip through a log file and a signal waveform file, finding out the reasons of function errors and performance substandard, and carrying out the debugging of the performance of the network-on-chip. Therefore, a user can be helped to quickly and efficiently complete the function debugging and performance analysis of the network-on-chip, so that the verification efficiency of verifying the network-on-chip can be improved, and the verification period can be shortened; therefore, the problem of low efficiency of function debugging and performance analysis of the network-on-chip in the prior art is solved.

The invention discloses a large model system based on a calculation acceleration chip, and relates to the field of large models. Comprising a plurality of calculation acceleration units and a management server, and an inter-chip and off-chip data interaction network is formed and realized; a mixed video memory of the calculation acceleration unit is matched with an SSD to form a multi-source storage mode; a normalized network-on-chip, an interconnection transmission system, a storage control system and a plurality of calculation acceleration cores are arranged in the calculation chip; the normalized network-on-chip can read model parameters of a target position based on the storage control system and send the model parameters to the calculation acceleration core for calculation and recovery; and interacting with the management server and other computing acceleration units based on the interconnection transmission system, and reading and storing external model parameters and inter-chip model parameters. The technical problems of insufficient video memory capacity, too high hardware cost and limited transmission bandwidth in a traditional scheme are effectively solved through collaborative design of a mixed video memory architecture and a normalized network-on-chip in combination with a multi-stage routing control and dynamic configuration mechanism.

The invention relates to a network-on-chip virtual channel routing system, a data forwarding method and related equipment, and the system comprises a routing outlet calculation module which is used for receiving a data packet transmitted by a network sender through a routing inlet and determining a routing outlet buffer area to which the data packet needs to be forwarded; the virtual channel buffer area distribution module is used for distributing a serial number of an idle virtual channel buffer area for the data packet; the virtual channel buffer area module comprises a plurality of virtual channel buffer areas corresponding to different route outlet buffer areas, and is used for caching the data packets by utilizing the corresponding virtual channel buffer areas according to the distributed serial numbers and recording pointer information of the data packets through a linked list; sending the data packet to the route exit buffer area when the route exit buffer area prepares data forwarding; and the credit release module is used for releasing the credit information to the network sender to control the maximum number of the data packets sent by the network sender. The utilization rate and throughput of the virtual channel are improved.

Conflict-free, stall-free, broadcast networks on neural inference chips are provided. In various embodiments, a neural inference chip comprises a plurality of network nodes and a network on chip interconnecting the plurality of network nodes. The network comprises at least one pair of directional paths. The paths of each pair have opposite directions and a common end. The network is configured to accept data at any of the plurality of nodes. The network is configured to propagate data along a first of the pair of directional paths from a source node to the common end of the pair of directional paths and along a second of the pair of directional paths from the common end of the pair of directional paths to one or more destination node.

The invention provides an on-chip network router, and a transmission method and device for routing data in an on-chip network, and the router comprises a row module and a column module which are mutually independent physically, so as to achieve the dimension decoupling of a data flow; wherein each of the row module and the column module comprises a crossbar switch and an arbitration unit coupled with the crossbar switch; the arbitration unit is configured to execute an arbitration decision on only one request in a conflict-free request pair when the two input ports of the crossbar switch request to be connected to the two different output ports respectively to form the conflict-free request pair, and to execute an arbitration decision on the conflict-free request pair based on the result of the arbitration decision. A data path is automatically established for another request in the conflict-free request pair to achieve mirroring effect arbitration. The router adopts the row and column decoupling type architecture and is matched with a mirror effect arbitration mechanism, so that resource competition is effectively reduced, arbitration logic is simplified, and the throughput and efficiency of the network-on-chip router are improved.

A computer-implemented method includes loading a simplistic network-on-chip (NoC) topology that is fully routed, and performing reinforcement learning on the NoC topology to identify a sequence of topology transformations that will produce a more optimal NoC topology. Performing the reinforcement learning includes running a plurality of training sessions. Running each training session includes using a machine learning model to apply a set of transformations to the NoC topology according to a policy, computing a cost of the NoC topology after the set of transformations has been applied, and updating the policy in response to the cost.

The invention provides a network-on-chip data transmission method, device and equipment and a storage medium, and relates to the technical field of computers, the method is applied to a transmission control node, and the transmission control node is arranged on a transmission channel between a network interface of a first node and a second node. A first node sends a message to a second node through a plurality of transmission channels. The method comprises the following steps: acquiring a credit value of each transmission channel; the credit value reflects the vacancy number of the cache region of the transmission channel, and the credit value is in positive correlation with the vacancy number; selecting a target transmission channel from the plurality of transmission channels according to the credit value; receiving a message transmission request sent by the first node, and forwarding the message transmission request to the second node through the target transmission channel; and when a response message returned by the second node is received, returning the identifier of the target transmission channel to the first node through the network interface, so that the first node sends a message to the second node through the target transmission channel.

The invention discloses a network-on-chip fault-tolerant system based on a fault processing router and a dual fault-tolerant distributed route, and relates to the technical field of network-on-chip. The system comprises a fault processing router and a dual fault-tolerant distributed routing mechanism. The fault processing router comprises a port distribution module, a redirection FIFO module, an error correction module, a crossbar switch module, a crossbar switch bypass module and a detection master control module. The modules cooperate to realize fault isolation and path reconstruction. According to the dual fault-tolerant distributed routing mechanism, fault tolerance is realized through single fault isolation, composite fault collaboration and dynamic routing adjustment, and deadlock is avoided and network connectivity under fault topology is maximized by dynamically relaxing and forbidding a steering rule. The problems of single-point failure and composite fault accumulation caused by permanent faults of transistors of the network-on-chip are solved.

The PIO communication device comprises a protocol conversion module and a PIO transaction processing module, the protocol conversion module and the PIO transaction processing module are connected with each other, the protocol conversion module is connected with a computing component connected to a network-on-chip NoC through an AXI interface, and when the computing component initiates a PIO read-write request, the PIO transaction processing module sends the PIO read-write request to the computing component; the protocol conversion module performs conversion of read-write requests between an AXI protocol and a PIO protocol and mapping of response states, and the PIO transaction processing module initiates register access and descriptor writing operation to the network protocol processing component by analyzing the converted PIO read-write requests and receives register read response data returned by the network protocol processing component. According to the invention, a decoupling design of an address channel, a data channel and a response channel is adopted, conversion of a PIO read-write transaction between an AXI interface and a network protocol interface is completed, and high-bandwidth and low-delay non-blocking PIO data transmission and processing are realized.