561 results about "Networks on chip" patented technology

The invention discloses a large model calculation acceleration chip architecture, and relates to the field of large models. Comprising a normalized network-on-chip, an interconnection transmission system, a storage control system and a calculation acceleration core, the storage control system is connected with the Memory video memory group and the external SSD memory based on different built-in storage controllers; the normalized network-on-chip reads on-chip model parameters of a target position based on the storage control system, sends the on-chip model parameters to the calculation acceleration core for calculation, restores on-chip model data, carries out off-chip interaction with an external management server based on the interconnection transmission system, receives an instruction task, reads and restores external model parameters, and sends the external model parameters to the calculation acceleration core for calculation. And performing inter-chip interaction with other computing acceleration chips based on an interconnection transmission system, and reading and restoring inter-chip model parameters. According to the scheme, the hybrid video memory computing chip architecture supports multi-parallel SSD direct connection access, the capacity is expanded at low cost under the condition of keeping the bandwidth, and high cost performance is kept for both large-scale parallel tasks and small-sized low-cost all-in-one machines.

The embodiment of the invention provides a data transmission method and device based on a network-on-chip, electronic equipment and a readable storage medium. The method comprises the steps that a data packet is received, and a target routing node corresponding to the data packet is determined; determining a next-hop routing node corresponding to the routing node from the tree topology structure according to the receiving direction of the data packet and the position of the routing node in the tree topology structure; the tree topology structure is a structure for connecting configuration channels of the routing nodes; and sending the data packet to the next-hop routing node, so that the next-hop routing node determines the corresponding next-hop routing node until the next-hop routing node is the target routing node, sending the data packet to the target routing node, so that the target routing node performs configuration according to the data packet, and sending the configured data packet to the next-hop routing node, so that the next-hop routing node determines the corresponding next-hop routing node until the next-hop routing node is the target routing node. The bandwidth utilization rate during data transmission is improved, and the real-time performance of data transmission is improved.

The invention discloses a self-adaptive dynamic routing method and system for an NoC (Network on Chip), and relates to the technical field of routing management. Comprising the steps that the local congestion degree of each routing node is collected through a communication link, the global congestion degree is generated through a weighted average mechanism, each routing node integrates delay counters in the east direction, the west direction, the south direction and the north direction according to a local router, the delay counters are used for monitoring the time interval when adjacent data packets leave a buffer area in real time, and the global congestion degree is generated; taking a time interval of leaving a buffer area of adjacent data packets as output delay, spreading the output delay to neighbor routing nodes, calculating local congestion degree and global congestion degree of the routing nodes, generating all possible shortest paths and a candidate direction set corresponding to output directions according to addresses of a source routing node and a destination routing node, and sending the candidate direction set to the destination routing node; screening an optimal path through the local congestion degree and the global congestion degree in sequence; and when a plurality of equivalent paths exist, the routing direction is randomly selected to balance the network load.

The invention discloses a network architecture based on multi-core transmission, and relates to the field of integrated circuits. The network-on-chip module comprises at least one node ring consisting of M pipeline cascade routing nodes; adjacent routing nodes in adjacent node rings are cascaded according to a longitudinal depth pipeline to form a node matrix; n sending buffers and N receiving buffers are respectively arranged on the node ring on the outermost layer of the node matrix, and each sending buffer and each receiving buffer are respectively connected with the corresponding IP core through directly connected routing nodes; a routing algorithm based on a node matrix is built in the network configuration unit, a target IP core is determined according to data sent into the sending buffer by source IP core data, a node matrix is controlled to plan and generate a data transmission path, and data transmission is executed. The data buffer is added in the network-on-chip architecture, so that the data transmission path is shortened, the feedback is more timely, and the network bandwidth is larger; a routing node adds a data replication realization function to realize multicast and broadcast modes; and the interface complexity of the whole node matrix is reduced.

A self-optimizing and self-programming computing system (SOSPCS) design framework that achieves both programmability and flexibility and exploits computing heterogeneity [e.g., CPUs, GPUs, and hardware accelerators (HWAs)] is provided. First, at compile time, a task pool consisting of hybrid tasks with different processing element (PE) affinities according to target applications is formed. Tasks preferred to be executed on GPUs or accelerators are detected from target applications by neural networks. Tasks suitable to run on CPUs are formed by community detection to minimize data movement overhead. Next, a distributed reinforcement learning-based approach is used at runtime to allow agents to map the tasks onto the network-on-chip-based heterogeneous PEs by learning an optimal policy based on Q values in the environment.

The invention discloses a network-on-chip routing method and device, routing nodes, equipment, a medium and a product, and relates to the technical field of network-on-chip, and the method comprises the steps: firstly, screening the routing nodes through employing the input direction of a message, and limiting the selection range of the next-hop routing node; the relative position of the target routing node relative to the current routing node is determined, the routing nodes are further screened according to the relative position, and candidate routing nodes are determined; and determining a next-hop routing node according to the cache capacity and the input direction of the candidate routing node, and transmitting the message to be transmitted to the next-hop routing node to complete routing. The problem that the routing of the network-on-chip is easy to cause network message blockage or link failure of the network-on-chip can be solved. According to the method, an input direction is adopted to limit a selection range of a next-hop routing node, a relative position is adopted to determine candidate routing nodes, the next-hop routing node is determined in the candidate routing nodes based on cache capacity, and self-adaptive deadlock-free routing is realized.

The invention discloses a pulse neural network hardware accelerator and a data processing method, and the accelerator is characterized in that a low-power-consumption three-stage pipeline CPU module is used for receiving input data, scheduling an SNN network acceleration instruction, and sending the input data to an asynchronous edge SNN hardware accelerator module through a coprocessor interface; the asynchronous edge SNN hardware accelerator module comprises a pulse data encoding and decoding module, L neuromorphic kernels and an on-chip network, the pulse data encoding and decoding module encodes input data into a pulse form and sends the pulse form into the neuromorphic kernels, and the neuromorphic kernels are used for performing calculation based on the data in the pulse form; the network-on-chip is used for communication between the neuromorphic kernels, and the connection between neurons before and after synapses in the neuromorphic kernels is realized by adopting a synaptic cross array. According to the invention, the data processing acceleration performance can be greatly improved.

The invention relates to the technical field of integrated circuit system-on-chip communication, and relates to a network-on-chip transmission method and device based on a dynamic parallel mechanism, and a medium. The method comprises the following steps: carrying out parallel transmission by adopting a control link and a data link which are separated; the control link and the data link are respectively provided with an independent packing module and an independent unpacking module; different transaction types are adapted through a dynamic message structure; dynamic subpackaging is carried out according to the data size during data link packaging; when the control link is unpacked, parameters are split through the Controldec module and are sent to the parameter receiving module; and when the data link is unpacked, the data link is controlled by a state machine, and the split data is transmitted into a data storage module. The invention aims to effectively reduce congestion, reduce power consumption and improve the transmission efficiency and the overall performance of the network on chip through parallel transmission architecture design, double-link parallel packet processing logic design and a composition structure of a dynamic message.

Techniques for interfacing electronics are disclosed. A system-on-chip is accessed. The system-on-chip includes a network-on-chip (NoC) topology. The NoC sub-topologies are based on a physical location of the plurality of logic blocks. A first sub-topology is coupled to a receiving block, wherein the coupling includes inserting an interfacing block. The interfacing block includes a digital PLL (DPLL). The first sub-topology sends to the interfacing block data and a first clock. The first clock is input to the DPLL and used as a reference clock. The DPLL generates a second clock that is used to save the data that was sent. The interfacing block forwards to the receiving block the second clock and the data that was saved. The second clock is used as the internal clock in the receiving sub-topology. The NoC communications includes packets. Additional interfacing blocks are instantiated as necessary.

The invention discloses a cross-chip communication method, a direct connection module and a system, which consumes virtual channel credit during arbitration and packet reorganization, supplements the virtual channel credit when unpacked and uploaded to a network-on-chip, ensures that packets are correctly interacted in cross-chip communication through the channel credit, and reorganizes the packets according to a CXS protocol in an arbitration mode. According to the invention, ordered transmission of a plurality of packets in one physical channel is realized, 'starvation 'can be effectively prevented, the packet of a certain virtual channel is effectively prevented from being indefinitely delayed, the bandwidth utilization rate is improved, and the delay and congestion risks of cross-core-particle communication can be reduced.

The invention provides a processor chip with adjustable power consumption, which is integrated with a plurality of functional cores and a plurality of routers, all the routers are mutually connected to form an on-chip network, all the functional cores are mounted on the on-chip network to realize mutual communication, and the chip further comprises a power consumption management module, all the functional cores and all the routers are configured to be subjected to clock frequency adjustment by a power consumption management module, and the power consumption management module is used for adjusting the clock frequency of the processor chip based on a received frequency raising request from the functional cores and / or the routers; the clock frequency of the processor chip is adjusted based on a self-configured adjusting mechanism; wherein the power consumption management module is configured to support unified adjustment of clock frequencies of all the functional cores and / or all the routers, and independently adjust the clock frequencies of each functional core and each router; and the power consumption management module is mounted on the network-on-chip to realize communication with each router and each functional core.

A collaborative Network-on-Chip (NoC) development environment (CNDE) is accessed. The CNDE is based on cloud-native software. The CNDE enables graphical design of a NoC topology within a database. A first NoC sub-topology within the NoC topology is created within the CNDE. The creating includes coupling a first network initiator, a first router, and a first network target. A second NoC sub-topology within the NoC topology is generated within the CNDE. The generating includes coupling a second network initiator, a second router, and a second network target. An interfacing block is inserted within the CNDE, enabling two-way communication between the first NoC sub-topology and the second NoC sub-topology. The NoC topology is validated. The validating ensures that the first network initiator is coupled to the first and second network targets, and that the second network initiator is coupled to the first and second network targets.

An integrated circuit includes logic circuits and a network-on-chip in a region of the integrated circuit. The network-on-chip is configurable to transmit at least two of user data, configuration data, and emulation data to the logic circuits. The network-on-chip is configurable to transmit the user data to and from the logic circuits during a user mode of the integrated circuit. The network-on-chip is configurable to transmit the configuration data to the logic circuits for configuring the logic circuits during a configuration mode of the integrated circuit. The network-on-chip is configurable to transmit the emulation data to and from the logic circuits during an emulation mode of the integrated circuit.

This disclosure provides systems, methods, and devices for enhancing data communication and computation efficiency in Systems on a Chip (SoC). In one aspect, a system is provided that uses a network on a chip (NOC) to route communications between chip components using a plurality of network interfaces linked by shared data connections. The system may be configured to route communications via multiple virtual channels along the shared connections, with credit restrictions for the channels. Additionally, the system may support mechanisms for maintaining both private and shared credit balances for these virtual channels. Additional aspects are also discussed.

The invention discloses a large model system based on a calculation acceleration chip, and relates to the field of large models. Comprising a plurality of calculation acceleration units and a management server, and an inter-chip and off-chip data interaction network is formed and realized; a mixed video memory of the calculation acceleration unit is matched with an SSD to form a multi-source storage mode; a normalized network-on-chip, an interconnection transmission system, a storage control system and a plurality of calculation acceleration cores are arranged in the calculation chip; the normalized network-on-chip can read model parameters of a target position based on the storage control system and send the model parameters to the calculation acceleration core for calculation and recovery; and interacting with the management server and other computing acceleration units based on the interconnection transmission system, and reading and storing external model parameters and inter-chip model parameters. The technical problems of insufficient video memory capacity, too high hardware cost and limited transmission bandwidth in a traditional scheme are effectively solved through collaborative design of a mixed video memory architecture and a normalized network-on-chip in combination with a multi-stage routing control and dynamic configuration mechanism.

The invention relates to a network-on-chip virtual channel routing system, a data forwarding method and related equipment, and the system comprises a routing outlet calculation module which is used for receiving a data packet transmitted by a network sender through a routing inlet and determining a routing outlet buffer area to which the data packet needs to be forwarded; the virtual channel buffer area distribution module is used for distributing a serial number of an idle virtual channel buffer area for the data packet; the virtual channel buffer area module comprises a plurality of virtual channel buffer areas corresponding to different route outlet buffer areas, and is used for caching the data packets by utilizing the corresponding virtual channel buffer areas according to the distributed serial numbers and recording pointer information of the data packets through a linked list; sending the data packet to the route exit buffer area when the route exit buffer area prepares data forwarding; and the credit release module is used for releasing the credit information to the network sender to control the maximum number of the data packets sent by the network sender. The utilization rate and throughput of the virtual channel are improved.

Conflict-free, stall-free, broadcast networks on neural inference chips are provided. In various embodiments, a neural inference chip comprises a plurality of network nodes and a network on chip interconnecting the plurality of network nodes. The network comprises at least one pair of directional paths. The paths of each pair have opposite directions and a common end. The network is configured to accept data at any of the plurality of nodes. The network is configured to propagate data along a first of the pair of directional paths from a source node to the common end of the pair of directional paths and along a second of the pair of directional paths from the common end of the pair of directional paths to one or more destination node.

The invention provides an on-chip network router, and a transmission method and device for routing data in an on-chip network, and the router comprises a row module and a column module which are mutually independent physically, so as to achieve the dimension decoupling of a data flow; wherein each of the row module and the column module comprises a crossbar switch and an arbitration unit coupled with the crossbar switch; the arbitration unit is configured to execute an arbitration decision on only one request in a conflict-free request pair when the two input ports of the crossbar switch request to be connected to the two different output ports respectively to form the conflict-free request pair, and to execute an arbitration decision on the conflict-free request pair based on the result of the arbitration decision. A data path is automatically established for another request in the conflict-free request pair to achieve mirroring effect arbitration. The router adopts the row and column decoupling type architecture and is matched with a mirror effect arbitration mechanism, so that resource competition is effectively reduced, arbitration logic is simplified, and the throughput and efficiency of the network-on-chip router are improved.

A computer-implemented method includes loading a simplistic network-on-chip (NoC) topology that is fully routed, and performing reinforcement learning on the NoC topology to identify a sequence of topology transformations that will produce a more optimal NoC topology. Performing the reinforcement learning includes running a plurality of training sessions. Running each training session includes using a machine learning model to apply a set of transformations to the NoC topology according to a policy, computing a cost of the NoC topology after the set of transformations has been applied, and updating the policy in response to the cost.

The invention provides a network-on-chip data transmission method, device and equipment and a storage medium, and relates to the technical field of computers, the method is applied to a transmission control node, and the transmission control node is arranged on a transmission channel between a network interface of a first node and a second node. A first node sends a message to a second node through a plurality of transmission channels. The method comprises the following steps: acquiring a credit value of each transmission channel; the credit value reflects the vacancy number of the cache region of the transmission channel, and the credit value is in positive correlation with the vacancy number; selecting a target transmission channel from the plurality of transmission channels according to the credit value; receiving a message transmission request sent by the first node, and forwarding the message transmission request to the second node through the target transmission channel; and when a response message returned by the second node is received, returning the identifier of the target transmission channel to the first node through the network interface, so that the first node sends a message to the second node through the target transmission channel.

The invention discloses a network-on-chip fault-tolerant system based on a fault processing router and a dual fault-tolerant distributed route, and relates to the technical field of network-on-chip. The system comprises a fault processing router and a dual fault-tolerant distributed routing mechanism. The fault processing router comprises a port distribution module, a redirection FIFO module, an error correction module, a crossbar switch module, a crossbar switch bypass module and a detection master control module. The modules cooperate to realize fault isolation and path reconstruction. According to the dual fault-tolerant distributed routing mechanism, fault tolerance is realized through single fault isolation, composite fault collaboration and dynamic routing adjustment, and deadlock is avoided and network connectivity under fault topology is maximized by dynamically relaxing and forbidding a steering rule. The problems of single-point failure and composite fault accumulation caused by permanent faults of transistors of the network-on-chip are solved.

The PIO communication device comprises a protocol conversion module and a PIO transaction processing module, the protocol conversion module and the PIO transaction processing module are connected with each other, the protocol conversion module is connected with a computing component connected to a network-on-chip NoC through an AXI interface, and when the computing component initiates a PIO read-write request, the PIO transaction processing module sends the PIO read-write request to the computing component; the protocol conversion module performs conversion of read-write requests between an AXI protocol and a PIO protocol and mapping of response states, and the PIO transaction processing module initiates register access and descriptor writing operation to the network protocol processing component by analyzing the converted PIO read-write requests and receives register read response data returned by the network protocol processing component. According to the invention, a decoupling design of an address channel, a data channel and a response channel is adopted, conversion of a PIO read-write transaction between an AXI interface and a network protocol interface is completed, and high-bandwidth and low-delay non-blocking PIO data transmission and processing are realized.

Receiving a compute express link (CXL) packet at a link controller of an input / output (I / O) chip, and responsively terminating the CXL packet to generate a load / store memory transaction having a plurality of parameters comprising a host physical address (HPA), and a logical device ID (LD_ID), translating, using a forwarding engine, the HPA into a device physical address (DPA) based on the LD_ID, and appending network-on-chip (NoC) routing information to the load / store memory transaction, outputting, the load / store memory transaction and the NoC routing information to a plurality of signal traces on a printed circuit board (PCB), receiving the load / store memory transaction and the NoC routing information, and routing, using a NoC, the load / store memory transaction based on the NoC routing information to a destination port on the NoC, the NoC comprising (i) memory controller ports, (ii) edge processing unit (EPU) ports, and (iii) die-to-die interface ports.

The invention discloses an object routing node, a routing method and a network-on-chip. The object routing node comprises a first register and a second register, and the first register is configured to respond to the condition that a first message of a first type and a second message of a second type are received at the same time, select to store the first message and send the second message to the object routing node under the condition that a next routing node of the object routing node meets a scheduling condition. Providing the first message for a next routing node; the second register is configured to acquire the second message in response to the fact that the second message is not received by the first register and the anti-starvation mechanism is triggered, and the anti-starvation mechanism is configured to indicate that after the first register is vacant, the first register does not receive the first type of message until the second message is scheduled to the next routing node through the first register. According to the object routing node, the arbitration logic is reduced, and the resource overhead caused by the arbitration logic is greatly reduced.

The embodiment of the invention provides a data method and device, electronic equipment and a storage medium. The data processing method comprises the following steps: in response to receiving a first request data packet, determining the number of available buffer units in a receiving request buffer area used for receiving the first request data packet in a receiving proxy node; in response to the fact that the number of the available buffer units is smaller than or equal to the first threshold value, at least one request data packet stored in the receiving request buffer area is discarded. According to the method, at least one request data packet in a buffer area for receiving a receiving or storing request of a receiving proxy node is discarded, and the discarded request data packet is sent to the receiving proxy node again, so that the quantity of at least one available buffer unit in the buffer area for receiving the receiving or storing request of the receiving proxy node can be ensured; therefore, the interconnection network-on-chip is prevented from being congested or locked, and the performance of the interconnection network-on-chip is improved.

The invention relates to the technical field of integrated circuit design, in particular to a reconfigurable network-on-chip of a data stream accelerator. The reconfigurable network-on-chip of the data stream accelerator adopts a dual-mode reconfigurable router architecture, each router is integrated with four HT switches, and the connection direction is controlled through a mode selection signal; meanwhile, a normal mode of standard Mesh connection and a high throughput HT mode of directional aggregation bandwidth are supported; in a high throughput HT mode, a north port IN, a south port IS, an east port IE and a west port IW are used for injecting data in parallel, in order to make full use of the bandwidth of each router, unused output ports are reconstructed to transmit data in the same direction, and a high-bandwidth link is formed; and the FC layer and the CONV layer are optimized. According to the reconfigurable network-on-chip of the data flow accelerator, unused ports, buffer areas and routing logic are redirected to the target direction by dynamically switching the router mode, and maximum utilization of bandwidth resources is achieved.

The invention discloses a congestion-aware network-on-chip fault-tolerant routing method and a congestion-aware network-on-chip fault-tolerant routing system, and relates to the technical field of computer network communication. Comprising the steps of 1, creating an on-chip network fault-tolerant routing system, 2, deploying a network monitoring module at each router node, and generating routing configuration based on real-time data, and 3, when a network is congested and / or failed, measuring the congestion degree through the network monitoring module according to the size of an idle cache at an input end, and determining the weight W of a path according to the congestion degree; step 4, collecting link and routing node fault information and an input cache state through the network monitoring module, reporting the information to an upper computer management module, updating global network state information by the upper computer management module according to received data collected by the network monitoring module, generating routing configuration in combination with a routing rule, and sending the routing configuration to the network monitoring module; and real-time routing configuration is issued to each routing node through the configuration module.

The invention relates to the technical field of congestion detection and solution of a high-performance network-on-chip, and relates to a congestion detection and self-adaptive control method and system of a 2D (two-dimensional) network-on-chip (NoC). The method comprises the following steps: based on a 2D mesh NoC topology, generating a data packet injection rate of each node by using a Poisson distribution flow model, and modeling and recording a buffer load value and an arbitration waiting request number through an NoC simulator; classifying nodes according to node centrality annular distribution characteristics, and initializing a threshold register value; when congestion control is input, an input blocking index is periodically calculated, and a threshold value register is dynamically adjusted according to a threshold value; a congestion control path is output, a data packet is redirected when an output busy signal is activated, and a new request is blocked if all output ports are busy; through off-line estimation optimization and on-line detection adjustment, NoC congestion is effectively solved, and system performance and reliability are improved.

The invention provides a double-end cooperative network-on-chip flow control method and device and electronic equipment, and the method comprises the steps: receiving first flow counting information synchronously transmitted by a destination end through a rapid signal, and determining second flow counting information of a source end, the source end and the destination end are respectively a starting node and an ending node of a complete link in the network-on-chip; estimating the link state of the network-on-chip according to the first flow counting information and the second flow counting information; and controlling the flow injection rate of the source end according to the link state. According to the method, counting information synchronization of a source end and a destination end is realized by utilizing the characteristics of low cost and high speed of a control signal in the network-on-chip, so that the link state of the network-on-chip is accurately estimated, the process ensures that no obvious flow accumulation exists on a path, bandwidth resource waste caused by excessive speed limitation is avoided, and the link state of the network-on-chip is accurately estimated. Quicker and more accurate flow management is supported; and more timely and accurate flow regulation is realized.

The invention discloses a wafer-level integrated system-oriented network-on-chip routing architecture and a working method thereof, the network-on-chip routing architecture forms a two-dimensional mesh topology structure by a plurality of router nodes, and routers are connected with one another through crisscrossed links in four directions; the basic unit of the network-on-chip field area routing architecture is a router; according to the system, flexible configuration of routing tables and functional modules of all routers is realized through a configuration packet in a specific format. The system adopts a detection method based on a heartbeat packet, a router actively sends a heartbeat request to a neighbor and waits for a response, and meanwhile, a layered health state monitoring mechanism is realized at an on-chip network field level. According to the mechanism, a local monitor is responsible for summarizing router and link states in a region, and a global monitor integrates information of each region to generate a field-level health report. The configuration and fault detection method provided by the invention has the advantages of flexibility, high efficiency, high expandability, high detection precision and the like, and is suitable for the network-on-chip in a large-scale wafer-level integrated system.