69 results about "Networks on chip" patented technology

This invention discloses a method for optimizing the topology of a 3D on-chip network (SoC) for high-speed data acquisition systems. Addressing the problem that general-purpose 3D SoC architectures are difficult to adapt to the communication characteristics of high-speed data acquisition systems, leading to high transmission latency and redundant link resources, this method models the network topology adjustment process as a Markov decision process and employs deep reinforcement learning to achieve adaptive optimization of the topology. The method uses a general-purpose 3D SoC as the initial architecture, constructing a state representation that includes node connection features, average network latency, longest path latency, and link area; defining a pruning and regrowth action space; designing a reward function that integrates changes in average latency, longest path latency, and link area; and using a deep Q-learning network with a multilayer perceptron structure for policy training. To improve learning efficiency, an action candidate set is constructed and combined with a two-layer greedy policy to achieve fast and effective search. Through iterative learning and topology updates, a 3D SoC topology that better suits the communication load of high-speed data acquisition systems can be obtained, reducing average transmission latency and link area overhead while ensuring connectivity.

The application relates to the chip technical field and discloses a partition unit, a partition, a chip, a network-on-chip implementation method and a medium. The partition unit comprises the following steps: obtaining an operation type and an access address corresponding to a memory access request through a secondary cache, and forwarding the memory access request to a control module of a directory corresponding to the access address when the operation type is a partial write operation; writing request data corresponding to the memory access request into a small-capacity cache through the control module, reading a target partition unit corresponding to the partition unit from a state recording module, generating a listening request according to the memory access request and sending the listening request to the target partition unit, receiving listening data fed back by the target partition unit, merging the listening data and the request data to generate complete data, and writing the complete data into a memory controller. Hardware support for cache consistency can be provided in an artificial intelligence chip with a multi-core architecture, and a network-on-chip implementation scheme supporting cache consistency is provided.

The application discloses a reconfigurable processor and an execution method fusing neuromorphic and general computing, and comprises a total control module and an on-chip network module, wherein the on-chip network module comprises a control module, a pulse storage module, a weight storage module, a pulse time module, a LIF neuron module and a classification comparison module. The execution method comprises the following steps: acquiring an input data set; selecting a working mode of the on-chip network module according to the input data set; and performing data recognition processing on the input data set according to the working mode, and outputting a data recognition output result. The application realizes the working of a central processing unit (CPU) and a spiking neural network (SNN) in a single core, thereby improving the utilization rate of a heterogeneous core and reducing the delay of core-to-accelerator communication. The application can be widely applied to the technical field of neural network accelerator as a reconfigurable processor and an execution method fusing neuromorphic and general computing.

This disclosure provides a method, apparatus, device, medium, and product for access verification in on-chip networks (NoCs), relating to integrated circuit design and verification and System-on-Chip (SoC) design technologies, particularly in the areas of NoC security verification, access control, and access control isolation verification. The specific implementation scheme is as follows: a routing access permission file is parsed to obtain access permission paths and self-test instances; the self-test instances are executed to obtain self-test results; the self-test results and the routing access permission file are compared and verified to obtain a verification result; if the verification result fails, the access permission paths in the routing access permission file are modified until the verification result passes; routing tests are performed in a UVM environment based on the modified access permission paths to obtain the access verification result. This technical solution can shorten the access verification cycle of on-chip networks.

This invention relates to an on-chip network quality of service (QoS) arbitration method, system, and storage medium. The on-chip QoS arbitration method determines port status hierarchically, prioritizes responding to sudden data forwarding requests, and uses an anti-starvation counter to monitor port scheduling. Ports that have not been granted forwarding privileges for a long time are given priority in being allocated forwarding rights. When there are no special port requirements, arbitration scheduling is carried out uniformly. Compared with existing technologies, this invention balances data transmission timeliness and port scheduling fairness, effectively avoiding port starvation and data congestion problems, and improving the stability of on-chip network forwarding.

A Network-On-Chip (NoC) -based accelerator is disclosed for performing in-network and in-memory sparse tensor computations between an activation tensor and a weight tensor. The accelerator comprises a plurality of NoC nodes organized in a first two-dimensional (2D) network. Each NoC node includes a plurality of kernels organized in a second 2D network, and each kernel contains a plurality of cores organized in a third 2D network. The weight tensor is evenly distributed among the NoC nodes in the first 2D network. Within each NoC node, the kernels are configured to perform output-channel gathering on the weight tensor, while the cores within each kernel perform input-channel gathering. These gathering processes generate a condensed weight tensor that is evenly distributed among the NoC nodes. The activation tensor is broadcasted to the NoC nodes, enabling parallel sparse tensor computation using the evenly distributed and condensed weight tensor.

This application discloses an on-chip network router device and communication system for hybrid topology, including a pop-out module, a buffer module group, a control module, a selection module group, an arbitration module, and a register module group. The pop-out module is used to output local address data from multi-source input data to the neuron end and transmit non-local address data to the buffer module group. The buffer module group is used to synchronously and temporarily store non-local address data. The control module is used to generate control signals for regulating read enable and gating actions based on the data storage status of the buffer module group. The selection module group is used to select one path from multiple valid data paths for transmission to the arbitration module based on the control signals. The arbitration module is used to perform address matching and transmission conflict arbitration on the selected multiple data paths and forward the valid data to the corresponding register module group. The register module group is used to update the hop count of the arbitrated data stream and then forward it to the ring topology on-chip network.

This application relates to the field of integrated circuit design technology and discloses an on-chip network deadlock prevention method and system based on path reservation and credit backhaul. The core of the method lies in proactively locking virtual channel resources along the entire path via an independent reservation request packet along an adaptive route before data packet transmission. Combined with a "credit backhaul confirmation" mechanism, data packets are only allowed to be injected into the network after the source node receives an confirmation packet, thus transforming resource dependencies into unidirectional credit flow control. Simultaneously, reservation resource management is achieved by setting a distributed reservation state table in each router, and soft reservation and multi-path exploration mechanisms are introduced to improve resource utilization efficiency and path selection flexibility. This scheme fundamentally breaks the conditions for circular waiting, completely avoids deadlock, and eliminates the performance bottleneck of traditional methods when virtual channel resources are limited, achieving high determinism in data transmission, low blocking risk, and high efficiency in resource utilization.

Provided in the embodiments of the present application are a memory access method and a related device. The method comprises: acquiring a prefetch request, which is a predicted request generated by a processor, or a fetch request, which is extracted from a request sent by the processor to a network-on-chip, wherein the prefetch request at least comprises a memory address and control information; sending the prefetch request to a prefetch network; on the basis of the prefetch request, reading, from a memory, prefetched data that corresponds to the prefetch request; determining whether the memory address in an access request sent by the processor to the memory matches the memory address in the prefetch request; and if the memory address in the access request sent by the processor to the memory matches the memory address in the prefetch request, using the prefetched data as feedback data for the access request, and returning the prefetched data to the processor. The embodiments of the present application can improve data transmission efficiency.

The present disclosure provides a method and device for transmitting a request in a system chip, and a system chip. The method comprises: obtaining a plurality of sending requests; the sending requests enter a normal channel cache after entering a network on chip; obtaining a request delay time of the sending requests; performing a time delay threshold determination on the request delay time to obtain sending requests exceeding the time delay threshold; obtaining a flow control packet of the sending requests exceeding the time delay threshold; the flow control packet is transmitted in a virtual channel in the network on chip, and is compared with the identity code of the cache sending requests located in the normal channel, when the comparison result is consistent, the emergency request packet is dispatched to the virtual channel through an escape channel in the network on chip, and is preferentially dispatched to a plurality of downstream nodes of the network on chip through the virtual channel, and is transmitted in the downstream nodes by using the virtual channel. The present disclosure can improve the real-time performance of the virtual channel escape.

A computer-implemented method of generating a network-on-chip (NoC) topology for an electronic system includes creating a logical description of a plurality of empty sub-networks that connect initiators to targets of an electronic system. The method further includes placing the sub-networks within free space of a floorplan of the electronic system in a desired topology shape; and performing automated topology synthesis to add switches to each of the sub-networks such that the initiators are connected to the targets in accordance with a communication policy.

The application provides a communication method and device of a system on chip and a storage medium. In the method, an abnormal code returned by a network on chip is acquired in the process that a communication subject communicates with a communication object through the network on chip, and the communication subject and the communication object are state detected according to the abnormal code. In the case that the state detection result is a software repairable abnormality, the communication object is state repaired, the communication subject is caused to enter a waiting time, and after the waiting time reaches a preset waiting time length, a communication channel of the communication subject and the communication object is re-established based on the network on chip. The abnormality is repaired according to abnormal information in the case of on-chip communication abnormality in the system on chip, the stability of on-chip communication is ensured, and the user experience is improved.

This invention relates to the field of chip design technology, and more particularly to a register access system based on a shared address, comprising a host subsystem and a chip subsystem. The host subsystem includes one physical functional module and N virtual functional modules. The chip subsystem includes a protocol conversion module, a register on-chip network, and M IP modules. Each IP module corresponds to a register address space, each register address space contains one or more register addresses, each register address corresponds to a register group, and each register group includes N+1 registers. Each of the N+1 registers in each register group corresponds one-to-one with the physical functional module and the N virtual functional modules. The host subsystem sends a register access request to the protocol conversion module through the physical functional module or the virtual functional module to access the target register. This invention can achieve effective isolation and flexible control between physical and virtual functions while ensuring efficient use of address resources.

The application discloses a kind of sideband signal communication configuration circuit for on-chip network mounting IP, belong to chip design field, comprising: low-speed protocol communication configuration interface module, AXB sideband communication interface module, on-chip network module.First, the request of reading and writing sideband signal register based on low-speed protocol of external equipment is received, protocol is converted into the request package of on-chip network form, is sent to each routing node by on-chip network module, then utilizes protocol decoding bypass mainband communication interface, enters the AXB sideband communication interface module of current node, connects the configuration bus of IP, controls the reading and writing request of IP sideband signal register, then when reading and writing request succeeds, original road returns reading and writing response to external equipment.The application can effectively improve the wiring congestion of large scale on-chip network, timing bottleneck, increase the bandwidth of data path and configuration path, reduce kernel address occupation, while also beneficial to the rapid expansion integration of on-chip network.

This invention provides an on-chip network verification method and device based on credit backpressure, belonging to the field of chip verification technology. This invention avoids the setup time violation risk of traditional rising-edge sampling by synchronously sampling the credit signal and the valid data signal on the falling edge of the clock, and can stably capture the signal state within the same clock cycle, solving the sampling deviation problem in scenarios where data transmission and credit return occur simultaneously. By combining the states of the two signals to determine the counter update method, it fully covers all signal combination scenarios, ensuring that the credit update logic completely matches the actual hardware behavior. Through credit overflow and underflow boundary checks before the update, it intercepts the risk of counting anomalies in advance. Simultaneously, it configures an independent credit counter for each virtual channel to avoid inter-channel interference, and performs flow control verification based on accurate credit counters, solving the problems of unreliable verification results and low scenario coverage caused by inaccurate counting.

The techniques described herein can relate to providing a programmable interconnection network (e.g., a programmable network-on-chip (NOC)). A method can include determining a transmission parameter, combining one or more lanes of the interconnection network based at least in part on the transmission parameter, and power gating any unused lanes after the combining.

Techniques for network-on-chip (NoC) memory addressable encryption and authentication. In an embodiment, NoC circuitry includes NoC routing circuitry, memory circuitry that stores a security parameter, and security circuitry that secures (e.g., encrypts and / or authenticates) a payload based on the security parameter. The security circuitry may secure the payload before the payload is packetized for transmission through the NoC, after the payload is de-packetized for output to an endpoint, or as the payload transits the NoC. The security circuitry may be centralized or distributed amongst access points of the NoC. Distributed security circuitry may exchange a security parameter over a secure link of the NoC circuitry. The security circuitry may include decryption circuitry that decrypts a response from a first endpoint before the response is packetized for transmission through the NoC, after the response is de-packetized for output to a second endpoint, or as the response transits the NoC.

This application provides a request scheduling method and system, relating to the field of chip technology. The method includes: when it is detected that at least one on-chip network of a first chip needs to send at least one access request to a second chip, obtaining at least one flow control status parameter corresponding to the first on-chip network; determining whether the first on-chip network meets the request scheduling conditions based on the at least one flow control status parameter and the first request type of the first access request corresponding to the first on-chip network; and if it is determined that the first on-chip network meets the request scheduling conditions, performing request scheduling on the first on-chip network based on the first weight of the first on-chip network to send the first access request to the second chip. This achieves fine-grained request scheduling based on flow control status parameters, request type, and weight, avoiding monopolization of transmission resources by a single on-chip network, ensuring orderly transmission of access requests from different on-chip networks, and improving transmission real-time performance and stability.

The application provides a residual neuromorphic processing architecture, which comprises 16 neuromorphic cores and an on-chip network communication, and introduces two mechanisms of double packet time division multiplexing and distributed pipeline synchronization on the basis of a traditional on-chip network router circuit, so that a high-throughput pipeline parallel inference without deadlock can be realized in a 16-core system with a 4*4 grid scale only by adding a small amount of state machine and a multiplexer circuit. The deadlock problem is solved by a double packet time division multiplexing control strategy, so that the MS and the pulse packet are alternately transmitted in time, and the routing deadlock caused by the mixed data flow is fundamentally avoided. The application improves the calculation accuracy, reduces the resource consumption and improves the throughput. Compared with the scheme without adopting the DP-TDM, the application is shortened by 29.37%. The system reaches a high throughput of 817.9K time steps / second, and the comprehensive performance is better than that of the existing scheme.

This invention discloses a hardware accelerator, device, and application method for sparse matrix-vector multiplication. The hardware accelerator includes an off-chip storage system, an on-chip network for data exchange routing, and an on-chip processing system for performing data fetching, multiplication calculations, and matrix row element merging. The off-chip storage system includes HBM channels for storing five types of data: column indices, row indices, vector values, matrix values, and result vectors. Each HBM channel includes an HBM stack and a memory controller. The HBM channels for storing vector values ​​are connected to the on-chip network via a L2 cache, while the remaining HBM channels are directly connected to the on-chip processing system. This invention aims to improve on-chip data reuse in hardware accelerators for sparse matrix-vector multiplication, reduce off-chip memory accesses, and improve the performance and energy efficiency of the hardware accelerator.

The application provides a data transmission method and device of an on-chip network, equipment and a storage medium, relates to the technical field of computers, and the method is applied to a transmission control node. The transmission control node is arranged on a transmission channel between a network interface of a first node and a second node. The first node sends messages to the second node through multiple transmission channels. The method comprises the following steps: acquiring a credit value of each transmission channel; the credit value reflects the number of empty positions of a buffer area of the transmission channel, and the credit value is positively correlated with the number of empty positions; selecting a target transmission channel from the multiple transmission channels according to the credit value; receiving a message transmission request sent by the first node and forwarding the message transmission request to the second node through the target transmission channel; and in the case that a response message returned by the second node is received, returning the identification of the target transmission channel to the first node through the network interface, so that the first node sends messages to the second node through the target transmission channel.

This disclosure provides a method, apparatus, and computer device for data routing in an on-chip network. The method includes: generating a target address code at a source node based on multiple destination nodes of a data routing task, wherein the target address code includes reference coordinates and a mask, and the value of each bit of the mask indicates whether the bit is a wildcard bit; determining a coverage area for the data routing task based on the reference coordinates and the mask; in response to determining based on the mask that the current node is not within the coverage area, performing unicast routing with the reference coordinates as the target node to route data packets of the data routing task to the next node; and in response to determining based on the mask that the current node is within the coverage area, determining a replication branch for routing data packets to route data packets of the data routing task to the corresponding target adjacent nodes from at least two output ports corresponding to at least two target adjacent nodes in the current node.

The application relates to the technical field of hard disks, in particular to a garbage collection method and system of a solid state disk controller based on a network on chip. The method comprises the following steps: selecting a garbage collection target block from a plurality of NAND flash memory blocks, identifying valid pages and reading the valid pages to a flash memory storage controller buffer; keeping valid page cache data and obtaining error analysis results; judging whether the valid pages need error correction according to the error analysis results and determining available target pages in a migration target block; directly writing the buffer valid pages into the available target pages when error correction is not needed, executing error correction by an error correction processing unit and writing the available target pages through network on chip interconnection when error correction is needed; cyclically executing the above steps for each valid page of the target block, and erasing the target block after migration is completed to recover storage space, so that the internal data transmission path of valid page migration is shortened, garbage collection latency is reduced, and the influence on host request processing performance is reduced.

Embodiments of the present disclosure provide a cache consistency processing method, a cache consistency processing device, a system on chip, a computer storage medium and a computer program product. The cache consistency processing method is used for managing cache consistency of processing units corresponding to each node of a network on chip. The cache consistency processing method comprises: unpacking a current monitoring packet received from an upstream routing node to obtain a current merging position of a current destination node set sharing a current routing node, wherein an initial merging position of an initial destination node set is generated by a cache consistency node and sent through an initial routing node; analyzing the current merging position to determine a downstream merging position of a downstream destination node set, wherein the downstream destination node set is at least part of the destination node set sharing a downstream routing node; and packaging the downstream merging position in a downstream monitoring packet and sending the downstream monitoring packet to the downstream routing node.

Disclosed are architectures of semiconductor integrated circuit (IC) device, more specifically an artificial intelligence (AI) accelerator. The AI accelerator comprises a processing block, a memory block disposed laterally side-by-side to each other and over a common substrate, and a logic base die vertically interposed between the common substrate and the memory block. The processing block comprises a computing die that comprises a plurality of parallel processing cores for processing artificial intelligence algorithms. The memory block heterogeneously integrated with the processing block through electrical connections formed in the common substrate. The memory block comprises a memory stack that comprises one or more vertically stacked memory die layers. The logic base die comprises one or more data communication interfaces between the memory block and the processing block. The data communication interfaces include at least a network on chip configured to electrically connect the memory block with each processing core.

One example provides a computing device (100) comprising a write communication channel (104) and an initiator device (120) connected to the write communication channel (104). The initiator device (120) has ordering rules for the write communication channel (104). Further, a network on a chip (NoC) device (112) is connected to the write communication channel (104). The NoC device (112) includes a reorder buffer (118). The computing device (100) also comprises a hardware memory barrier (HMB) device (102) connected to the write communication channel (104) such that at least a portion (132) of the write communication channel (104) is routed through the HMB device (102).

The embodiment of the disclosure provides a consistency transaction processing method and a network-on-chip system. The method comprises the following steps: a directory node receives a first request for a target cache line of a slave node from a first request node; the directory node receives a second request for the target cache line of the slave node from a second request node, wherein the directory node receives the second request before receiving an acknowledgement completion message for the first request; if it is determined that a non-blocking processing condition is met according to a current directory state of the directory node and a request type of the second request, the directory node processes a transaction corresponding to the second request without receiving the acknowledgement completion message for the first request. The embodiment of the disclosure can process the transaction corresponding to the second request without waiting for the acknowledgement completion message of the first request when the non-blocking processing condition is met, thereby improving parallelism, reducing access latency, and improving the operation efficiency and performance of the whole system.

The application discloses a brain-like chip hardware acceleration method and system, relates to the related field of brain-like computing, and comprises the following steps: collecting heterogeneous time sequence data streams in real time through a multi-modal sensor array on an industrial device; performing event detection to generate a sparse pulse event stream; deploying a brain-like chip, which internally integrates a pulse neural network and an on-chip network of a memory-computing integrated architecture; inputting the sparse pulse event stream into the brain-like chip, distributing the pulse events through the on-chip network, performing asynchronous event-driven parallel processing on the sparse pulse event stream by using a dynamic calculation distribution mechanism of the pulse neural network, and obtaining a real-time state feature vector of the industrial device; and fusing and reasoning with a pre-stored device health knowledge graph to generate a control instruction or a fault early warning signal. The application solves the technical problems of slow calculation speed, low efficiency and poor real-time performance of existing data processing systems, achieves real-time and efficient processing of industrial data, and further improves the technical effects of device operation stability and reliability.