36 results about "System on chip design" patented technology

A bus architecture system to provide concurrency, fabricated on an integrated circuit for a system on chip design, for connecting a plurality of bus masters to a plurality of bus slaves. The system includes a plurality of multiplexers in communication with each data in port of each bus master and each bus slave. The system also includes a plurality of isolated data paths connecting the port out of each bus master to each multiplexer in communication with each data in port of each bus slave, and a plurality of isolated data paths connecting the port out of each bus slave to each multiplexer in communication with each data in port of each bus master, thereby providing concurrency on the system on chip design. In addition a distributed arbitration is included to allow each bus slave to be selected independently of the other bus slaves.

A method and system to facilitate a scalable scan system in the design of a system-on-chip. In one embodiment of the invention, the system-on-chip includes a controller and one or more clock gating units. The clock gating unit is added to each unique clock domain of each function or logic block in the system-on-chip. By having a controller that connects to each clock gating unit and the scan input and output signals in each logic block of the SOC, this allows a scalable scan system in the design of the SOC and allows frequent block level design changes in the SOC without extensive changes to the scan logic in one embodiment of the invention. In addition, the scalable scan system also allows at-speed scan write-through testing of a memory array that can improves the scan test coverage of the system-on-chip.

The present invention proposes a new asymmetric-lightly-doped drain (LDD) metal oxide semiconductor (MOS) transistor that is fully embedded in a CMOS logic. The radio frequency (RF) power performance of both conventional and asymmetric MOS transistor is measured and compared. The output power can be improved by 38% at peak power-added efficiency (PAE). The PAE is also improved by 16% at 10-dBm output power and 2.4 GHz. These significant improvements of RF power performance by this new MOS transistor make the RF-CMOS system-on-chip design a step further. Index Terms—Lightly-doped-drain (LDD), metal oxide semiconductor field effect transistor (MOSFET), metal oxide semiconductor (MOS) transistor, radio frequency (RF) power transistor.

A method (400) and system (10) for managing interrupts in a system on a chip design that includes multiple processors (100a, 100b, ..., 100n) coupled to multiple peripheral devices (120a, 120b, ..., 120m). A plurality of interconnected interrupt controllers (110a, 110b, ..., 110n) are coupled between the processors and the peripheral devices. Interrupts generated by the peripheral devices are received by all of the interrupt controllers. In one embodiment, an interrupt controller is paired with a processor. Each interrupt controller can identify which interrupts will be passed to its respective processor. The interrupt controllers work in concert to pass each interrupt to a particular processor.

A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This is accomplished by planning the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations. The established plan is then applied with communications between power supply integrated circuits and load system-on-chip.

Testing of the test signal connections to a functional block of circuitry within an integrated circuit is made using wrapper serial scan chain cells of a wrapper serial scan chain. These wrapper cells can then be used to validate that the correct signals are reaching test signal inputs and the correct signals are reaching their destination from test signal outputs when that functional block of circuitry is incorporated within a larger design, e.g., a system-on-chip design.

The invention discloses a self-holding analog core testing shell in the technical field of system on chip designs of electronic information technology, comprising an analog test input motivating pathway, a self-holding analog testing interface, a test controller, an output analog switch and an analog test response outputting pathway, wherein the analog test input motivating pathway is connected with the self-holding analog testing interface; the self-holding analog testing interface is connected with the test controller; the test controller is connected with the output analog switch; the output analog switch is connected with the analog test response outputting pathway; and the self-holding analog testing interface and the output analog switch are respectively connected with an analog core. By means of the self-holding analog core testing shell provided by the invention, the motivation applying and the response analyzing of the analog test of multiplexing of multiple ports of single DAC (Digital-Analog Converter) and ADC (Analog-Digital Converter) are realized.

A method of producing an integrated circuit (700) using a system-on-chip (SoC) architecture includes providing a first circuit (710) in a first island of synchronicity (IoS); and providing a source-synchronous data link (755/757, 765/767) between the first circuit (710) in the first IoS and a hard core (720) in a second IoS for communicating n-bit data elements between the first circuit (710) and the hard core (720). The source-synchronous data link (755/757, 765/767) includes a set of n data lines (755, 765) for transporting the n-bit data elements between the first circuit (710) and the hard core (720), and a source- synchronous clock line (757, 767) for transporting a source clock between the first circuit (710) and the hard core (720) for clocking the n-bit data elements. The hard core (720) does not include a bus interface adaptor for interfacing with the source-synchronous data link (755/757, 765/767).

A data reading method for motion estimation in an embedded system is provided. The embedded system includes an external memory device and a video encoding device, wherein the external memory device stores a first frame, and the video encoding device has an internal memory. First, a second frame is divided into M×N sub frame sets, wherein each of the sub frame sets has O×P sub frames. Then, each of the sub frame sets is selected in a calculation sequence, and the selected sub frame set is stored into the internal memory. Next, a predicted search path of each sub frame in the selected sub frame set is calculated. Thereafter; a predicted reading range is determined, wherein the predicted reading range includes the predicted search paths of the sub frames. Finally, a comparison data is read from the first frame according to the predicted reading range.

The invention discloses a pixel-level time and intensity digital conversion circuit. The invention achieves a pixel-level time and intensity digital conversion circuit, for one-time laser pulse, all pixel units can give time information and intensity information of echo signals, in the data reading stage, a row and column selection control circuit is not needed, and all pixel information of each row is read sequentially, thereby greatly improving the working frequency of an area array reading circuit; the information representing the time and intensity of the echo signals is directly output ina digital format, and an on-chip ADC is not required to be quantified twice, thereby reducing the difficulty of design of the on-chip system.

Computer system for programmable built-in self-test (PMBIST) insertion into system-on-chip designs comprising one or more memories, including at least one processor and computer-executable instructions that cause the system to determine a PMBIST configuration based on one or more test configuration files; generate one or more package files based on the PMBIST configuration; insert PMBIST hardware into the SoC design based on the package files and characteristics of the memories; suspend PMBIST hardware insertion after an event related to the package files; and resume PMBIST hardware insertion after receiving one or more updated package files. In some embodiments, the package files are independent of vendor-specific memory models. In some embodiments, the package files comprise a plurality of data structures. Exemplary methods and computer-readable media can also be provided embodying one or more procedures the system is configured to perform.

The invention belongs to the field of system-on-chip design, and provides a system for realizing low-voltage real-time detection of an SoC chip and a detection method thereof. Wherein the register bank within the CPU comprises a plurality of registers corresponding to different voltage levels of the VBAT voltage respectively, The processor of the on-chip power management module performs step-by-step monitoring of the VBAT voltage according to the value of each register to generate the corresponding interrupt, and the CPU performs a low-power process according to the fast response of the interrupt type. Through the setting of multiple VBAT voltage grades, multiple VBAT voltage grades can be monitored at the same time, early warning, enriching the low-voltage detection function, and expanding the application range.

Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete system-on-chip testing, to ensure both the circuit reliability and performance of system-on-chip design. As an added advantage, development costs are reduced for system-on-chip applications.