3 results about "System on chip design" patented technology

The embodiment of the invention provides a system-on-chip design method and device, a deadlock detection method and device, electronic equipment and a storage medium. The system-on-chip design method comprises the steps that a network-on-chip included in a system-on-chip in design is mapped into a first directed connected graph; determining a first directed connectivity dependency graph according to the first directed connectivity graph and a routing algorithm of the network-on-chip; mapping subsystems included in the system-on-chip in the design into a second directed connected graph; determining a second directed connectivity dependency graph according to the second directed connectivity graph and a logic routing algorithm of the subsystem; determining a third directed connected graph according to the first directed connected graph and the second directed connected graph; determining a third directed connectivity dependency graph according to the first directed connectivity dependency graph and the second directed connectivity dependency graph; and performing deadlock detection on the system-on-chip in design according to the third directed connectivity graph and the third directed connectivity dependency graph, and optimizing the system-on-chip in design according to a deadlock detection result. According to the scheme, the design cost of the system-on-chip can be reduced.

This disclosure provides a method, apparatus, device, medium, and product for access verification in on-chip networks (NoCs), relating to integrated circuit design and verification and System-on-Chip (SoC) design technologies, particularly in the areas of NoC security verification, access control, and access control isolation verification. The specific implementation scheme is as follows: a routing access permission file is parsed to obtain access permission paths and self-test instances; the self-test instances are executed to obtain self-test results; the self-test results and the routing access permission file are compared and verified to obtain a verification result; if the verification result fails, the access permission paths in the routing access permission file are modified until the verification result passes; routing tests are performed in a UVM environment based on the modified access permission paths to obtain the access verification result. This technical solution can shorten the access verification cycle of on-chip networks.

Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA). The attribute mismatch is provided for further design or timing constraint modifications and / or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (SDC).