10 results about "System on chip design" patented technology

A system-on-chip design method and apparatus, a system-on-chip, and an electronic device, the system-on-chip comprising: a network-on-chip, the network-on-chip comprising a network routing component, the network routing component being arranged in a top module; and a plurality of subsystem modules, wherein on-chip interconnection is realized among the plurality of subsystem modules through the network routing component.

The embodiment of the invention provides a system-on-chip design method and device, a deadlock detection method and device, electronic equipment and a storage medium. The system-on-chip design method comprises the steps that a network-on-chip included in a system-on-chip in design is mapped into a first directed connected graph; determining a first directed connectivity dependency graph according to the first directed connectivity graph and a routing algorithm of the network-on-chip; mapping subsystems included in the system-on-chip in the design into a second directed connected graph; determining a second directed connectivity dependency graph according to the second directed connectivity graph and a logic routing algorithm of the subsystem; determining a third directed connected graph according to the first directed connected graph and the second directed connected graph; determining a third directed connectivity dependency graph according to the first directed connectivity dependency graph and the second directed connectivity dependency graph; and performing deadlock detection on the system-on-chip in design according to the third directed connectivity graph and the third directed connectivity dependency graph, and optimizing the system-on-chip in design according to a deadlock detection result. According to the scheme, the design cost of the system-on-chip can be reduced.

This disclosure provides a method, apparatus, device, medium, and product for access verification in on-chip networks (NoCs), relating to integrated circuit design and verification and System-on-Chip (SoC) design technologies, particularly in the areas of NoC security verification, access control, and access control isolation verification. The specific implementation scheme is as follows: a routing access permission file is parsed to obtain access permission paths and self-test instances; the self-test instances are executed to obtain self-test results; the self-test results and the routing access permission file are compared and verified to obtain a verification result; if the verification result fails, the access permission paths in the routing access permission file are modified until the verification result passes; routing tests are performed in a UVM environment based on the modified access permission paths to obtain the access verification result. This technical solution can shorten the access verification cycle of on-chip networks.

A method to generate a hardware design for an electronic device wherein a digital hardware design under test (DUT) for the electronic device is received in a test environment, the digital hardware DUT having an input with a connected buffer; receiving assertions relating to the digital hardware DUT and the buffer; inputting watched data into the buffer; using a state machine to verify the assertions; detecting a deadlock or livelock in the digital hardware DUT in dependence on the verification; and in response to detecting a deadlock or livelock in the digital hardware, providing an output indicative of a deadlock or livelock state detected in the digital hardware DUT. The method may be used in simulation verification or formal verification, e.g. dynamic simulation, particularly for system-on-chip (SoC) designs where computing elements are connected by a fabric or a bus. The DUT may be a high-level language description of a component of a SoC. The buffer may be part of the DUT or a test bench and the watched data may be symbolic data. Assertions may be provided in SystemVerilog Assertions (SVA), Property Specification Language (PSL) or Open Verification Language (OVL). The state machines may be finite state machines (FSM).

Systems and methods for assembling and developing a System-on-a-chip (SoC) by using templates and designer input data are described. One of the methods includes receiving a request for generating a design of the SoC. In response to the request, a template database is accessed to provide templates of a plurality of designs of systems-on-chips (SoCs). Each of the templates is for a technology application. The method includes receiving a selection of one of the templates. The one of the templates represents components of the SoC. The method also includes receiving a configuration file including configuration data input for the components of the SoC. The method includes compiling the configuration file and a definition file for the SoC to generate design files for the SoC.

The invention provides a verification method and device and related equipment. The method comprises the steps that conversion relation mapping information, module design information of a functional module and system-on-chip design information of a system-on-chip are acquired; the conversion relation mapping information is used for indicating a mapping relation of each module in the functional module converted to a hierarchical instance name of the system on chip; generating an actual connection relation table and a target connection relation table based on the conversion relation mapping information, the module design information of the functional module and the on-chip system design information of the on-chip system; the actual connection relation table is used for indicating the actual connection relation between the modules of the corresponding function modules in the system on chip, and the target connection relation table is used for indicating the target connection relation between the modules of the corresponding function modules in the system on chip; and comparing the actual connection relation table with the target connection relation table, and determining the connection correctness between the modules of the corresponding functional modules in the system on chip. According to the method, the connection correctness between the modules of the corresponding functional modules in the system on chip can be confirmed.

The present application discloses a firmware data loading method, system, device and storage medium, which are applied to the field of system-on-chip design technology, including: after the SoC system is powered on, receiving each read instruction sent by the SoC system; when receiving any one read instruction, determining whether the data content specified by the read instruction is cached; if so, feeding back the data content specified by the read instruction in the cache to the SoC system; otherwise, reading the data content in parallel based on N blocks of firmware data memories, arranging the read data and placing it in the cache, and feeding back the data content specified by the read instruction in the cache to the SoC system; wherein each of the N blocks of firmware data memories stores complete SoC system startup firmware data, and N is a positive integer not less than 2. Applying the solution of the present application can improve the firmware data reading speed and ensure the reliability of the SoC system.

Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA). The attribute mismatch is provided for further design or timing constraint modifications and / or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (SDC).

The invention relates to the technical field of ZYNQ system-on-chip (SOC) design, and discloses an AXI4 bus-based self-defined direct memory access implementation method and an AXI4 bus-based self-defined direct memory access implementation system. The method comprises the following steps: firstly, converting a data bit width of a user side into a data bit width adaptive to AXI4 through a write channel to obtain spliced data; writing the spliced data into a buffer FIFO for buffering, converting the spliced data in the FIFO into an AXI4 interface signal, and moving the AXI4 interface signal to a dynamic random access memory DDR3 of a PS end; and then data in a dynamic random access memory DDR3 of the PS end is transferred to a buffer FIFO through a read channel, and the data in the buffer FIFO is read and split into the data bit width of the user end. Therefore, the self-defined DMA based on the AXI4 bus has the advantages that the interface can be self-defined, the flexibility is controllable, less logic resources are consumed, the configuration process is simple, the portability is higher and the like, and the localization requirement can be met.