33 results about "Core level" patented technology

A device is provided which includes a first microprocessor core to generate a first output signal; a second microprocessor core to generate a second output signal; a switching fabric having a first input / output port; and lockstep logic, coupled between the first input / output port of the switching fabric and the first and second microprocessor cores, to detect whether the first output signal differs from the second output signal.

Voltage islands enable a core-level power optimization of ASIC / SoC designs by utilizing a unique supply voltage for each cluster of the design. Creating voltage islands in a chip design for optimizing the overall power consumption consists of generating voltage island partitions, assigning voltage levels and floorplanning. The generation of voltage island partitions and the voltage level assignment are performed simultaneously in a floorplanning context due to the physical constraints involved. This leads to a floorplanning formulation that differs from the conventional floorplanning for ASIC designs. Such a formulation of a physically aware voltage island partitioning and method for performing simultaneous voltage island partitioning, level assignment and floorplanning are described, as are the definition and the solution of floorplanning for voltage island based designs executed under area, power, timing and physical constraints. The physical planning of voltage islands includes: a) characterizing cell clusters in terms of voltages and power consumption values; b) providing a set of cell clusters that belong to a single voltage island Random Logic Macro (RLM); and c) assigning voltages for the voltage island RLMs, all within the context of generating a physically realizable floorplan for the design.

The invention discloses a method and a device of detection processing of a core-level rootkit. The method comprises the following steps of A, pre-storing a new loading module node signature at a current node of a core module chain table, and storing a current node signature into a new loading module node; B, loading a new module, judging whether the signature stored in the new loading module node is matched with the current node signature or not, judging whether the signature stored in the current node is matched with the new loading module node signature or not, if one is not matched, preforming the step C; C, comparing a currently operational system call table with a spare system call table, if not consistent, generating a report of discovering a hidden module. According to the method and the device, invasion of the rootkit is detected by setting a mutually matching mechanism of the new loading module and the current node signature of the chain table, and the report is further affirmed through comparing the system call table with a spare reference file, so that the reliability of a detection result is improved, and meanwhile, through setting a system recovery method, safety operation of the system is ensured.

Voltage islands enable a core-level power optimization of ASIC / SoC designs by utilizing a unique supply voltage for each cluster of the design. Creating voltage islands in a chip design for optimizing the overall power consumption consists of generating voltage island partitions, assigning voltage levels and floorplanning. The generation of voltage island partitions and the voltage level assignment are performed simultaneously in a floorplanning context due to the physical constraints involved. This leads to a floorplanning formulation that differs from the conventional floorplanning for ASIC designs. Such a formulation of a physically aware voltage island partitioning and method for performing simultaneous voltage island partitioning, level assignment and floorplanning are described, as are the definition and the solution of floorplanning for voltage island based designs executed under area, power, timing and physical constraints. The physical planning of voltage islands includes: a) characterizing cell clusters in terms of voltages and power consumption values; b) providing a set of cell clusters that belong to a single voltage island Random Logic Macro (RLM); and c) assigning voltages for the voltage island RLMs, all within the context of generating a physically realizable floorplan for the design.

The invention relates to the structure static load test technology and particularly relates to a multi-bonding point high-load inclined pushing-type loading device. The device comprises a step type force transmission tool (20), inclined columns (23), P1-P8 loading equipment (24), a test platform (25), a foundation (29), P3-P16 loading equipment (22), P9-P12 loading equipment (21), bearing bases (30), wedge form supports (31), 400 ton pressure type dynamometers (32), force transmission pressure bars (33), high bearing bulb nest combinations (35) and loading tools (34). The P1-P8 loading equipment (24) provide upward loads in an axial direction. The loading tools (34) are connected to a test piece and provide upward loads in an oblique direction for the test piece. With the adoption of the multi-bonding point high-load inclined pushing-type loading device, the core level front bonding low temperature combined static load test can be smoothly completed, and a sound test technical reserve is provided for enforcement and conduction of the follow-up type low temperature static load test.

Systems and methods for packet switching in a network, including two or more hybrid packet / circuit switching network architectures configured to connect two or more core level switches in the network architectures, the network architectures being controlled and managed using a centralized software defined network (SDN) control plane. An optical ring network may be configured to interconnect the two or more hybrid network architectures, and one or more hybrid electrical / optical packet / circuit switches configured to perform switching and traffic aggregation. One or more high-speed optical interfaces and one or more low-speed electrical / optical interfaces may be configured to transmit data.

A method and system for digitally controlled multi-frequency clocking are provided. The method includes receiving a system reference oscillator clock frequency at a microprocessor including multiple cores. The system reference oscillator clock frequency provides a reference frequency to a local oscillator. The local oscillator supplies a core clock frequency to at least one of the cores. The method further includes adjusting the local oscillator to output the core clock frequency at a frequency greater than the system reference oscillator clock frequency as a function of digital frequency characteristic data associated with the core or cores. The method supports extendibility to larger systems and may support enhanced power management through frequency adjustments at the core level.

The invention discloses a cross-regional disaster recovery method and device. The method comprises the following steps of respectively deploying cloud networks in two partitions, wherein each of the two cloud networks is provided with a computing resource layer, a database layer and a storage layer; and respectively carrying out monitoring and disaster recovery on the computing resource layer, thedatabase layer and the storage layer. According to the method and the device, the cross-regional disaster recovery of hierarchical management is realized through the cloud network, the deployment cost is low, the switching time is short, no negative influence is generated on services, and the time for cross-regional disaster recovery can be shortened. Furthermore, cross-regional disaster recoveryis achieved on the computing resource layer, the database layer and the storage layer respectively, so that a complete cloud disaster recovery scheme is achieved, and a problem of local disaster recovery and even remote disaster recovery of the important and core-level services and above is solved.

The invention relates to a method for realizing kernel level process lib based on embedded Linux operating system, which realizes an integral kernel process manage system, provides kernel process management, signal amount management, memory management and log management, and AIP function interface of the function subgroup of standard C lib. The invention has the advantages that 1, the invention can modify little on kernel to support the software real-time or hardware real-time calling mechanism of prior embedded Linux operating system and confirm the application real-time demand, 2, the invention can completely eliminate the consumption of repeated switch of application process between user state and kernel state, to improve the integral performance of embedded Linux application system, 3,the invention shields the complexity of kernel module programming, to provide a development frame for developers and a series of programming interfaces (API), thereby reducing development and application complexity and improving development efficiency.

In the static noise check of the LSI hierarchical design, in order to reduce the data volume of the common parts and load of the design operation and design automation, when a plurality of cores, comprising same sub-chips, are present, the static noise check data for the whole chip is generated from the core-level design data of one of the cores, and the chip-level design data.

A reflection surface 12 constituted by a transition metal having a core level absorption edge in the vicinity of a wavelength of a soft X-ray is formed on an inside of a vacuum vessel 14, and furthermore, there is provided a permanent magnet 13 for generating a magnetic field in a perpendicular direction to a longitudinal direction of the vacuum vessel 14 in a position of the reflection surface 12 by which the soft X-ray is to be reflected, and the soft X-ray to be linearly polarized light incident on the vacuum vessel 14 is reflected at plural times over the reflection surface 12 in a position where the magnetic field is applied in such a manner that magnetic scattering is increased by a resonant effect of a magnetic circular dichroism when the soft X-ray is reflected by the reflection surface 12. Thus, a great difference in a refractive index is made between circularly polarized counterclockwise light and circularly polarized clockwise light which constitute the linearly polarized light, and a phase difference between the circularly polarized counterclockwise light and the circularly polarized clockwise light is obtained at a time. Consequently, it is possible to reversibly convert the soft X-ray from the linearly polarized light into the circularly polarized light or from the circularly polarized light into the linearly polarized light by a reflection to be carried out at only several times.

This invention discloses a cluster-processor expansion method by flexible allocation of computing resource, and its steps are: (1) setting the array of microcontroller, which is composed of two or more microcontrollers, adding a reading cluster interface for each microcontroller in SRF, and each microcontroller has the same structure and same interface with cluster controller, to start implementation of a core-level procedure under the control of cluster controller, (2)setting interfaces between microcontroller and operational group, (3) setting the cluster controller and adding interfaces connected with each microcontroller on it,(4) setting Clusterop in the controller, to make a core-level procedure implement only in a microcontroller and some computing group ensuring that many microcontrollers executes the procedure at the same time with the permission of computing resources.

The invention discloses a method and a device for measuring energy band bending by photoelectron energy spectrum. The method includes: obtaining the core level photoelectron spectrum of the sample to be tested under N different photoelectron emission angles; N is an integer and N≥4; according to the theoretical relationship between the core level photoelectron spectrum and the corresponding photoelectron emission angle, the photoelectron The theoretical relationship between the emission angle and the corresponding integration depth and the core level photoelectron spectrum under different photoelectron emission angles respectively obtain the energy level values ​​corresponding to N different integration depths; the photoelectron emission angle corresponds to the integration depth one by one; according to the energy The theoretical relationship between the level value and the integration depth, the N integration depths and the energy level values ​​corresponding to each integration depth are fitted to obtain the surface core energy level; the surface core energy level is the corresponding core energy level when the integration depth is 0; according to The theoretical relationship between the energy band bending and the surface core energy level and the value of the surface core energy level can be used to obtain the size of the energy band bending of the sample to be tested. Thereby, the measurement accuracy of band bending can be improved.

This invention discloses a instruction control method for streaming processor, which divides the instruction control into flow-level process and core-level process, the flow-level process is responsible for data scheduling between calculation core and off-chip memory, the core-level process completes data calculation, and the steps is: (1) initializing scalar data of the core-level procedure, (2) preparing vector data for the core-level procedure, (3) start executing the core-level procedure, (4) executing the procedure, (5) storing vector data generated by the procedure into the off-chip memory, (6) reading scalar result of the procedure.

A method for correcting astigmatism of an electronic optical column of an electron emission spectromicroscope, comprising the steps of:forming a reference structure on a surface of a sample comprising a structure of interest to be imaged,imaging the reference structure by the spectromicroscope with secondary electrons and with core level photoelectrons,eliminating astigmatism defects appearing during the imaging of the reference structure with secondary electrons and with core level photoelectrons,a material of the reference structure being chosen such that, during core level photoelectron imaging, the contrast C between the average intensity Ia of the material of the reference structure and the average intensity Ib of the material of the sample is such that:C=Ia-IbIa+Ib≥0.2.