1363results about "Architecture with multiple processing units" patented technology

A Super System is disclosed and its inputs / outputs are coupled with a Mach-Zehnder interferometer (MZI), wherein the Mach-Zehnder interferometer (MZI) can be coupled with a first optical waveguide either in a two-dimensional (2-D) or in a three-dimensional (3-D) arrangement. The first optical waveguide can be then coupled with (i) a semiconductor optical amplifier (SOA) and / or (ii) a second optical waveguide (that can include an optical resonator) either in a two-dimensional (2-D) or in a three-dimensional (3-D) arrangement. The Super System can include multipliers of matrices and graphic processors.

A multi-scale cascaded hourglass depth map completion method guided by RGB image is presented. [Solution] The multi-scale cascade hourglass depth map completion method includes step S1 of obtaining a sparse depth map to be completed and a corresponding RGB color guide image, performing channel-dimensional pre-processing on the sparse depth map and the RGB color guide image and connecting them in series to obtain a target RGB_D image to be processed, step S2 of inputting the target RGB_D image to be processed into a trained depth map completion network model including an early fusion encoder, a sparse depth map teaching module, a multi-scale hourglass completion module and an optimization reinforcement module, and step S3 of obtaining the output of the optimization reinforcement module as a completed dense depth map.

The invention relates to the technical field of ultra-low power consumption microcontrollers, and discloses an ultra-low power consumption microcontroller architecture design method and system, and the method comprises the steps: constructing a heterogeneous dual-core processor comprising a high-performance core and a low-power consumption core, and dividing the heterogeneous dual-core processor into a plurality of independent power domains; constructing a sub-threshold voltage operation system on a plurality of independent power supply domains, and configuring a multi-layer storage structure in the heterogeneous dual-core processor; recording task characteristic data by using a multi-level storage structure, executing task dynamic allocation between dual cores, and creating a dynamic task allocation mechanism; and performing static analysis and function block division on the application code based on a dynamic task allocation mechanism to obtain a plurality of function code blocks, and performing storage hierarchy and processor core allocation on the plurality of function code blocks to obtain a function code allocation result. According to the method, the dynamic migration of the workload and the optimal resource allocation are realized, and the energy consumption of the microcontroller in various working scenes is reduced.

The invention discloses an RISC-V vector optimization method, device and equipment based on thread scheduling, relates to the field of digital integrated circuit design, and is used for solving the problems of operation resource waste, relatively low operation efficiency and performance reduction caused by memory access performance limitation in the prior art. Comprising the following steps: acquiring an RISC-V vector instruction, extracting decoding information from the RISC-V vector instruction, and acquiring register configuration information in a vector state; determining thread scheduling information according to the decoding information, the register configuration information, the current thread execution state and hardware configuration; executing a corresponding thread task according to the thread scheduling information; after execution is finished, if the thread task of the current instruction is executed, updating the state and delivering the current instruction; otherwise, updating the state and executing the next thread task until all the thread tasks are executed, writing back the data, completing instruction delivery and ending the instruction cycle. According to the method, the vector instruction execution performance under memory access performance limitation can be effectively improved, and the overall operation performance is improved.

The embodiment of the invention provides a matrix and vector operation device based on an RISC-V extension instruction, the device comprises a coprocessor and a main processor which are connected with each other, an RISC-V instruction set and a coprocessor extension instruction set are configured in the main processor, the RISC-V instruction set comprises a vector extension instruction set related to a vector operation task, and the coprocessor extension instruction set comprises a coprocessor extension instruction set related to the vector operation task. The coprocessor extension instruction set comprises a matrix processing instruction set related to a matrix operation task, and the main processor is configured to send the matrix processing instruction set related to the matrix operation task or a vector extension instruction set related to a vector operation task to the coprocessor when a calculation task is executed, the computing task is executed in parallel with the coprocessor; the coprocessor is configured to execute a matrix operation task unloaded by the main processor according to the matrix extension instruction set to obtain an execution result of the matrix operation task; or executing the vector operation task unloaded by the main processor according to the vector extension instruction set to obtain an execution result of the vector operation task.

Implementing asymmetric processor cores to enable higher operating frequencies in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a core cluster that comprises a plurality of processor cores and a corresponding phase-locked loop (PLL). Each processor core is based on a common instruction set architecture (ISA) and is configured to operate synchronously based on a same clock signal from the PLL of the core cluster. A first subset of processor cores within the core cluster is implemented with a different physical characteristic relative to a second subset of processor cores within the core cluster, wherein the different physical characteristic enables each processor core of the first subset of processor cores to operate at a higher operating frequency than each processor core of the second subset of processor cores.

One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread architecture, the general-purpose graphics compute unit to concurrently execute the first instruction and the second instruction.

The invention provides a training strategy determination method for a computing power cluster using chips of various models in a mixed mode and a related device, and relates to the technical field of graphic processing chips, computing power clusters, large models, model training and the like. The method comprises the following steps: determining each target model chip forming a computing power cluster and a corresponding quantity proportion; for each target model chip, determining performance evaluation of the target model chip in a preset performance type and weight distribution of each performance type under each alternative training strategy; for each alternative training strategy, performing weighting processing on the performance evaluation under each corresponding preset performance type in combination with each corresponding number proportion by using the weight distribution, matched with each target model chip, of the alternative training strategy, so as to obtain corresponding comprehensive training evaluation; and determining a target training strategy based on the evaluation parameter of each comprehensive training evaluation. By applying the scheme, the training strategy which is suitable for being used by the computing power cluster which mixedly uses multiple types of chips during training of a large model can be quickly determined at low cost.

The present application discloses a compute-in-memory chip, an instruction scheduling method, and a related apparatus. The compute-in-memory chip comprises an instruction memory, an instruction scheduler, and at least one compute-in-memory memory; each compute-in-memory memory comprises at least one storage array; the instruction memory is used for acquiring a first tensor instruction to be executed; and the instruction scheduler is used for scheduling, on the basis of the association relationship between the first tensor instruction and a second tensor instruction and the state of a target storage array needing to be operated for executing the first tensor instruction, the first tensor instruction to the compute-in-memory memory to which the target storage array belongs so that the compute-in-memory memory executes the first tensor instruction. According to embodiments of the present application, diversified compute-in-memory computing can be supported, efficient out-of-order execution scheduling of a tensor instruction set is achieved on the basis of the compute-in-memory chip, and the requirements of compute-in-memory technology for high concurrency and high throughput rate are met.

[Problem] To enable generation of more effective advertisements. [Solution] An information processing device comprising a control unit that edits a tag group obtained by converting advertisement content to text, extracts a derivable element from the advertisement content, and generates, by deriving the corresponding element according to the edited tag group, derived advertisement content based on the advertisement content.

The invention relates to the technical field of artificial intelligence chips, and discloses a data processing method and device, a processor and electronic equipment. Determining a first jump step length required for rearranging the block data based on the block size of the input data in the first dimension; secondly, performing jump reading on the block data according to a first jump step length, rearranging and loading read input elements into a thread private register so as to realize transposition storage of the block data in the thread private register, and mapping a thread direction on a second dimension so as to obtain a data basis of convolution correlation calculation; convolution correlation calculation is executed based on the transposed data in the thread private register and the weight data in the thread private register, repeated data reading in the calculation process is reduced during sliding window calculation, and an operator is converted into calculation performance bottleneck operation from memory access performance bottleneck operation.

Embodiments are directed to an integrated circuit with multiple dies connected in a die-to-die (D2D) configuration. The integrated circuit can include a first die and a second die connected to the first die via a D2D interface circuit in the D2D configuration forming a D2D structure with the first die. The D2D interface can connect a first plurality of superlanes of the first die with a second plurality of superlanes of the second die for streaming data between the first die and the second die along a first direction or a second direction orthogonal to the first direction.

A multi-core processor according to some example embodiments may be a multi-core processor including a plurality of cores, and may include a first core that receives a task migration instruction, and transmits metadata including branch prediction data obtained during execution of a migration subject task determined as a subject of the task migration instruction among a plurality of tasks, to an external memory, and a second core that receives a task execution instruction, and reads the metadata from the external memory on the basis of the task execution instruction, and executes the migration subject task using the metadata.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The embodiment of the invention provides a vector data processor, an instruction processing method, a system on chip and computing equipment, the vector data processor comprises a data access unit and a vector floating point unit, the data access unit comprises a temporary register, and the vector floating point unit comprises a vector register; the data memory access unit is used for responding to a vector memory access instruction, performing memory access of target vector data on a memory and updating a temporary register based on the target vector data, and the vector memory access instruction is obtained by splitting a mask vector memory access instruction; and the vector floating point unit is used for reading the target vector data from the temporary register and writing back the corresponding target element in the target vector data to the vector register based on the mask vector. The hardware design is optimized, the complexity is effectively reduced, the power consumption is controlled, the performance frequency is effectively improved, the area of a vector data processor is reduced, and the innovative scheme provided by the embodiment of the specification can be used for an RISC-V instruction set chip.

The invention belongs to the field of integrated circuits and computer system structures, and provides a caching method and system for a memory access unit of a superscalar processor, and the method comprises the steps: receiving a plurality of memory access instructions in the same period, and determining a corresponding Bank in a to-be-accessed cache through the memory access instructions; after the memory access instruction obtains a cache access permission, if cache line missing occurs, generating a missing request, merging all the missing requests, and performing parallel prefetching training on the merged missing requests by utilizing a mode of fusing a constant step length prefetching mode and a complex step length prefetching mode to obtain a prefetching request and a prefetching cache address corresponding to the prefetching request; requesting a missing cache line from the first-level cache to the second-level cache based on the missing queue, and writing the missing cache line back to the cache line of the corresponding data cache in the first-level cache; and storing the bus consistency request by using the sniffing queue, judging whether the data in the multi-core cache are consistent or not by using the consistency request, and performing consistency modification according to a judgment result. The cache hit rate and the bandwidth utilization rate are improved.

Circuitry comprises processing circuitry configured to execute program instructions in dependence upon respective trigger conditions matching a current trigger state and to set a next trigger state in response to program instruction execution; the processing circuitry comprising: instruction storage configured to selectively provide a group of two or more program instructions for execution in parallel; and trigger circuitry responsive to the generation of a trigger state by execution of program instructions and to a trigger condition associated with a given group of program instructions, to control the instruction storage to provide program instructions of the given group of program instructions for execution.

Processors, systems and methods are provided for thread level parallel processing. A processor may include a sequencer and a plurality of columns of vector processing units coupled to the sequencer. The sequencer may include a scalar instruction decoder, a vector instruction decoder, and a plurality of scalar processors configured to concurrently execute one or more scalar instructions decoded by the scalar instruction decoder to generate one or more vectors of parameters. The vector instruction decoder may be configured to decode one or more vector instructions to generate a set of configurations with the one or more vectors of parameters embedded as one or more vectors of immediate values and send the configurations to a target column. Each column of vector processing units may be configured to repeatedly execute the vector operations in the configurations using one or more respective elements of one or more vectors of immediate values per repetition.

The embodiment of the invention provides a data processing method and device for a processor, the processor, electronic equipment and a storage medium. The processor comprises at least one computing core. The data processing method comprises the steps that a search space of a target parameter is obtained, and the search space comprises a first parameter to an nth parameter; a calculation time model of the processor is obtained, and the calculation time model is a function of the target parameter and the number of calculation cores of the processor; traversing the target parameter in the search space, and calculating the calculation time corresponding to the selected target parameter based on a calculation time model; in response to the minimum calculation time when the target parameter is the kth parameter, determining the target parameter as the kth parameter; the calculation scale of each of the at least one calculation core is configured using the kth parameter. The data processing method does not need to be operated on real hardware, the performance of a processor is fully utilized, and the calculation efficiency is greatly improved.

The invention relates to the technical field of interrupt control, and discloses a simplified interrupt control method and device, equipment and a medium. The method comprises the following steps: judging whether an interrupt vector is enabled or not, wherein the interrupt vector comprises a plurality of ITRs; under the condition that the interrupt vector is successfully enabled, the priority of the interrupt event is obtained, the timing requirement of a first ITR is determined based on the priority, the first ITR is the ITR associated with the interrupt event, and the timing requirement is used for adjusting the bit width of the first ITR; adjusting a timer based on the timing demand of each ITR in the interrupt vector; and after timing of the timer is finished, sending the interrupt vector to the host so as to trigger the interrupt vector. According to the invention, the requirement of the interrupt vector for hardware resources can be reduced.

The invention provides a vector processor, a high-performance processor and electronic equipment. The vector processor comprises a vector program control unit, a plurality of functional units, a matrix register file and a scalar register, wherein the vector program control unit is used for fetching instructions and transmitting the instructions; the vector program control unit interacts with the scalar register; the function unit is used for performing function processing according to the instruction; the matrix register file is used for returning data after receiving the read-write request; rearranging the data and then returning the data; performing read-write interaction with the functional unit; and configuring a configuration register of the vector program control unit through data in the matrix register file. The vector processor provided by the invention can efficiently process the vector data.

A discrete three-dimensional (3-D) processor comprises stacked first and second dice. The first die comprises three-dimensional memory (3D-M) arrays, whereas the second die comprises at least a portion of a logic / processing circuit and an off-die peripheral-circuit component of the 3D-M array(s). The preferred 3-D processor can be used to compute non-arithmetic function / model. In other applications, the preferred 3-D processor may also be a 3-D configurable computing array, a 3-D pattern processor, or a 3-D neuro-processor.

A neural network processing unit (NPU) includes a plurality of processing elements for performing the ANN model computations using weight parameters and input activation data; an NPU internal memory operatively coupled to the plurality of processing elements for storing at least one of the weight parameters or the activation data; and a dedicated external memory interface configured for a direct data pathway to an external main memory system storing ANN model data, the direct data pathway facilitating transfer of a portion of the ANN model data, wherein the NPU is configured to receive the ANN model data via the dedicated external memory interface for processing.

A discrete three-dimensional (3-D) processor comprises vertically stacked and communicatively coupled first and second dice. The first die comprises memory arrays, while the second die comprises non-memory circuits and off-die peripheral-circuit components of the memory arrays. The total-number difference of the BEOL layers between the memory arrays and the off-die peripheral-circuit components is substantially larger than the total-number difference of the BEOL layers between the non-memory circuits and the off-die peripheral-circuit components.

The invention provides an inference system and method of a large language model based on multi-chip parallel computing, and relates to the technical field of artificial intelligence. The system comprises a pre-calculation module used for processing input instruction information to generate to-be-reasoned data, and the to-be-reasoned data is in a matrix form; the expert parallel module is used for sending the to-be-reasoned data to accelerator chips in the expert parallel module and determining sub-reasoning data processed by the activation expert units corresponding to the accelerator chips respectively, so that the activation expert units carry out calculation based on the corresponding sub-reasoning data and complete parallel calculation result data is determined. The input data is broadcasted to all the accelerator chips, each accelerator chip selects the corresponding input data for calculation according to the set activation expert unit, the same complete calculation result is obtained through global protocol operation among all the accelerator chips, and the overall operation performance and efficiency are improved.

SYSTEMS AND METHODS IN THE FIELD OF SELF-SUPERVISED DETECTION OF FACIAL BOUNDARIES. Systems and methods for self-supervised learning (SSL) in facial detection networks are proposed. In one embodiment, a facial detection network comprises encoder components configured to encode facial features, the encoder components including trained components of a masked image modeling (MIM) network configured to process non-overlapping patches determined from the input image, the MIM network trained with an SSL objective; and decoder components configured by training to determine local matches between features to determine estimates for facial landmarks. In one embodiment, the MIM network is an MAE network.In one embodiment, the decoder components are derived from those of a second trained network comprising the encoder components as trained but fixed, wherein the decoder components of the second network are trained using locality constraint repulsion loss (LCR). Methods are proposed for SSL training of the encoder and decoder components. Figure for abstract: none.

A method of accelerating training of a low-power, high-performance artificial neural network (ANN) includes (a) performing fine-grained pruning and coarse-grained pruning to generate sparsity in weights by a pruning unit in a convolution core of a cluster in a lower-power, high-performance ANN trainer; (b) selecting and performing dual zero skipping according to input sparsity, output sparsity, and the sparsity of weights by the convolution core, and (c) restricting access to a weight memory during training by allowing a deep neural network (DNN) computation core and a weight pruning core to share weights retrieved from a memory by the convolution core.

The embodiment of the invention provides a tensor data processing method and device and a storage medium, and aims to ensure that a to-be-processed operator can support a target public data type and avoid performance loss caused by introduction of unnecessary data type conversion so as to improve the operation efficiency of the operator.

A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.

The invention discloses a fair arbitration complementary steering routing method based on a three-dimensional network-on-chip, which belongs to the field of network-on-chip communication, and is characterized in that an output port of a first node is determined according to an arbitration mechanism, the first node comprises a plurality of output ports, and each output port corresponds to a second node; according to a steering model of a routing layer where the first node is located, whether the steering direction corresponding to the output port is one steering direction limited by the steering model or not is judged; and if not, the to-be-sent data is sent to one of the routing nodes on the adjacent routing layer, and one of the routing nodes on the adjacent routing layer forms a second node after receiving the to-be-sent data. The congestion avoidance performance of the adaptive routing method and the uniform distribution of communication flow in the network can be further improved, and finally the purpose of improving the communication performance and reliability of the three-dimensional network-on-chip is achieved.