33results about How to "Improve data access" patented technology

A system and method for processing machine learning techniques (such as neural networks) and other non-graphics applications using a graphics processing unit (GPU) to accelerate and optimize the processing. The system and method transfers an architecture that can be used for a wide variety of machine learning techniques from the CPU to the GPU. The transfer of processing to the GPU is accomplished using several novel techniques that overcome the limitations and work well within the framework of the GPU architecture. With these limitations overcome, machine learning techniques are particularly well suited for processing on the GPU because the GPU is typically much more powerful than the typical CPU. Moreover, similar to graphics processing, processing of machine learning techniques involves problems with solving non-trivial solutions and large amounts of data.

Methods and systems for use in connection with an asymmetrical digital subscriber line (ADSL) system being available to provide voice service and data service to the customer's premises. One service of the voice service or the data service is in use at the customer's premises, and the exemplary methods and systems detect a request for provision of the other service. In response to the detection, impact information may be provided on performance of the one service in light of concurrent use of the other service. A list of modes of operation of the other service is provided. The subscriber may consider the impact information and the list of modes and respond with a selected mode of operation of the other service. The selected mode is detected and the other service is operated pursuant to the selected mode to the customer's premises.

A shock-absorbing mobile hard disk mounting arrangement in which shock-absorbing spring members are provided to support the hard disk on the circuit board inside the mobile hard disk box, preventing damage to the hard disk when the mobile hard disk box is vibrated accidentally.

A memory architecture includes K first control lines, M groups of second control lines and a memory cell array. K and M are positive integers. Each group of second control lines includes at least one second control line. The memory cell array includes M memory banks. Each memory bank is coupled to the K first control lines. The M memory banks are selected according to M bank select signals respectively so as to receive a shared set of first control signals through the K first control lines. The M memory banks are coupled to the M groups of second control lines respectively, and receive independent M sets of second control signals through the M groups of second control lines respectively. Each memory bank performs one of a column select operation and a sense amplification operation according to the set of first control signals and a set of second control signals.

The invention provides a method for improving the performance of a stacked DRAM cache, and proposes a line buffer manager to help shorten the access delay of the stacked DRAM cache and accelerate data access, thereby improving performance. The present invention includes the following steps: S1, propose a line buffer manager, which includes a line state table, the line state table includes a plurality of line state entries, and each line state entry includes an activation bit, a tag value sequence, a tag value filling bit and a waiting request In order to describe the state of a memory row data; S2, the row buffer manager is connected with the data access request queue, and the row buffer manager updates the information of the row status table according to the data access request arriving in the data access request queue; S3, The row buffer manager is connected to the cache controller, and the row buffer manager receives the command from the cache controller and updates the information of the row status table; S4, the row buffer sends the stacked DRAM buffer through the cache controller to the stacked DRAM cache according to the information of the row status table. control commands.

Methods and systems for use in connection with an asymmetrical digital subscriber line (ADSL) system being available to provide voice service and data service to the customer's premises. One service of the voice service or the data service is in use at the customer's premises, and the exemplary methods and systems detect a request for provision of the other service. In response to the detection, impact information may be provided on performance of the one service in light of concurrent use of the other service. A list of modes of operation of the other service is provided. The subscriber may consider the impact information and the list of modes and respond with a selected mode of operation of the other service. The selected mode is detected and the other service is operated pursuant to the selected mode to the customer's premises.

A memory architecture includes K first wordlines, M groups of second wordlines, a memory cell array and M switch circuits. K and M are positive integers. Each group of second wordlines includes a plurality of second wordlines. The memory cell array includes M memory banks. The M memory banks are coupled to the M groups of second wordlines respectively, and receive independent M sets of second wordline signals through the M groups of second wordlines respectively. M switch circuits are disposed in correspondence with the M memory banks respectively. Each switch circuit selectively couples the K first wordlines to a corresponding memory bank so that the corresponding memory bank receives a shared set of first wordline signals through the K first wordline. Each memory bank performs a data access operation according to the received set of first wordline signals and a corresponding set of second wordline signals.

Embodiments of the present invention provide a data storage system, a data storage method, and a PCM bridge. The system includes: a processor, a memory controller, a phase-change memory PCM bridge, and a phase-change memory PCM. The processor is connected to the PCM bridge through the memory controller. , the PCM bridge is connected to the PCM, and non-volatile small data is stored in the PCM, and the PCM bridge is used to receive the first operation signal for reading or writing small data from the CPU through the memory controller, and convert the first operation signal A second operation signal capable of reading or writing to the PCM is formed to read small data in the PCM or write small data in the PCM through the second operation signal. The data storage system, the data storage method and the PCM bridge provided by the embodiments of the present invention can be read or written bit by bit by using the PCM, which improves the operation efficiency, increases the life of the system, and accelerates the ability of data access.