A performance improvement method for stacking dram cache

Abstract

The invention provides a method for improving the performance of a stacked DRAM cache, and proposes a line buffer manager to help shorten the access delay of the stacked DRAM cache and accelerate data access, thereby improving performance. The present invention includes the following steps: S1, propose a line buffer manager, which includes a line state table, the line state table includes a plurality of line state entries, and each line state entry includes an activation bit, a tag value sequence, a tag value filling bit and a waiting request In order to describe the state of a memory row data; S2, the row buffer manager is connected with the data access request queue, and the row buffer manager updates the information of the row status table according to the data access request arriving in the data access request queue; S3, The row buffer manager is connected to the cache controller, and the row buffer manager receives the command from the cache controller and updates the information of the row status table; S4, the row buffer sends the stacked DRAM buffer through the cache controller to the stacked DRAM cache according to the information of the row status table. control commands.

Description

technical field [0001] The invention relates to a method for improving the performance of a stacked DRAM cache. Background technique [0002] The memory wall problem in the context of big data processing exacerbates the problem of data transfer between on-chip processors and off-chip memory. Integrated on-chip stacked DRAM (3D DRAM) memory is an effective way to meet this challenge, and its advantages lie in high bandwidth and low power consumption. Therefore, on-chip stacked DRAM is used as the last level of on-chip cache to temporarily store data from off-chip memory, reduce the amount of data transmission on and off the chip, significantly reduce data transmission delay, and effectively improve system performance. On the other hand, the organizational structure and interface design of on-chip stacked DRAM are not friendly to cache access, which hinders further improvement of system performance and affects its performance as the last level of cache. [0003] The on-chip ...

AI Technical Summary

Problems solved by technology

If the target memory line is not in the line buffer, a high-energy, high-latency line miss is caused; in addition, even if the target memory line is in the line buffer, a cache miss may occur, resulting in additional delay and energy consumption

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