154results about How to "Improve parallelism" patented technology

The invention discloses a training reasoning method of a decision model, a product, electronic equipment and a medium, and relates to the technical field of artificial intelligence. In the method, when the training reasoning process of the decision model is divided into a plurality of calculation tasks to be distributed to different cluster nodes, the load pressure on the nodes is reduced; and the plurality of data subsets obtained by splitting the input data corresponding to the calculation task are allocated to different calculation nodes, so that the load pressure on the calculation nodes is reduced, the utilization rate of node resources is improved, parallel processing of the data subsets corresponding to the input data is realized, and the efficiency of training reasoning is improved. When the training reasoning process of the decision model is divided into one calculation task, the plurality of data subsets obtained by splitting the input data corresponding to the calculation task are distributed to different calculation nodes, so that the load balance on the calculation nodes is ensured, the load is reasonably distributed to the nodes in the cluster, and the calculation efficiency is improved. And the utilization rate of node resources is improved.

The invention relates to a multi-back-end separated memory system and an optimization control method thereof, the multi-back-end separated memory system comprises an intelligent far memory multi-back-end management control module and a multi-back-end far memory switch, the intelligent far memory multi-back-end management control module analyzes and processes calling of page errors and page switching triggering, and the multi-back-end far memory switch is used for switching the multi-back-end far memory switch. Switching instruction information and parameter regulation and control instruction information are obtained; and the multi-rear-end remote memory exchanger receives and executes the switching instruction information and the parameter regulation and control instruction information, runs applications on the separated memory architecture and the multi-rear-end remote memory software system, and releases resources after running is finished. By supporting a memory exchange strategy and a system architecture of a plurality of heterogeneous far-end separated memory rear ends, parallel access of a plurality of paths of far memories is realized to improve data throughput, application characteristics are analyzed, and intelligent rear end switching and data exchange parameter adjustment are realized; parallel access of a plurality of memory exchange back-end devices, fine-grained parameter configuration of a remote memory data access path, real-time switching of a plurality of memory exchange back-ends and an intelligent control and management method of the remote memory access path can be realized.

The embodiment of the invention discloses a static random access memory in-memory computing system and method, and the system comprises a feature memory which is used for storing an input signal of a neural network model; the SRAM storage array is used for storing each weight of the neural network model and performing logical operation on an input signal and each weight to obtain a plurality of logical operation results, each weight is divided into a plurality of binary blocks after CSD coding, complementary mode blocks are reserved after processing of eliminating all-zero mode blocks, and each binary block is divided into a plurality of binary blocks; after information is extracted from each complementary mode block, an index, a symbol and a value are obtained, and each weight is stored in a complementary mode block mode; the metadata storage is used for storing indexes and symbols; the adder tree is used for performing decoding and additive operation on the plurality of logical operation results according to the indexes and the symbols; the shift accumulation unit is used for performing shift accumulation on the addition result; and the post-processing unit is used for post-processing the shift accumulation result to obtain an output signal of the neural network model.

The invention discloses an FPGA (Field Programmable Gate Array) implementation method of a DVB (Digital Video Broadcasting) high-speed demodulator. A digital signal enters a parallel DDC (Direct Digital Control) module and is re-adapted to multiple symbol rates; the parallel AGC module adjusts the power of the digital signal to a fixed power value; the method comprises the following steps: passing through Oamp; m algorithm: completing symbol synchronization; related peaks are extracted, and frame synchronization is completed; correcting the frequency to enable the frequency to reach participation frequency deviation; performing frequency compensation on the digital signal after loop filtering; after error information is calculated and filtered, the digital signal is compensated; and restoring the original information of the digital signal. According to the invention, by adopting the parallel processing module, the real-time performance and the parallelism degree of digital signal processing can be greatly improved, and the performance of the whole demodulator is enhanced. Each module is designed to be adaptive to the change of a digital signal, for example, the AGC module can dynamically adjust the power of the digital signal to ensure that the output digital signal is always kept at a fixed power level so as to adapt to different receiving conditions.

The invention relates to the technical field of simulation regression systems, and provides a parallel simulation regression method and system based on cluster servers. The method comprises the following steps: classifying simulation tasks according to task types, and determining a dependency relationship among a plurality of simulation tasks; generating a parallel simulation task list through a cluster server management tool according to the dependency relationship among the plurality of simulation tasks; and delivering the parallel simulation task list to a cluster server, and running simulation tasks by the cluster server to generate a simulation result. The parallel simulation regression system is conveniently constructed by utilizing the scheduling function of the cluster server, the dependency relationship of various types of tasks can be processed, the degree of parallelism of the simulation regression system is increased to the maximum extent, and the method has universality and can be widely applied to different scenes.

The invention relates to the technical field of intelligent Internet of Vehicles, in particular to a task unloading method in a vehicle-mounted edge computing environment based on deep reinforcement learning, which comprises the following steps: acquiring a task vehicle to generate a to-be-executed task, uploading the task to an RSU, generating a scheduling decision according to the current state of the task and available resources, and sending the scheduling decision to the RSU. The task is allocated to a service vehicle or locally executed; performing priority division on the tasks by utilizing an analytic hierarchy process, and obtaining the current state of each to-be-executed task; obtaining service vehicle numbers and task vehicle numbers of the tasks based on task states and priority level utilization model scheduling, and calculating unloading and scheduling strategies; obtaining available computing resources of the current service vehicle; and training the sequence to the sequence model by using an Actor-Cr-it ic algorithm to obtain an optimal task part unloading and scheduling strategy. The computing resources of the service vehicle and the edge server can be fully utilized, the execution time delay of all tasks in the whole time period is smaller, and the task execution success rate is higher.

The invention relates to multi-process combined injection molding equipment and an injection molding method.The injection molding equipment comprises a mold closing assembly, a range finder, a first injection assembly, a gas injection assembly, a second injection assembly, a manipulator and an infrared heater, the mold closing assembly comprises a fixed mold plate and a movable mold plate which are oppositely arranged, and a mold is arranged between the fixed mold plate and the movable mold plate; the range finder is arranged on the mold; the first injection assembly is used for injecting a foaming material of a product main body into the mold, and the first injection assembly communicates with the gas injection assembly; the second injection assembly is used for injecting a second component material into the mold; the manipulator is used for clamping the thermoplastic organic sheet, and the infrared heater is used for heating the thermoplastic organic sheet. Compared with the prior art, integrated lightweight product machining is completed on the same equipment, multiple parts are directly connected when formed in the mold, product transfer and recombination caused by multiple independent procedures are avoided, and the production efficiency and the production quality are effectively improved.

The embodiment of the invention provides a data processing method and a data processing chip, and the method comprises the steps: determining a first operation object corresponding to a first operation unit under the condition that the state of the first operation unit is an idle state, the first operation unit is any one of at least two operation units, and the first operation object corresponds to the first operation unit; the first operation object comprises one of a first node in the first Merkel tree and a target sequence chain of a second node in the first Merkel tree; and operating the first operation object by using the first operation unit to obtain an operation result. Thus, when any operation unit is in the idle state, the nodes or the sequence chains in the Merkle tree serve as the operation objects of the operation unit, the storage space can be reduced, high-parallel operation under the small storage space is achieved, all the operation units are fully utilized, and the operation efficiency is improved. And the parallel effect is improved while the utilization rate of the operation unit is improved, so that the operation efficiency is improved.

The invention discloses a heterogeneous computing architecture testing method of an ISP module, and belongs to the technical field of heterogeneous computing. According to the technical scheme, a high-level synthesis tool is used for generating and verifying an IP to be tested; a target algorithm IP application system is constructed by using a microprocessor IP hardcore and an AXI bus connector of a heterogeneous computing platform, a target algorithm IP core is operated by using software to carry out an application test, and actually measured data is stored in a nonvolatile storage medium; transplanting an operation system and an OpenCV library to the heterogeneous computing platform for the development board, and storing a target algorithm software operation result to a data file after a test program is operated; and evaluating the function correctness and the performance index of the target algorithm IP by using the actually measured data and the software operation result. The method has the advantages that effective testing and optimization of the heterogeneous computing architecture of the ISP module are achieved through the software and hardware co-simulation and IP core verification technology, middle-level optimization, a comprehensive testing framework and other methods, and powerful support is provided for technology development, application and popularization in related fields.

The invention discloses a vector processing device, a chip, electronic equipment and a method, and belongs to the technical field of chips. The vector processing device comprises an instruction buffer, a vector decoding unit, a register unit and a plurality of pipelines, the instruction buffer is used for storing instruction packets to be executed, and each instruction packet comprises a plurality of vector instructions which can be executed in parallel; the vector decoding unit is used for decoding each vector instruction included in the instruction packet to obtain a control signal corresponding to each vector instruction, and broadcasting the control signal corresponding to each vector instruction to the register unit and the plurality of assembly lines in a clock period; a register unit to store data related to the vector instruction; and the assembly line is used for processing data related to the vector instruction according to the control signal corresponding to the vector instruction to obtain a processing result corresponding to the vector instruction. By processing a plurality of vector instructions in one clock period, the processing efficiency of the vector instructions can be remarkably improved.

The invention discloses a multi-node metadata management method for a persistent memory file system in an NUMA system, and relates to the technical field of novel storage of data centers. File data access is a mixing process of file metadata and file data, for example, in a file creating and deleting process, global information of a file system needs to be accessed so as to update access time, idle data blocks, idle inode and the like of the file system; in the file reading and writing process, a directory structure needs to be traversed, a file metadata inode structure corresponding to a file name is searched, space is distributed, data is copied, file system global information and file metadata inode information are updated, and file reading and writing are completed. In the design of a current NUMA persistent memory file system, the operation of remotely accessing metadata is involved in the file data access process, so that the file read-write performance is reduced. According to the method, a redundant dynamic attribute metadata management mechanism and a centralized directory management mechanism based on the access frequency are adopted, metadata management of the persistent memory file system in the NUMA system is optimized, and the influence of cross-node metadata access on file data access performance is reduced.

The invention discloses an optimization method, system and device for a ReLee filtering algorithm based on a CUDA platform, and relates to the technical field of signal processing.The optimization method comprises the following steps that a first memory and a second memory are applied in a global memory of a GPU, image data to be filtered in a memory of a CPU is copied to the first memory, and the second memory is copied to the second memory; according to the to-be-filtered image data layout block stored in the first memory, after a CUDA kernel function is started, all threads in the block are allowed to execute the kernel function so as to obtain a filtering result, the filtering result is stored in the second memory, and the filtering result is copied to the memory of the CPU. Through the steps, the optimization method is favorable for improving the calculation efficiency.

The embodiment of the present application discloses a multi-core processing system and its task scheduling method, chip, and storage medium. The multi-core processing system includes multiple control cores and multiple processing cores. The multiple control cores are respectively connected to the multiple processing cores. The first control core reads a first instruction and executes the first instruction when it is determined that the first instruction is a control instruction executed by the control core; when the first control core determines that the first instruction is a data processing instruction executed by the processing core, it sends the first instruction to the first processing core for execution. In this way, a one-to-many topological structure is configured between the control core and the processing core according to the processing requirements, so as to improve the parallelism of data processing instruction processing, thereby improving data processing efficiency and reducing chip area.

The present invention relates to the technical field of vacuum electronic devices, and provides an electron gun frame, comprising an insulating porcelain seat, a first anode seat and a second anode seat arranged on the insulating porcelain seat, and a positioning member for fixing the first anode seat and the second anode seat, wherein the insulating porcelain seat comprises an insulating porcelain ring, and at least two positioning block groups evenly distributed along the circumference of the top surface of the insulating porcelain ring, each positioning block group comprises a first positioning block, a second positioning block and a third positioning block, the first positioning block, the second positioning block and the third positioning block are arranged in sequence and equidistantly, the setting heights of the first positioning block, the second positioning block and the third positioning block are successively larger, and each of the first positioning block, the second positioning block and the third positioning block is fixedly connected to the first anode seat, the second anode seat and the positioning member respectively by a clamping method. The present invention solves the technical problem that the miniaturized traveling wave tube in the prior art cannot meet the requirements in terms of weight reduction, processing, assembly and precision.

The invention provides a polarization code soft input soft output decoding method, a decoding device and communication equipment. The decoding method comprises the following steps: (S1) aiming at all special nodes forming a polarization code, fast serial cancellation list decoding under dynamic frozen bit constraint is executed, and the types of the special nodes comprise rate zero, rate one, repetition and single parity check; (S2) after each special node is decoded, calculating the approximation of the posterior probability sum of legal code words which are not accessed under the node; and (S3) utilizing the approximate estimation codebook probability obtained in the step (S2) and calculating bit-level soft information of the output polarization code. Compared with an SO-SCL decoding algorithm, the low-delay soft input and soft output decoding method for the polarization codes, provided by the invention, has the advantages that the degree of parallelism is improved and the decoding delay is remarkably reduced on the premise that the soft output precision is not lost by realizing rapid soft output decoding based on the Rate0, the Rate1, the REP and the SPC nodes.

The invention provides an underground garage electronic map drawing method and device based on the Internet of Vehicles, and relates to the technical field of the Internet of Vehicles. The method comprises the following steps: detecting the position of a vehicle in response to receiving an underground garage drawing task sent by map maintenance equipment; after it is detected that the vehicle enters the underground garage, first certification information is sent to map maintenance equipment, so that after the map maintenance equipment verifies the first certification information, a data collection instruction is sent to the vehicle-mounted terminal; in response to the received data acquisition instruction, collecting and storing monitoring data obtained by monitoring the vehicle by a steering sensor, a speed sensor and a gyroscope; and after it is detected that the vehicle leaves the underground garage, second proof information and the monitoring data are sent to the map maintenance equipment, so that after the map maintenance equipment verifies the second proof information, an electronic map of the underground garage is drawn according to the monitoring data. In this way, the electronic map of the underground garage can be accurately drawn.

The invention relates to a method, a device and a system for setting transaction operation dependence based on a log sequence. The method mainly comprises the steps that after a target end data synchronization service receives a DML operation of a source end, an MD5 value calculated by the source end in the operation is extracted to serve as a KEY, and then a transaction ID in the operation is extracted to serve as a TRXID; constructing a detection record X by using the currently operated KEY, merging the detection record X into the hash table R, performing conflict detection judgment in the merging process, and returning a TRXID value corresponding to a conflicting KEY if the conflicting KEY exists; otherwise, 0 is returned to serve as the corresponding TRXID, and no conflict exists; and setting the TRXID obtained by conflict detection judgment as a conflict TRXID, writing the initial LSN of the first memory chip in the memory linked list corresponding to the current hash table R into the current operation, and setting the initial LSN as a conflict LSN. According to the method, the dependency relationship between transaction operations can be determined, which transactions need to wait can be determined during synchronous operation, and the synchronization parallelism can be improved to the maximum extent.

The invention provides a kernel driving method and device based on multi-kernel collaboration and electronic equipment. The method comprises the following steps: receiving a calling task of a user mode by a service driver; the service driver sends the calling task to a task queue of an IP driver of a corresponding type according to the IP type corresponding to the calling task; selecting a calling task from the task queue as a target task by the IP driver; if the IP corresponding to the target task is of a multi-core structure, the IP driver sends the target task to a corresponding multi-core cooperation unit; selecting, by the multi-core cooperation unit, a target core from the plurality of cores of the IP according to a priority policy; the multi-core cooperation unit schedules the target task to the target core; and executing the target task by the target core. In this way, the task processing capacity of the system is greatly improved, and the overall efficiency is improved.

The invention discloses a thread data reading and writing-back method and device, equipment and a storage medium, and relates to the field of data read-write, and the method comprises the following steps: marking a plurality of operands based on operand types of the operands in a current branch thread to obtain a plurality of corresponding marked operands; if a reading request is received, determining whether an operand corresponding to the request is marked as a reusable operand or not; if yes, reading cache data corresponding to the operand from a preset cache; if not, reading target data corresponding to the operand, and storing the target data to a preset cache; if the write-back request is received, determining whether an operand corresponding to the request is marked as a reusable operand or not; if yes, the requests are added to a local cache queue, and merging and data writing-back are carried out based on the requests in the queue when the queue is full; and if not, writing the data corresponding to the operand into the target register. Therefore, the read-write efficiency of the data can be improved.

The invention belongs to the field of data processing and finance, and relates to a metadata-based writing method, which comprises the following steps: analyzing a data writing request sent by a client to obtain file metadata, selecting a target data node from a node list according to the file metadata, and determining a current data node by the client according to node identification information, a current data node writes a data packet sent by a client into a preset storage position, generates a corresponding response packet, puts the response packet into a preset to-be-processed queue, calls a callback function to obtain the length of the data packet and slice metadata information, and synchronizes the slice metadata information to other nodes. And taking out the response packet from the to-be-processed queue according to the data packet length, putting into a preset response queue and returning to the client. The invention further provides a metadata-based writing device, computer equipment and a storage medium. In addition, the invention also relates to a block chain technology, and the data packet can be stored in a block chain. The metadata is transmitted at the data node, and the efficiency and timeliness of data writing are improved.

The invention discloses a GPU (Graphics Processing Unit) parallel acceleration method for subdivision volume parameter evaluation, which comprises the following steps of: S1, storing and traversing a volume grid through a data structure containing a half side and a half surface, and judging the type of each volume unit; s2, performing CC body subdivision under any topology once, and isolating irregular vertexes if a plurality of irregular edges in a body unit must converge at an irregular point; s3, aiming at different topologies, numbering control grid vertexes by using a data structure containing a half surface and a half side, obtaining a subdivision matrix according to a numbering sequence and a CC subdivision rule, and pre-calculating a subdivision matrix feature structure; and S4, performing parallel parameter evaluation on different types of volume grid units. According to the method, the optimized parallel algorithm is designed, the multi-core architecture and the floating-point operation capability of the GPU are fully utilized, and the parameter evaluation speed of the complex body subdivision model is effectively improved.

The application discloses a cloud application picture display method and device, a server, a terminal and a storage medium, and relates to the field of cloud applications. The method comprises the following steps: running a cloud application program, and acquiring a cloud application picture in a cloud application program running process; based on a picture segmentation strategy corresponding to the cloud application program, the cloud application picture is segmented into at least two sub-pictures; the at least two sub-pictures are parallel encoded to obtain at least two sub-encoding data blocks corresponding to the cloud application picture; the at least two sub-encoding data blocks are sent to a proxy server in parallel, so that the proxy server sends the at least two sub-encoding data blocks to a terminal, the at least two sub-encoding data blocks are decoded by the terminal, and the at least two sub-pictures obtained by decoding are spliced to obtain the cloud application picture. In the case of fully utilizing hardware resources, the parallel degree of the encoding and transmission process is improved by segmenting the cloud application picture, and the effect of reducing the display delay of the cloud application picture on the terminal side is achieved.

The invention relates to the technical field of glycosylation, and provides a DeepGP glycopeptide enrichment column and a method for efficiently enriching N glycopeptide and O glycopeptide. The preparation method of the DeepGP glycopeptide enrichment column comprises the following steps: uniformly mixing microcrystalline cellulose, cation exchange filler and anion exchange filler, and then packing the mixed filler into a column and compacting to obtain the DeepGP glycopeptide enrichment column. Compared with the enrichment effects of four enrichment columns on HET cell line glycopeptide samples, the DeepGP glycopeptide enrichment column prepared by the invention has the highest parallelism and enrichment efficiency in three times of parallel enrichment. Besides, 245 N glycopeptides can be identified in an IgG standard substance by utilizing a DeepGP column, and 4286 N glycopeptides and 749 O glycopeptides can be simultaneously identified in mouse plasma, so that the method is high in detection precision, high in sensitivity, good in repeatability and very wide in application range.

The invention discloses a tea bud detection method and system based on a lightweight FPGA (Field Programmable Gate Array), and the method comprises the steps: carrying out the lightweight processing of a network model through eight-time channel pruning, and carrying out the weight fixed-point quantification of weight distribution, thereby not only compressing a model redundancy filter according to the model parameter quantity and calculation quantity, but also improving the detection precision of a tea bud. And meanwhile, optimization can be carried out according to the calculation characteristics of the FPGA single-engine accelerator. The pruning multiple is set to be eight to regularize the pruned network structure, calculation of a redundant filter is reduced, hardware deployment of a target detection network on a resource-limited FPGA platform is completed, and the reasoning performance of a network model is improved; besides, the PE parallel computing matrix adopts a convolution computing strategy of cyclic partitioning, and all output feature sub-blocks are obtained by performing cyclic traversal in input and output size dimensions, so that the problem that all input feature maps and weight parameters cannot be completely stored by limited FPGA storage resources is solved.

This application provides a directed acyclic graph (DAG) scheduling method and system for multiple toolchains in intelligent agents, solving the technical problems of existing scheduling methods that rely on manual orchestration, have high topological redundancy, and low execution efficiency. First, it receives multi-tool collaboration task instructions and parses them to obtain a set of tool identifiers to be orchestrated and corresponding tool capability declaration texts. Then, it extracts historical call topology patterns with time-stamped edges; next, it retrieves candidate directed edges that meet capability connection conditions and combines them to generate an initial DAG skeleton; then, it eliminates redundant edges to obtain a simplified DAG structure; finally, it generates a tool call execution sequence containing time-series tool identifiers and a predecessor dependency list. This invention can achieve automated and efficient scheduling of multiple toolchains, adapt to dynamic task requirements, and reduce the overall task execution time.

This invention discloses a method, apparatus, medium, and product for calculating bonding interactions in molecules. The method includes: allocating bonding tasks using a three-dimensional interconnected computing architecture, and constructing a bonding atom set and a bonding task index table matching the allocated bonding tasks within each computing module. This ensures that identical atoms do not need to be repeatedly stored when the computing module executes all bonding tasks, reducing the storage overhead of atomic information; dynamically acquiring and filling atomic information from the local machine or other computing modules into the corresponding storage locations of the bonding atom set, extracting atomic information according to the index table, calculating bonding components in parallel, and accumulating the bonding components of identical atoms to obtain the resultant bonding force; and updating the resultant bonding force and atomic information through inter-module interaction, and re-storing the atomic information according to the updated spatial arrangement. This reduces the amount of data transmission between modules while ensuring the accuracy of molecular bonding interaction simulation, thereby improving the stability and efficiency of the overall molecular dynamics simulation.

The utility model discloses a novel encoder, which comprises an encoder moving disc and an encoder static disc provided with a PCB (printed circuit board), the encoder static disc is provided with a reading head electrically connected with the PCB, the encoder static disc is provided with a central through hole A, and the aperture of the central through hole A is larger than the diameter of a motor shaft. The encoder static disc is installed at the tail end of the motor shell in the using state, the encoder movable disc is installed at the tail end of the motor shaft in the using state, a gap is reserved between the encoder static disc and the encoder movable disc, and the reading head is used for detecting rotation information of the encoder movable disc. According to the utility model, the encoder static disc is directly installed at the tail part of the motor shell, no extra support for installing the encoder static disc is needed, and the encoder static disc is located between the encoder dynamic disc and the motor, thereby reducing the occupied space of the encoder, reducing the length of the motor on the whole, reducing the occupied space when the servo motor is used, and improving the service life of the servo motor. And meanwhile, an encoder static disc bracket is not arranged, so that the cost of the encoder is reduced.

The utility model relates to the technical field of injection molds, in particular to an injection mold with a quick demolding function, which comprises an upper mold seat and a lower mold seat, an air cylinder is fixedly mounted on the surface of the upper mold seat, a support is fixedly mounted on the bottom surface of the upper mold seat, an upper mold block is fixedly mounted on the bottom surface of the support, and a lower mold block is fixedly mounted on the lower surface of the upper mold seat. An upper die head is fixedly mounted in the upper die block, and a movable plate is slidably connected into the support. According to the utility model, the ejector rod slides in the sliding chute of the upper module, so that the ejector rod realizes vertical and accurate guiding, abrasion or blockage is obviously reduced, the service life of the mold is prolonged, and the product quality is improved. And the guide rods of the movable plate slide in the guide holes, so that the stability and the parallelism are enhanced, and the alignment precision of the mold under pressure or thermal expansion is ensured. Power of the air cylinder directly acts on the moving plate, so that the ejector rod directly applies force to a forming material, demolding is accelerated, the forming period is shortened, the driving efficiency and the response speed are improved, and the production process is effectively accelerated.

The application discloses a kind of based on multi-value logic parallel decision Hash algorithm fast cracking device and method, belong to information security and cryptanalysis technical field.This device adopts Tianpi framework, core hardware includes 6400 four-value logic operation unit, 2300 MSD carry-free adder and 4.3 billion parallel logic rule base;Through hash length automatic identification, rule dynamic scheduling, segmented operation, pipeline cascade and parallel candidate generation etc., realize 50 bits ~ 50000 bits and greater bit number ultra-wide range hash fast reverse cracking, can give consideration to 50 / 70 / 100 bit short bit width hash economic operation, and support post-quantum hash algorithm extension.This application is strong, cost controllable, cracking speed is fast and can room temperature stable operation, is suitable for password audit, security detection, data traceability and anti-quantum attack etc.

The utility model discloses a chlorine liquefier tube head welding structure which comprises a tube plate and a plurality of heat exchange tubes, and the heat exchange tubes are arranged on the tube plate in a penetrating mode. The length of the part, extending out of the tube plate, of the tube head of the heat exchange tube is 0-1mm; the tube plate is provided with a groove used for being connected with a heat exchange tube, and the angle of the groove ranges from 45 degrees to 60 degrees. The heat exchange tube is in interference fit with the hole wall of the tube plate through expanded connection, and the groove is filled with a welding seam to fixedly connect the heat exchange tube with the tube plate. According to the chlorine liquefier pipe head welding structure, the welding quality of the chlorine liquefier pipe head can be improved, the connection reliability is enhanced, and leakage is effectively prevented.