52results about How to "Improve parallelism" patented technology

This application provides a directed acyclic graph (DAG) scheduling method and system for multiple toolchains in intelligent agents, solving the technical problems of existing scheduling methods that rely on manual orchestration, have high topological redundancy, and low execution efficiency. First, it receives multi-tool collaboration task instructions and parses them to obtain a set of tool identifiers to be orchestrated and corresponding tool capability declaration texts. Then, it extracts historical call topology patterns with time-stamped edges; next, it retrieves candidate directed edges that meet capability connection conditions and combines them to generate an initial DAG skeleton; then, it eliminates redundant edges to obtain a simplified DAG structure; finally, it generates a tool call execution sequence containing time-series tool identifiers and a predecessor dependency list. This invention can achieve automated and efficient scheduling of multiple toolchains, adapt to dynamic task requirements, and reduce the overall task execution time.

This invention discloses a method, apparatus, medium, and product for calculating bonding interactions in molecules. The method includes: allocating bonding tasks using a three-dimensional interconnected computing architecture, and constructing a bonding atom set and a bonding task index table matching the allocated bonding tasks within each computing module. This ensures that identical atoms do not need to be repeatedly stored when the computing module executes all bonding tasks, reducing the storage overhead of atomic information; dynamically acquiring and filling atomic information from the local machine or other computing modules into the corresponding storage locations of the bonding atom set, extracting atomic information according to the index table, calculating bonding components in parallel, and accumulating the bonding components of identical atoms to obtain the resultant bonding force; and updating the resultant bonding force and atomic information through inter-module interaction, and re-storing the atomic information according to the updated spatial arrangement. This reduces the amount of data transmission between modules while ensuring the accuracy of molecular bonding interaction simulation, thereby improving the stability and efficiency of the overall molecular dynamics simulation.

The utility model discloses a chlorine liquefier tube head welding structure which comprises a tube plate and a plurality of heat exchange tubes, and the heat exchange tubes are arranged on the tube plate in a penetrating mode. The length of the part, extending out of the tube plate, of the tube head of the heat exchange tube is 0-1mm; the tube plate is provided with a groove used for being connected with a heat exchange tube, and the angle of the groove ranges from 45 degrees to 60 degrees. The heat exchange tube is in interference fit with the hole wall of the tube plate through expanded connection, and the groove is filled with a welding seam to fixedly connect the heat exchange tube with the tube plate. According to the chlorine liquefier pipe head welding structure, the welding quality of the chlorine liquefier pipe head can be improved, the connection reliability is enhanced, and leakage is effectively prevented.

The invention discloses a light plane high-precision rapid calibration method and system for multi-line structured light, and belongs to the technical field of structured light three-dimensional measurement, and the method comprises the steps: obtaining camera parameters in a to-be-calibrated multi-line structured light system; wherein the camera parameters comprise an internal parameter matrix, a distortion coefficient matrix and an external parameter matrix of a camera; selecting a main laser ray; wherein the main laser line is any laser line in a to-be-calibrated multi-line structured light system; based on the camera parameters, a light plane equation of a main laser ray is obtained through fitting solution; and calculating a light plane equation of each laser line except the main laser line in the to-be-calibrated multi-line structured light system based on the light plane equation of the main laser line by utilizing a fixed parallel relationship among the laser lines. According to the scheme, the calibration efficiency can be greatly improved, the light plane parallelism is ensured, personal errors are reduced, and the method is suitable for industrial field rapid deployment.

The application discloses a kind of nano-silica polycarbonate film moisture permeability detection device, it is related to polycarbonate film detection technical field, including water storage tank and adjusting assembly, the top of water storage tank is connected with load disc by one-way valve, and the inside of load disc is placed with lower partition, the top of lower partition is provided with top cover, and the inside of top cover is placed with upper partition, the periphery of load disc is connected with connecting assembly.The application forms multiple independent test chambers by lower partition and upper partition, which makes it possible to place the same sample in multiple different humidity environments simultaneously and efficiently for comparison testing when detecting the moisture permeability of nano-silica polycarbonate film. The humidity environment is accurately generated by the humidifying unit and drying unit, and the mixture ratio of dry and wet gas input into each chamber is flexibly adjusted by the bus adjusting valve, thereby achieving wide-range humidity control.

The application relates to the technical field of communication, in particular to a chaotic image encryption method based on global dynamic selection, which has the technical scheme as follows: S1, generating a chaotic sequence used in the encryption method by using a 2D-LSM chaotic system; S2, expanding an image into a one-dimensional array through raster scanning; S3, dynamically DNA encoding the image to convert the one-dimensional array into a DNA matrix; S4, dynamically permuting the DNA matrix to obtain a permutation image; S5, DNA decoding the permutation image to obtain a DNA decoding matrix; S6, dynamically diffusing and encrypting the DNA decoding matrix to obtain an encrypted image; and S7, repeating steps S2-S6 to repeatedly encrypt the encrypted image as an initial image. The method has the advantages of high flexibility and selectivity.

The invention relates to the technical field of motors, and discloses a motor shaft insulation coating processing method, a fixing tool and a spraying device.The motor shaft insulation coating processing method comprises pretreatment and shielding, dynamic spraying, post-treatment and a second base, a spraying cavity is formed in the second base in the circumferential direction, and the spraying cavity can rotate; and the clamping piece is arranged in the spraying cavity, and the clamping piece fixes and rotates the motor shaft along the axis of the motor shaft. The clamping piece is arranged to fix the motor shaft, the axial parallelism of the motor shaft and the second base is improved, when the spraying cavity rotates and ascends and descends and a spraying opening of the spraying gun ascends and descends, the motor shaft can be still relative to the second base, the position precision of the motor shaft and the second base is guaranteed, and then the distance between the motor shaft and the spraying gun is kept stable; therefore, the thickness uniformity of the insulating coating on the surface is ensured, the insulating effect is ensured, a plurality of motor shafts are sequentially sprayed, and the spraying efficiency is improved.

This disclosure relates to parallel inference methods, apparatuses, devices, and media for multiple LoRA large models, and pertains to the field of deep learning technology. By adding a dedicated process for the LoRA model, it achieves decoupling and separate management from the original large model process at the process level. At the system architecture level, it realizes isolation and parallel computing of the basic large model and multiple LoRA models in terms of computing and storage resources. Compared with traditional methods that deploy the large model and LoRA models on the same device, this disclosure can deploy more LoRA models and improve inference concurrency. Before each iteration of inference, the metadata data is synchronized within the LoRA process group, and the input data is controlled to be broadcast only within the large model process group, avoiding communication and storage redundancy caused by broadcasting input data to the LoRA process and optimizing preprocessing efficiency. By separating the LoRA process and the large model process for parallel operation, efficient separation and collaboration of inference are achieved.

This invention proposes a fast continuous cancellation decoding method for special nodes of polar codes, comprising: determining special nodes in the target decoding tree for continuous cancellation decoding based on the distribution of polar code information bits and frozen bits, wherein the special nodes include a first dual constraint and a second dual constraint; performing a hard decision on the log-likelihood ratio sequence of the special nodes to obtain a first estimated codeword sequence; calculating the check value of the first dual constraint, and flipping the bit estimates in the first estimated codeword sequence based on the check value of the first dual constraint to obtain a second estimated codeword sequence; calculating the check value of the second dual constraint, constructing a set of flipped bit pairs based on the check value of the second dual constraint, selecting the bit pair with the smallest metric in the set, and flipping the bit estimates at the corresponding positions of the bit pairs in the second estimated codeword sequence to obtain the target estimated codeword sequence. This method significantly reduces decoding latency while maintaining performance lossless and is easy to implement on hardware platforms.

The utility model discloses a flight distance measurement module, and belongs to the technical field of camera modules. The flight distance measurement module comprises a transmitting end and a receiving end; the receiving end comprises a lens, a lens bracket, an optical filter, an image sensing chip and a base; the lens is arranged on the base through a lens support, the image sensing chip is arranged on the base, and the lens, the optical filter and the image sensing chip are sequentially arranged in the optical axis direction of the lens; wherein the optical filter is attached to and covers the photosensitive area of the image sensing chip or is connected to the light emitting side of the lens. The receiving end of the flight distance measurement module provided by the utility model is low in height and good in shooting quality.

The invention discloses a distributed deep learning communication scheduling optimization method based on selective gradient compression. The distributed deep learning communication scheduling optimization method comprises the following steps: step 1, constructing a convergence time model; step 2, obtaining a fitted convergence time model; step 3, constructing a gradient tensor priority index; step 4, constructing to obtain a candidate compression tensor set; 5, obtaining a gradient tensor communication operation execution sequence; step 6, calculating a local gradient tensor; and step 7, according to the compression tensor set and the communication operation execution sequence, carrying out compression and communication on the gradient tensor to obtain a global synchronization gradient. According to the method, the gradient compression subset which enables the total training time to be shortest is determined by performing optimal balance between single iteration time consumption and convergence loss caused by compression, and the degree of parallelism of the subset and calculation in a synchronous aggregation stage is improved, so that distributed deep learning training is accelerated.

The invention discloses a batch data processing method and device suitable for a database, equipment and a medium, relates to the technical field of data processing, and is applied to a processor. Monitoring whether a target instruction meeting a preset stride condition exists in a data processing instruction stream corresponding to the preset database in the target assembly line or not, if yes, entering an instruction pre-execution mode, vectorizing the target instruction and a subsequent instruction having a dependency relationship with a register of the target instruction, and outputting the vectorized instruction; performing instruction pre-execution based on the vectorized instruction and a first execution unit, and storing an instruction pre-execution result to a first physical register file and a result cache region; and when the data processing instruction stream in the target assembly line reaches the input end of the second execution unit, matching the instruction pre-execution result in the result cache region, and completing batch data processing operation based on an information matching result. According to the invention, the efficiency and accuracy of batch data processing are improved.

This invention discloses a spaceborne optical switching system, method, and related apparatus based on a superframe time slot mechanism. The system includes several spaceborne nodes interconnected via inter-satellite laser links. Each spaceborne node comprises a master control node and slave nodes. The master control node maintains a global time reference, periodically collects service status information from each slave node, performs time slot and resource allocation calculations, and sends the optical switching configuration results to the execution layer. The slave nodes perform local service access, status acquisition and reporting, time synchronization locking, and transmit optical pulses or optical data signals according to a unified time system within their allocated time slots. This system, method, and related apparatus can overcome the bottlenecks in rate, power consumption, and latency caused by traditional electrical switching and software control methods, improving the speed, parallelism, and stability of the optical switching control process, thereby increasing the resource utilization of inter-satellite optical links and the overall throughput of the system.

The invention discloses a system and a method for accelerating a gene alignment execution process. The system comprises a processing thread management module, one or more dynamic caches and a dynamic cache management module. Wherein the processing thread management module is configured to set a gene comparison process as a multi-stage assembly line, each execution step of the gene comparison process corresponds to one assembly line stage on the multi-stage assembly line, and a plurality of processing threads are distributed for each assembly line stage; and dividing gene sequence data to be compared into a plurality of data blocks and providing the data blocks to the multi-stage assembly line for processing. The dynamic caches are used for data transmission between two pipeline stages, and each dynamic cache comprises at least two cache blocks. And the dynamic cache management module is configured to manage distribution and recovery of the dynamic caches between the two pipeline stages and control switching of working states between different cache blocks in each dynamic cache. According to the method, the overlapping degree of process calculation and input and output is higher, the memory efficiency is higher, and the performance of overall execution is improved.

The utility model discloses a kind of composite material compression test fixtures of synchronous pressure application, including chassis and clamping block;Chassis includes bottom plate that can be installed on test table and the back plate and two side plates connected with bottom plate;Two pairs of clamping block are symmetrically arranged, and each pair of clamping block is symmetrically arranged;The upper and lower clamping block of one side is slidably installed on the same movable plate by first vertical guide structure, movable plate side portion is slidably installed on back plate by horizontal guide structure, movable plate is installed with clamping power component in the side away from clamping block, clamping power component is towards one side side plate, clamping power component is used to resist on side plate and promote the clamping of clamping block in the side;The upper and lower clamping block of the other side is slidably installed on the same fixed plate by second vertical guide structure, and fixed plate is installed on the other side plate;Clamping block is close to the end of effective test area and is equipped with extension and arc chamfer.This fixture can slow down the stress concentration of clamping block end in sample effective test area, and left and right clamping block load distribution is uniform.

The application relates to a special-shaped inner ring forming process based on roughening treatment, which comprises the following steps: 1) roughening treatment; and 2) cutting processing. The application realizes the clamping and cutting of the special-shaped inner ring taking the annular groove as a positioning reference based on roughening, effectively avoids the stress concentration and deformation of one of the two convex edges due to the over-thin thickness, improves the yield of products, and avoids the increase of the allowance of the annular groove due to the over-wide width under the processing requirements of the corresponding thickness and width, thereby improving the parallelism, flatness and roundness precision of the products.

The application discloses a CSR storage format-based SpMV implementation method and device and a medium, wherein the method comprises the following steps: dividing the SpMV into three segment operations, the three segment operations being a value operation, a product operation and a summation operation respectively, and each segment operation corresponding to a task; dividing each task into a plurality of task blocks; dividing all threads into a plurality of vectors, one vector comprising vector_size threads, and the vector being an execution unit of the task block; designing two launch queues and one counter to record the ready state of the task block; each vector acquiring and executing the task block in the ready state, and updating the ready state of the task block after execution; and when all the task blocks are executed, the SpMV operation is completed. The application divides the value and the product into task blocks of a fixed size, and improves the data utilization rate of GPU memory access. The application can be widely applied to the technical field of high-performance numerical calculation.

The application provides a micro-powder filling and micro-crystal fitting composite production line, which comprises a plurality of mechanical arms and wafer fitting equipment, a primary vibration powder supply device and a primary pressing device, and a powder secondary vibration powder supply pressing device; the mechanical arms are arranged between the primary vibration powder supply device and the primary pressing device, between the primary pressing device and the wafer fitting equipment, between the wafer fitting equipment and the secondary vibration powder supply device, and between the secondary vibration powder supply device and the secondary pressing device to link the feeding and discharging; the primary vibration powder supply device is provided with a first dust removal device, the primary pressing device is also provided with a first pressing dust removal mechanism, the powder secondary adding device is provided with a secondary dust removal mechanism, and the powder secondary pressing device is provided with a second pressing dust removal mechanism, so that surface dust removal can be performed in time after the powder is added and after the powder is pressed, and the overflowed powder can be avoided from being brought into the next station; and the relay operation of the plurality of mechanical arms replaces the traditional flow channel transmission.

This invention belongs to the field of computer dataflow architecture design technology, and relates to a sub-core-level task collaborative scheduling method and scheduling management unit for heterogeneous dataflow architectures. The method includes: splitting computational tasks into multiple operators, and further refining each operator into multiple sub-cores to construct sub-core waiting queues; clustering operators into different collaborative execution units based on data dependencies and sharing patterns, and constructing sub-core running queues; dynamically monitoring the availability status of the processing unit array during runtime, and dynamically allocating non-conflicting processing unit resources to multiple sub-cores using a resource masking mechanism; updating the status of a sub-core after its execution and releasing the corresponding processing unit resources; iterating the above process until all queues are empty, at which point scheduling ends. This invention, through a sub-core-level task collaborative scheduling mechanism combined with data reuse technology, simultaneously deploys multiple sub-cores to the processing unit array for execution, achieving efficient resource utilization and computational parallelization, and significantly improving the overall system performance.

The invention discloses a matrix multiplication optimization method and system oriented to an RISC-V architecture, and the method comprises the steps: detecting the hardware characteristics of a target RISC-V platform, and adaptively configuring optimization parameters according to a detection result; performing memory layout and data rearrangement on the input matrix B to realize memory optimization; a multi-level partitioning strategy is adopted to adapt to a memory hierarchical structure, and multi-level partitioning calculation is achieved; carrying out RVV vectorization core calculation by using RISC-V vector instruction extension to realize data-level parallel optimization; the instruction delay is hidden through loop expansion and a software assembly line, and a data prefetching mechanism is adopted to realize instruction-level parallel optimization; performing multi-core parallel computing by using an OpenMP multi-thread technology to realize thread-level parallel optimization; and calculating residual elements by using a vector register to realize tail processing optimization. According to the method, the cache hit rate and the calculation performance degree are improved, the hardware potential is fully excavated, and the method is suitable for edge devices with high requirements.

The invention discloses a segmented modeling and parameter identification method for an asymmetric electro-hydraulic actuator system. The method comprises the following steps that the asymmetric electro-hydraulic actuator system is modularly split into a motor control pump model and a hydraulic transmission model; aiming at the characteristics of the two sub-modules of the motor pump control model and the hydraulic transmission model, respectively establishing mathematical models, and solving corresponding transfer functions; input excitation is applied to each sub-module, output signals are collected, a model parameter relation matrix is established, Bode frequency domain characteristic fitting is carried out on the motor pump control module, an input and output relation is established for the hydraulic transmission model, time domain parameter fitting is carried out, and segmented identification is achieved until the preset identification precision requirement is met; and integrating the sub-module models of which the identification precision is completed, and constructing a complete identification model of the asymmetric electro-hydraulic actuator system. According to the method, the nonlinear characteristic of each module can be accurately identified, the dynamic performance of the system is optimized, and the control precision of the system is improved.

The utility model relates to processing device technical field provides a kind of slab processing auxiliary tool and processing system, including slab, with oppositely arranged first board surface and second board surface, second board surface is set to ground;At least one group of support structure, each group of support structure includes multiple support column that are arranged on the first board surface along the first board surface circumferential interval, the end surface of multiple support column away from the first board surface is in the same horizontal plane, and be configured to with the board surface connection of slab to be processed.The scheme provided by the utility model improves the flatness of slab products after processing.

The application provides a reconfigurable computing architecture mapping method based on graph convolution and reinforcement learning, comprising the following steps: acquiring a data dependency graph and a coarse-grained reconfigurable array, and calculating a minimum start interval of the data dependency graph; preprocessing the data dependency graph according to the minimum start interval; simplifying a hardware model resource graph according to the structure of the coarse-grained reconfigurable array; taking a node set of the hardware model resource graph as an action space; adopting a reinforcement learning model based on a graph convolution network to map the preprocessed data dependency graph, so as to obtain a mapping result of a data dependency graph node on the hardware model resource graph; calculating a reward value of the mapping result; and when it is judged according to the reward value that the mapping result meets a successful mapping condition, outputting the mapping result. The application optimizes the layout and wiring of a loop on a reconfigurable computing array by using graph convolution and reinforcement learning, improves the parallelism of loop execution, and thus increases the mapping quality and reduces the execution time of image denoising.

The application provides a non-volatile semiconductor memory array and a method for in-memory logic operation. In the array, a row of memory cells shares a word line, a column of memory cells shares a bit line and a storage gate lead, the source terminals of every two columns of memory cells are interconnected and connected to the same source lead CSL, and the end of each CSL is provided with a sensitive amplifier SA controlled by an enabling signal. One of the memory cells in every two columns has a substrate split, or the cell is replaced by a DCC cell. The method includes pre-writing, pre-charging, charging and discharging estimation, and judgment and result writing. The input and output are the storage states of different memory cells. The charging and discharging of the parasitic capacitor on the source lead when the memory cell is opened are detected as the input, and the SA is used to make a logic judgment and complete the writing. In one operation, any two-input logic except XOR and XNOR can be realized, and the logic result can be directly used as a logic input to realize cascading. The logic operation has many types, few steps, low difficulty and high efficiency.

The foldable projector lamp structurally comprises a rotating shaft connecting block, a bearing block, a limiting body, a heat dissipation pipe and a lamp body, the rotating shaft connecting block is fixed to the lower end of the bearing block, the center of the surface layer of the bearing block coincides with the circle center of the limiting body, and the heat dissipation pipe is perpendicularly arranged at the upper end of the bearing block through the limiting body; the lamp body is embedded in the inner layer area of the heat dissipation pipe and fixedly connected with the inner layer area. After a bearing block is further improved, an overturning piece and a rotator of an insulator can be controlled on line under adaptation of a signal receiving box, so that the overturning piece completes adjustment of the position of a baffle through overturning, meanwhile, the rotator rotates forwards and backwards, and the length of a heat dissipation pipe and the length of a lamp body can be controlled through a screw; therefore, the spotlight can be folded, the defect that the center of the spotlight body deviates due to mismatched positions is overcome, and meanwhile, the storage convenience of the follow-up spotlight can be improved and the control convenience during film and television shooting can be improved by reducing the size of the whole spotlight through folding.

This invention discloses a method for parallelizing and pipelining a nested multiplier, relating to the field of intelligent warehousing technology. Based on the nested multiplication concept, the multiplication operation is decomposed into a formula to obtain the squaring operation of the high-bit part and the difference of squares plus shift operation of the low-bit part. Based on the characteristic of 2ab in the multiplication formula, the intermediate values ​​required for high-bit calculation are obtained by querying a preset low-bit square value table through the low-bit results. For batch data, multiple sets of data are processed simultaneously through a parallel architecture. The overall calculation process is divided into multiple pipeline stages, and continuous calculation is achieved through stage cascading. The pipeline output results of each parallel computing unit are collected, verified, and integrated to output a complete set of multiplication results. This invention achieves breakthroughs in hardware resources, computational latency, and batch throughput through the collaborative design of nested recursive simplification, pipeline reuse, and parallel architecture, providing an efficient solution for high real-time and high-parallelism digital computing scenarios.

The application discloses a processing method of a wing piece, which comprises the following steps: first, connecting a processed piece with a processing tool; second, stacking equal-height iron and a base in sequence between flat mouth vices, and clamping the flat mouth vices on both sides of the base; third, contacting a dial gauge with a measuring side surface of the base, dragging the base by the flat mouth vices, observing and reading the value of the dial gauge, adjusting the base which does not meet the standard until the value change meets the standard; fourth, contacting the dial gauge with a measuring top surface of the base, dragging the base by the flat mouth vices, observing and reading the value of the dial gauge, adjusting the base which does not meet the standard until the value change meets the standard; and fifth, processing rectangular ends of the processed piece by using a processing tool until all the rectangular ends are processed into the shape of the wing piece. In application, the flat mouth vices can clamp multiple processing tools at a time, so that the flat mouth vices can calibrate multiple processing tools at a time, and the machine tool can process multiple processed pieces at a time after calibration. Therefore, the processing efficiency is high.

The application discloses a multifunctional optoelectronic logic gate device based on circularly polarized light and a preparation method and application thereof, comprising a bottom substrate, a bottom electrode, a chiral light-absorbing active layer, a top transparent electrode and a top transparent packaging layer which are sequentially stacked. The chiral light-absorbing active layer comprises lead-free chiral molecules, skeleton materials, carrier transport materials and stabilizers. The application utilizes the intrinsic differential response of chiral materials to left-handed and right-handed circularly polarized light to directly realize circularly polarized light detection on a single device. By synergistically regulating the polarization state, light intensity and / or external bias of incident light, the device can serve as a reconfigurable logic gate to output various binary or multi-value logic operation results. The application has the advantages of environmental friendliness and high stability, and realizes the integration of detection, logic and potential imaging functions. The device structure is simple, the preparation process is convenient, and the application has a wide application prospect in the fields of optical computing, information encryption and polarization imaging.

The application discloses a kind of intelligent reflecting surface unit with wideband low loss and intelligent reflecting surface, including interval air layer arrangement first dielectric substrate and second dielectric substrate, the first dielectric substrate one side is provided radiation patch, the one side of the second dielectric substrate is provided metal ground plate, the other side of second dielectric substrate is provided direct current control line, the radiation patch includes multiple coplanar metal patches, each metal patch is slotted in vertical direction and is connected using varactor, by controlling the direct current voltage at both ends of multiple varactors, so that the phase shift of intelligent reflecting surface unit continuously changes.The application not only reduces the reflection loss of unit, improves the directivity coefficient bandwidth of intelligent reflecting surface antenna, and the radiation performance has good stability in frequency band.

The application discloses a SYBR Green fluorescent quantitative PCR method for identifying Cyperus esculentus components based on a Ce44 gene and application thereof, and establishes a specific and high-sensitivity Cyperus esculentus component detection method by using a single copy gene of a Cyperus esculentus plant genome as a marker gene based on a SYBR Green real-time fluorescent quantitative technology.The method can accurately distinguish the Cyperus esculentus from four Cyperaceae plants and other 12 representative plants, and can accurately determine whether the six food samples on the market contain the Cyperus esculentus component.The specific real-time fluorescent quantitative PCR detection method for the Cyperus esculentus established by the application can provide a technical reference for qualitative and quantitative detection of the Cyperus esculentus component in Cyperus esculentus products.