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1312 results about "Single node" patented technology

A single node cluster is a special implementation of a cluster running on a standalone node. You can deploy a single node cluster if your workload only requires a single node, but does not need nondisruptive operations.

Novel massively parallel supercomputer

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input / Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.
Owner:INT BUSINESS MASCH CORP

Process and apparatus for tracing software entities in a distributed system

The invention relates to a process and apparatus for tracing software entities, more particularly a tracing tool providing tracing capabilities to entities in an application. The object-tracing tool provides software components to allow tracing the execution of an application. Tracing software entities is important for software developers to permit the quick localization of errors and hence facilitate the debugging process. It is also useful for the software user who wishes to view the control flow and perhaps add some modifications to the software. Traditionally, software-tracing tools have been confined to single node systems where all the components of an application run on a single machine. The novel tracing tool presented in this application provides a method and an apparatus for tracing software entities in a distributed computing environment. This is done by using a network management entity to keep track of the location of the entities in the system and by using a library of modules that can be inherited to provide tracing capabilities. It also uses a log file to allow the program developer or user to examine the flow, the occurrence of events during a trace and the values of designated attributes. The invention also provides a computer readable storage medium containing a program element to direct a processor of a computer to implement the software tracing process.
Owner:RPX CLEARINGHOUSE

Methods for visualizing transformations among related series of graphs

A method for displaying in a coherent manner the changes over time of a web site's structure, usage, and content is disclosed. Time tubes are generated by a method of displaying a related series of graphs. Time tubes illustrate changes in a graph that undergoes one or more transformations from one state to another. The transformations are displayed using the length of the cylindrical tube, filling the length of the time tube with planar slices which represent the data at various stages of the transformations. Time tubes may encode several dimensions of the transformations simultaneously by altering the representation of size, color, and layout among the planar slices. Temporal transformations occur when web pages are added or deleted over time. Value-based transformations include node colors, which may be used to encode a specific page's usage parameter. Spatial transformations include the scaling of physical dimension as graphs expand or contract in size. The states of a graph at various times are represented as a series of related graphs. In a preferred embodiment, an inventory of all existing nodes is performed so as to generate a list of all nodes that have existed at any time. This inventory is used to produce a layout template in which each unique node is assigned a unique layout position. To produce each planar slice, the specific nodes which exist in the slice are placed at their respective positions assigned in the layout template. In another aspect, corresponding nodes in planar slices are linked, such as with translucent streamlines, in response to a user selecting a node in a planar slice by placing his cursor over the selected node, or to show clustering of two or more nodes in one planar slice into a single node in an adjacent planar slice.
Owner:GOOGLE LLC

Interrupt architecture for a non-uniform memory access (NUMA) data processing system

A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.
Owner:IBM CORP

Massively parallel supercomputer

InactiveUS7555566B2Massive level of scalabilityUnprecedented level of scalabilityError preventionProgram synchronisationPacket communicationSupercomputer
A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input/Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.
Owner:IBM CORP

Data verification method based on block chains and data verification system thereof

The invention discloses a data verification method based on block chains and a data verification system thereof. The data verification method comprises the steps that the sensing data of the environment and/or household equipment state are acquired through multiple wireless sensor nodes of a wireless sensor network and processed and then uploaded to a data repeater; the data repeater receives the processed sensing data and then forwards the sensing data to a data verification network; multiple data verification nodes in the data verification network are responsible for verifying and saving the sensing data; and all the data verification nodes are block chain nodes, and multiple data verification nodes form a distributed database. The data verification task is completed by using the data verification nodes, and the verification work is distributed to the verification nodes from the data repeater so that the problems of being low in verification efficiency, low in speed, high in transmission delay and vulnerable because of the excessively centralized verification task can be overcome, and the nodes are excited to actively authenticate the data and rapidly complete the verification task so that the whole verification system is not influenced by single node failure of any node.
Owner:GUANGDONG UNIV OF TECH

School roll tracing authentication method based on block chains

ActiveCN107257341AProtect student privacyRetrospective Certification RealizationData processing applicationsTransmissionThird partyAuthentication
The invention discloses a school roll tracing authentication method based on block chains. The school roll tracing authentication method has the implementing process of: firstly, configuring a school block chain which comprises a plurality of region block chains, wherein in each region block chain, an independent P2P network is formed by a plurality of school nodes; configuring a monitoring block chain, and forming an independent P2P network by a plurality of monitoring nodes corresponding to the school block chain and at least one admission node; configuring a third-party CA authentication center, and connecting the monitoring block chain for issuing certificates to the school nodes which pass authentication determination; and configuring an inquiring node and implementing verification and tracing of school roll files by inquiring the school block chain and the monitoring block chain. Compared with the prior art, according to the school roll tracing authentication method based on the block chains, which is disclosed by the invention, partitioning is carried out according to regions, generation of the block chains can be more efficiently completed, and calculation efficiency is improved; and a plurality of monitoring mechanisms exist in each region, and admission of the nodes is strictly controlled, thereby benefiting for improving supervision and effectively solving the problem of single node failure.
Owner:SHANDONG INSPUR SCI RES INST CO LTD

Multi-thread parallel processing method based on multi-thread programming and message queue

ActiveCN102902512AFast and efficient multi-threaded transformationReduce running timeConcurrent instruction executionComputer architectureConcurrent computation
The invention provides a multi-thread parallel processing method based on a multi-thread programming and a message queue, belonging to the field of high-performance computation of a computer. The parallelization of traditional single-thread serial software is modified, and current modern multi-core CPU (Central Processing Unit) computation equipment, a pthread multi-thread parallel computing technology and a technology for realizing in-thread communication of the message queue are utilized. The method comprises the following steps of: in a single node, establishing three types of pthread threads including a reading thread, a computing thread and a writing thread, wherein the quantity of each type of the threads is flexible and configurable; exploring multi-buffering and establishing four queues for the in-thread communication; and allocating a computing task and managing a buffering space resource. The method is widely applied to the application field with multi-thread parallel processing requirements; a software developer is guided to carry out multi-thread modification on existing software so as to realize the optimization of the utilization of a system resource; and the hardware resource utilization rate is obviously improved, and the computation efficiency of software and the whole performance of the software are improved.
Owner:LANGCHAO ELECTRONIC INFORMATION IND CO LTD

Distributed Pluggable Middleware Services

Plug-in configurable middleware is provided for managing distributed applications. The middleware includes at least one core runtime engine configured as a plurality of concurrent instantiations on one or more hosts within a distributed architecture. These hosts can represent separate nodes or a single node within the architecture. Each core runtime engine instance provides the minimum amount of functionality required to support plug-in architecture, that is to support the instantiation of one or more plug-ins within that core runtime engine instance. Each core runtime engine instance is in communication with other concurrent core runtime engine instances and can share the functionality of plug-in instances with the other core runtime engine instances, for example through the use of proxies. A plurality of personalities representing pre-defined functions is defined and one of more of these personalities is associated with each core runtime engine instance. A plurality of pre-defined plug-ins are defined and associated with the personalities. Each plug-in is a unit of function containing runtime code that provides a portion of the function a personality to which the plug-in is associated. The plug-ins are instantiated on the appropriate core runtime instances to provide the function to that core runtime engine instance as defined in the associated personality.
Owner:IBM CORP
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