The invention discloses a
graph mapping method based on precise synthesis, and the method comprises the steps: constructing a precise synthesis structure
library based on NPN equivalence classes, and inputting the precise synthesis structure
library into a
Boolean network; k-
Cut cutting enumeration is carried out on the input
Boolean network, a
truth table is calculated,
cutting is matched with a structure in a precise comprehensive structure
library through Boolean matching, and rapid search is realized in combination with NPN classification; the
overlay network is generated through multi-round mapping optimization, logic sharing nodes are mined in combination with structural hash, and the multi-round mapping optimization comprises
delay-oriented mapping, global area
topological optimization and local accurate area optimization; and a new target network is generated based on the optimized
overlay network, redundant nodes are removed, and final
network construction is completed. According to the method, manual intervention is not needed through full-process automatic mapping and a redundancy removal mechanism, the labor cost of a technical mapping link in
chip design is remarkably reduced, and the method is particularly suitable for efficient design of complex circuits and emerging majority of logic base technologies.