122 results about "Parity-check matrix" patented technology

The invention belongs to the technical field of communication, and particularly relates to a multiplication active code decoding method based on an SO-ORBGRAND decoder. The SO-ORBGRAND decoder outputs soft information by calculating a correct posterior probability of a conjecture code word sequence, and high-performance decoding is realized through soft information exchange and optimization processing between the row decoder and the column decoder. In the iteration process, a method for judging the validity of the code word through the check matrix is designed by utilizing the polarization characteristic of the multiplication active code, so that the iteration is supported to jump out in advance to reduce the complexity. The invention provides a multiplication active code decoding algorithm based on an SO-ORBGRAND decoder, and compared with various non-system multiplication active code decoding algorithms and the performance of traditional long-code polarization codes, the method has remarkable advantages in error correction performance; a method for judging the validity of the code word through the check matrix by utilizing the polarization characteristic design of the multiplication positive code is provided, the complexity is reduced while the judgment success rate is improved, and the implementation overhead is reduced.

The invention discloses a flash memory error correction method and system based on adaptive learning, and relates to the technical field of data storage.The flash memory error correction method comprises the steps that flash memory voltage distribution and error code positions are collected in real time, and dynamic feature vectors are generated in combination with environmental parameters; constructing a hypergraph neural network based on the dynamic feature vectors, obtaining error propagation risk scores of the storage areas, and generating a priority list; based on the priority list, the check connectivity of the low-density parity check matrix is adjusted through matrix reconstruction, and a sparse check matrix is formed; an initialization parameter and a solution vector are generated based on the decoder ready state signal, sampling iteration and threshold judgment are carried out, and a decoding result is output; and when decoding fails, performing multi-device parameter updating by adopting aggregation optimization, and performing decoding again to output final correction data. According to the method, collaborative error correction is optimized through multi-device parameter aggregation, so that the limitation of single-device decoding is solved, the global error correction performance is optimized, and the fault-tolerant capability is enhanced.

A memory device and method for a partial checksum calculation using a sub-matrix with flexible media coverage inside of a memory device (i.e., NAND) of a memory system. The memory device includes: a plurality of memory cells; a control circuit configured to read a codeword sequence from the plurality of memory cells, and determine a sub-matrix including multiple non-zero circulants selected from particular matrix rows of a parity check matrix used in a controller of the memory system, the multiple non-zero circulants including non-zero row circulants for each matrix row; and a partial checksum calculator configured to perform a partial checksum calculation on a syndrome sequence based on the codeword sequence and the sub-matrix.

Transformer neural network based decoder for decoding Quantum Error Correction Codes (QECC), comprising, an input layer, a plurality of decoding layers, and an output layer. The input layer is adapted to receive initial noise estimation computed by a noise estimator for noise injected to syndrome bits of codewords encoded using QECC and transmitted over transmission channel(s) subject to interference, and create embeddings for the syndrome bits. The decoding layers adapted to compute an estimated logical operator matrix of each codeword, each comprises a self-attention layer constructed according to a mask indicative of a relation between the embeddings derived from a parity-check matrix of the error correction code. The plurality of decoding layers are trained using a combined loss function directed to minimize LER, BER, and error rate of the noise estimator. The output layer is adapted to produce a vector representing predicted soft error of the codeword's logical operator matrix.

An ECC engine of a semiconductor memory device includes an ECC encoder and an ECC decoder. The ECC encoder generates parity data based on main data based on a primitive polynomial and stores a codeword including the main data and the parity data in a target page. The ECC decoder reads the codeword from the target page based on an address to generate a syndrome and corrects at least one error bit in the read codeword based on the syndrome by respectively applying different syndromes to a single bit error in the read codeword, adjacent bit errors and non-adjacent bit errors occurring in non-adjacent two memory cells in the target page. The ECC decoder generates the different syndromes based on a parity check matrix generated as a function of the primitive polynomial. The primitive polynomial has an alpha matrix as a solution belonging to a Galois field.

Memory controllers and memory systems including the same are disclosed. The memory controller is configured to control a memory module, the memory controller comprising: processing circuitry configured to: perform ECC decoding of a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome; determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome; and output a decode status flag indicative of the type of error.

A semiconductor memory device includes an array of memory cells, an on-chip error correction code (ECC) engine, a link ECC engine. The link ECC engine receives, in a write operation, a first codeword including first main data and first link parity data from a memory controller, generates a first syndrome including a plurality of syndrome bits based on the first codeword and a first parity check matrix based on the first ECC, generates a decoding status flag indicating whether a transmission error is detected in the first codeword using a property of the first syndrome based on regularity of the first parity check matrix while decoding the first syndrome, corrects an error bit of the first codeword based on the decoded first syndrome, and provides the first main data of the corrected first codeword to the on-chip ECC engine.

An LDPC encoder is described with memory for storing a parity check matrix and a calculation unit to encode information bits into a codeword with reference to the parity check matrix. The parity check matrix includes an information part matrix and a parity part matrix. In the parity part matrix, Z*Z sub-matrices are sub-matrices, other than a zero matrix, and are arranged in each of the m rows and m columns. A sub-matrix is a scaled cyclic matrix obtained by shifting elements of an identity matrix by one to the left and multiplying the shifted elements by a scaling element. Except for the scaled cyclic matrix, the remaining sub-matrices are a zero matrix or an identity matrix, and the scaling element is an element allowing the parity part matrix to satisfy a full rank condition on a Galois field.

The application discloses a quasi-cyclic low-density parity-check code decoding method, system, device and medium, acquires a predetermined parity-check matrix; adjusts the parity-check matrix into a target operation matrix composed of a unit matrix and a displacement matrix, the dimensions of the unit matrix and the displacement matrix are both p x p; acquires a target codeword to be decoded corresponding to a current decoding recursion number; splits the target codeword into target sub-codewords with a length of p; in the target operation matrix, determines a target operation sub-matrix corresponding to each target sub-codeword; performs parallel operation on the target sub-codewords and the target operation sub-matrix to obtain a syndrome value of the target codeword; determines a current decoding result of the current decoding recursion number based on the syndrome value, and determines a target decoding result based on the current decoding result. In the application, parallel operation is performed on the corresponding target operation sub-matrix and the target sub-codeword, the operation efficiency of the syndrome value can be improved, and the operation efficiency of the entire decoding method is further improved.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a low density parity check (LDPC) code may include a parity check matrix (PCM) with a lifted parity submatrix. The lifted parity submatrix may include an upper-triangular portion having non-zero diagonal elements, a high-degree column portion, an all-zero portion, and a remaining portion, resulting in improved encoding efficiency. In some aspects, a transmitter may encode, in a first encoding operation, the upper-triangular portion and the high-degree column portion, and the transmitter may encode, in a second encoding operation, the all-zero portion and the remaining portion of the lifted parity submatrix. The encoded lifted parity submatrix may be transmitted from the transmitter to a receiver in a PCM as part of an LDPC code. Additionally, a base graph PCM structure may be included in the remaining portion of the lifted parity submatrix. Numerous other aspects are described.

This invention relates to network coding technology and discloses a network coding method based on maximum rank distance code. The method includes: performing network coding on transmitted data to obtain coded data; performing linear addition and multiplication on the coded data to obtain coded data packets; using a preset parity check matrix to perform error detection and location on the coded data packets to obtain an error matrix; and performing rank error correction on the coded data packets based on the error matrix to obtain the original source data. This invention also provides a network coding apparatus, device, and medium based on maximum rank distance code. This invention can reduce the amount of redundant data transmitted in the transmission network and maintain low latency and high data recovery success rate even in complex network environments.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 3 / 4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 144 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

A method for generating a parity check matrix, and a communication apparatus. The method comprises: acquiring a base matrix, the base matrix comprising a first matrix, the first matrix being a matrix consisting of the first column to the tenth column and the first row to the fourth row of the base matrix, elements comprised in the first column of the base matrix being all non-zero elements, and the first column being a punctured column; and, on the basis of the base matrix, obtaining a parity check matrix of a non-binary low-density parity check (LDPC) code, the parity check matrix being used for LDPC coding or LDPC decoding. The elements comprised in the first column of the base matrix are all non-zero elements, and the first column is a punctured column, such that the code rate of the LDPC code corresponding to the base matrix provided in the method can reach 2 / 3. Compared with the prior art, the method improves the code rate of non-binary LDPC codes, thereby improving coding and decoding performance of non-binary LDPC codes.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 3 / 4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 144 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

An apparatus may include a receiver and one or more processors. The receiver may receive log likelihood ratio (LLR) values corresponding to encoded data that is encoded using a low-density parity-check (LDPC) code. The one or more processors may identify a number of punctured parity bits corresponding to the encoded data, determine that the number of punctured parity bits is less than a threshold, and remove, from a first parity check matrix corresponding to the encoded data, one or more rows corresponding to the number of punctured parity bits to generate a second parity check matrix. The one or more processors may determine, using the LLR values and the second parity check matrix, that there is an error in the LLR values, and an LDPC decoder may decode, based at least on the determination, the LLR values to resolve the error.

The present disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate than a 4G communication system such as LTE. An encoding method performed by a transmission device of a communication system according to an embodiment of the present disclosure may comprise the steps of: identifying at least one parameter related to a convolutional code associated with a polarization-adjusted convolutional (PAC) code; on the basis of the at least one parameter, identifying a parity check matrix for an input binary vector of a polar code associated with the PAC code; on the basis of the parity check matrix, encoding a polar code concatenated with an outer code; and transmitting a codeword vector generated on the basis of the encoding.

This invention discloses a layered decoding method and apparatus for LDPC frames based on mutual information, relating to the field of digital signal transmission in the physical layer of wireless communication. The method includes the following steps: 1) Calculating the LLR value of a given codeword to be decoded, and performing Q-ratio specific-point quantization to maximize mutual information on the entire frame's LLR value; 2) Calculating the PP value of the Q-ratio specific-point quantized LLR value according to Bayes' formula; 3) Layering the PP values ​​of the LLR values ​​of the data to be decoded according to the coefficients of the parity check matrix H; 4) Calculating the information within the information node; 5) Performing parity check node update calculations according to the PMS decoding algorithm to obtain the information value outside the parity check node; 6) Updating the information node using the information value outside the parity check node; 7) Symbol decoding; 8) Calculating the syndrome according to H. If the result of the syndrome is 0 or the maximum number of iterations is reached, outputting the three-frame codeword result; otherwise, returning to step 3) for the next decoding iteration. This invention can effectively improve the decoding processing speed of each frame.

The invention relates to a short code length QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) code construction method based on a Stanley sequence and a genetic algorithm. According to the method, a Stanley sequence is used for forming first two rows of an index matrix meeting the condition that no four rings exist, then a genetic algorithm is used for searching a third row element which enables the index matrix to meet the requirements that the ring length is at least 8 and the number of trap sets is small, and therefore the index matrix with the girth length being at least 8 is obtained, the genetic algorithm can guarantee that the number of the trap sets is minimum, and the number of trap sets is small. And finally, the index matrix is expanded to obtain a parity check matrix of the index matrix, so that four rings and six rings do not exist in a Tanner graph of the check matrix, the number of trap sets is small, the storage space required by code words is small, and hardware implementation is easy. Simulation shows that compared with an HS-QC-LDPC code, an MT-QC-LDPC code and an SES-QC-LDPC code which have the same code rate and code length, the SS-QC-LDPC code constructed by the method has the advantages that the net coding gain is improved to a certain extent, and the constructed SS-QC-LDPC code has better waterfall region performance in a high signal-to-noise ratio region and has no obvious error leveling phenomenon.

An apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 5 / 6 and a code block size of 7776 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code, the first binary parity check matrix corresponding to a first exponent matrix. The one or more processors may be configured to encode data using the first binary parity check matrix. The transmitter may be configured to transmit the encoded data.

A decoder (30) for decoding low-density parity-check (LDPC) codewords. The decoder includes at least one core (10) and a memory (20) in which a number NC of predefined configurations are stored. The core is suitable for being dynamically configured with any one of the predefined configurations stored in the memory to decode an LDPC codeword using this configuration. The predefined configurations form a sub-group, in the strict sense, of 5G LDPC configurations defined in the 3GPP TS 38.212 standard. Each configuration corresponds to a triplet of three parameters {K, R, Z}, and to a parity matrix constructed according to at least a portion of these parameters. K is a message size encoded by the LDPC code, Z is an expansion factor of the parity matrix, and R is a code rate of the LDPC code.

Low density parity check (LDPC) codes for wireless communications are constructed to adapt to channel conditions. A method of encoding input bits by an LDPC code to obtain encoded bits is provided. A method of decoding the encoded bits is also provided. The LDPC code has a parity check matrix obtained by lifting a protograph matrix according to a lifting matrix, in which the lifting matrix is based on a polar kernel.

It is described a method of performing quantum error correction on a measurement-based quantum computer using fault complexes. A first chain complex is derived based on a first parity check matrix (PCM) and a second PCM that describe a quantum surface code. A second chain complex is derived based on a third PCM of a binary linear code. A fault complex having one or more boundary operators is generated based on a tensor product between the first and the second chain complexes. Qubits on the measurement-based quantum computer are prepared to implement a fault-tolerant graph state based on the one or more boundary operators of the fault complex. Quantum error correction can be performed based on the measurement of the prepared qubits.

One coding method of a plurality of coding methods including at least a first coding method and a second coding method is selected, an information sequence is encoded by using the selected coding method, and an encoded sequence obtained by performing predetermined processing on the information sequence is modulated and transmitted. The first coding method is a coding method having a first coding rate, for generating a first encoded sequence by performing puncturing processing on a generated first codeword by using a first parity check matrix. The second coding method is a coding method having a second coding rate, for generating a second encoded sequence by performing puncturing processing on a generated second codeword by using a second parity check matrix that is different from the first parity check matrix, the second coding rate after the puncturing process being different from the first coding rate.

The invention discloses an error correction coding method and device of a memory bank, electronic equipment and a storage medium, and relates to the technical field of error correction coding in a memory data reading and transmission process. According to the method, a 12-bit first check bit is generated based on a 12-bit first data bit and a reconstructed parity check matrix, and the reconstructed parity check matrix unifies the data column weight of the first data bit as 6 and the check column weight as 1; arranging the first data bits and the first check bits according to an alternating sequence to generate interleaving code words; splitting the interleaved code word into a second data bit and a second check bit, and calculating according to the second data bit and the reconstructed parity check matrix to obtain a third check bit; performing XOR operation on the second check bit and the third check bit to obtain a syndrome; and according to the syndrome and a preset combined syndrome rule table, performing a correction operation to obtain a corrected first data bit, thereby solving the problem of errors of multiple adjacent bit data in a data transmission process, and reducing the complexity and delay of a coding and decoding module.

A soft input is obtained from a sense word corresponding to encoded host data read from the memory device and decoded using a parity-check matrix. A match array is maintained. Each iteration of an error correcting code operation a number of unsatisfied check nodes of a respective bit of the sense word is calculated for each bit of the sense word. A bit flip threshold from a threshold data structure is obtained based on a current iteration of the error correcting code operation, a soft bit associated with the respective bit, and a match bit associated with the respective bit. The respective bit is flipped based on the number of unsatisfied check nodes satisfying the bit flip threshold.

An apparatus (105) includes a transmitter (120) and one or more processors (2010). The one or more processors (2010) is configured to identify, according to a code rate of 1 / 2 and a code block size of 7776 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check, QC-LDPC, code, the first binary parity check matrix corresponding to a first exponent matrix. The one or more processors (2010) encode data using the first binary parity check matrix. The transmitter (120) transmits the encoded data.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 1 / 2, a second parity check matrix corresponding to a first exponent matrix comprising 1152 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

This invention provides an efficient parallel encoding and decoding method for BCH codes, belonging to the technical field of BCH encoding and decoding circuit implementation in the areas of memory and error correction coding. Unlike previous lookup table methods, for an (n, k, t) BCH code with an n-bit codeword length, k data bits, and t-bit error correction capability, this invention only needs to store the values ​​of k n-k bit parity check matrix column vectors. These k n-k bit parity check matrix column vectors are then XORed with the S-synonym value for t rounds. The error pattern corresponding to the received codeword is obtained from the bitwise XOR value and corrected. This invention is a hardware-level encoding and decoding implementation, which can be completed within one clock cycle, reducing the multi-cycle decoding delay caused by iterative algorithms, achieving parallelization of BCH encoding and decoding, simplifying the encoding and decoding process, and reducing resource consumption.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 2 / 3, a second parity check matrix corresponding to a first exponent matrix comprising 768 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.