223 results about "Parity-check matrix" patented technology

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 3 / 4, a second parity check matrix corresponding to a first exponent matrix comprising 576 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 5 / 6, a second parity check matrix corresponding to a first exponent matrix comprising 384 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

The invention provides an optical-electric hybrid ultra-low time delay communication method and system, and relates to the technical field of communication, and the method comprises the steps: outputting a global synchronous clock signal with clock jitter less than 1ppm, dynamically dividing micro time slot resources in an orthogonal frequency division multiplexing symbol period, and generating a dynamically adjusted micro time slot resource distribution result; calculating an optimal phase offset matrix of the metasurface intelligent reflecting surface through a depth deterministic strategy gradient algorithm to obtain an optimized electromagnetic wave propagation path; generating a global optimization check matrix by aggregating the locally trained lightweight error correction model gradient of each node to obtain a compensated data stream; and constructing a causal graph model dynamic pruning high-entropy path to minimize causal entropy, through multi-agent reinforcement learning, taking time delay-energy efficiency as a game target to decide an optimal modulation order and a subcarrier switching strategy, and obtaining an optimized stable communication link. According to the invention, high-reliability and low-delay communication basic support is provided for high-precision intelligent manufacturing.

Techniques are disclosed for reducing overhead during hybrid automatic repeat request (HARQ) operations performed by a user equipment (UE) during wireless communication. The UE receives a message over the wireless network and obtains a parity check matrix (PCM) associated with a received message. Rows of the PCM are assigned to respective groups of a plurality of groups, where the respective groups have corresponding one or more parity checks as determined by the PCM. The UE generates a feedback message including a plurality of bits, wherein an individual bit of the plurality of bits indicates whether a corresponding respective group of the plurality of groups include one or more unsatisfied parity checks. The UE then transmits the feedback message to a base station of the wireless network.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 2 / 3, a second parity check matrix corresponding to a first exponent matrix comprising 768 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 1 / 2, a second parity check matrix corresponding to a first exponent matrix comprising 1152 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

The invention belongs to the technical field of communication, and particularly relates to a multiplication active code decoding method based on an SO-ORBGRAND decoder. The SO-ORBGRAND decoder outputs soft information by calculating a correct posterior probability of a conjecture code word sequence, and high-performance decoding is realized through soft information exchange and optimization processing between the row decoder and the column decoder. In the iteration process, a method for judging the validity of the code word through the check matrix is designed by utilizing the polarization characteristic of the multiplication active code, so that the iteration is supported to jump out in advance to reduce the complexity. The invention provides a multiplication active code decoding algorithm based on an SO-ORBGRAND decoder, and compared with various non-system multiplication active code decoding algorithms and the performance of traditional long-code polarization codes, the method has remarkable advantages in error correction performance; a method for judging the validity of the code word through the check matrix by utilizing the polarization characteristic design of the multiplication positive code is provided, the complexity is reduced while the judgment success rate is improved, and the implementation overhead is reduced.

In an aspect, digital communication coding methods (or simply coding methods) are provided, said methods comprising providing families of quasi-cyclic low-density parity check, LDPC, codes each represented by a single equation. Said single equation is derived from a geometry whose nature implies good error correcting properties for each of the LDPC codes and allows quasi-cyclic parity check matrices to be constructed for geometric LDPC codes of exceedingly long length, up to and exceeding four hundred thousand bits. The construction of such check matrices is not possible by any other known method. The LDPC codes have different lengths and different rates and the families of LDPC codes are provided with a guarantee of minimum distance. The geometric and quasi-cyclic properties of the LDPC codes allow low complexity decoding with very low frame error rates. Systems, computing systems and computer programs suitable to perform such coding methods are also provided.

The embodiment of the invention provides a coding and decoding method and device and a storage medium, relates to the technical field of communication, and can reduce the storage space requirement of coding. The method comprises the steps that a parity check matrix is determined, the dimension of the parity check matrix is determined based on the dimension of a binary extension matrix, the binary extension matrix is obtained by hashing an index matrix based on a lifting factor, and the lifting factor is determined based on the order of a binary basic matrix, an information bit sequence and a non-binary low-density parity check code NB-LDPC code; and according to the parity check matrix or a generation matrix corresponding to the parity check matrix, performing NB-LDPC coding on the information bit sequence to obtain a coding sequence.

The invention discloses a bit flipping decoding method and device for a low-density parity check code and a related medium. The method comprises the following steps of: 1, setting a target parameter; step 2, performing calculation based on the original code word and the check matrix to obtain a syndrome, and if the syndrome is judged to meet a first preset condition, entering step 3; 3, calculating to obtain an energy value of a corresponding bit by using an exclusive-or result between the original code word and the overlapped code word and a syndrome; 4, when the number of iterations is larger than the number of predicted effective times, it is judged that the energy value meets a second preset condition, and the energy value is updated to be the overturning threshold value; 5, performing flipping on the bits of which the energy values are greater than or equal to the flipping threshold value; and step 6, repeating the step 2 to the step 5 until the syndrome is equal to a preset value or the number of iterations reaches the maximum number of iterations, and outputting a decoding result. According to the method, the step 2 to the step 5 are repeated, so that the decoding speed can be improved and the calculation complexity can be reduced while the strong error correction capability is ensured.

Provided are an encoding method and apparatus, a decoding method and apparatus, and a storage medium. The encoding method comprises: determining a parity check matrix, wherein the dimension of the parity check matrix is determined on the basis of the dimension of a binary extended matrix, the binary extended matrix is obtained by hashing an exponential matrix on the basis of a lifting factor, and the lifting factor is determined on the basis of a binary fundamental matrix, an information bit sequence, and the order of a non-binary low density parity check code (NB-LDPC); and performing NB-LDPC encoding on the information bit sequence on the basis of the parity check matrix or a generator matrix corresponding to the parity check matrix, to obtain an encoding sequence.

The invention discloses an LDPC encoder based on a DVB-S2 protocol, a transmitting terminal and a test platform, and the LDPC encoder comprises an information bit matrix multi-port input RAM which is used for storing input information bits; the check matrix multi-port ROM is used for storing a check matrix; the accumulative sum matrix RAM is used for storing the accumulative sum matrix generated by the accumulative sum matrix calculation module; the check bit matrix RAM is used for storing a check bit matrix; the check matrix calculation module reads a check matrix from the check matrix multi-port ROM, and the check matrix is converted into a cyclic shift matrix through preprocessing; the accumulative sum matrix calculation module is used for reading information bits from the information bit matrix multi-port input RAM, executing loop right shift and accumulative operation, and calculating to obtain an accumulative sum matrix; and the check bit matrix initialization module is used for calculating a check bit matrix initialization vector according to a calculation result of the accumulation and matrix calculation module.

The invention discloses a flash memory error correction method and system based on adaptive learning, and relates to the technical field of data storage.The flash memory error correction method comprises the steps that flash memory voltage distribution and error code positions are collected in real time, and dynamic feature vectors are generated in combination with environmental parameters; constructing a hypergraph neural network based on the dynamic feature vectors, obtaining error propagation risk scores of the storage areas, and generating a priority list; based on the priority list, the check connectivity of the low-density parity check matrix is adjusted through matrix reconstruction, and a sparse check matrix is formed; an initialization parameter and a solution vector are generated based on the decoder ready state signal, sampling iteration and threshold judgment are carried out, and a decoding result is output; and when decoding fails, performing multi-device parameter updating by adopting aggregation optimization, and performing decoding again to output final correction data. According to the method, collaborative error correction is optimized through multi-device parameter aggregation, so that the limitation of single-device decoding is solved, the global error correction performance is optimized, and the fault-tolerant capability is enhanced.

The invention discloses a high-code-rate QC-LDPC check matrix construction method and device for NAND, a medium and a product, and relates to the technical field of channel coding, and the method comprises the steps: firstly, generating an initial check matrix which is uniform in row weight distribution and is free of a four-ring structure; secondly, traversing a preset shift value range for each non-zero item of the initial check matrix, and selecting a shift value which enables the number of six rings to be minimum to generate an intermediate check matrix; and finally, based on the number of the six rings in which each non-zero item participates in the intermediate check matrix, sequentially eliminating the non-zero items participating in the most six rings to obtain a target check matrix. According to the method, the four-ring, six-ring and global balance is progressively optimized, so that the error correction performance of the check matrix is remarkably improved, the decoding time delay is reduced, and the reliability requirement of a high-bit-rate NAND flash memory is met.

A memory device and method for a partial checksum calculation using a sub-matrix with flexible media coverage inside of a memory device (i.e., NAND) of a memory system. The memory device includes: a plurality of memory cells; a control circuit configured to read a codeword sequence from the plurality of memory cells, and determine a sub-matrix including multiple non-zero circulants selected from particular matrix rows of a parity check matrix used in a controller of the memory system, the multiple non-zero circulants including non-zero row circulants for each matrix row; and a partial checksum calculator configured to perform a partial checksum calculation on a syndrome sequence based on the codeword sequence and the sub-matrix.

A transmitter is provided that shapes uniformly-distributed bits into a non-uniformly distributed bits according to a parity check matrix of a linear code such that a product of the parity check matrix and the non-uniformly distributed bits equals the uniformly-distributed bits. Similarly, receiver is provided that recovers the uniformly-distributed bits from the non-uniformly distributed bits through a multiplication of the non-uniformly-distributed bits with the parity check matrix.

Transformer neural network based decoder for decoding Quantum Error Correction Codes (QECC), comprising, an input layer, a plurality of decoding layers, and an output layer. The input layer is adapted to receive initial noise estimation computed by a noise estimator for noise injected to syndrome bits of codewords encoded using QECC and transmitted over transmission channel(s) subject to interference, and create embeddings for the syndrome bits. The decoding layers adapted to compute an estimated logical operator matrix of each codeword, each comprises a self-attention layer constructed according to a mask indicative of a relation between the embeddings derived from a parity-check matrix of the error correction code. The plurality of decoding layers are trained using a combined loss function directed to minimize LER, BER, and error rate of the noise estimator. The output layer is adapted to produce a vector representing predicted soft error of the codeword's logical operator matrix.

The invention discloses a flash memory controller and a flash memory access method. The flash memory controller includes a decoder that performs a decoding operation based on received information obtained by the flash memory and a parity check matrix of a quasi-cyclic low-density parity check code. The decoder comprises a variable node module, a V2C shift module and a check node module which are coupled in series. The decoder further comprises a state data shifting module which is used for circularly shifting the state data of the check node module and then feeding back the state data to the check node module, and the state data shifting module is coupled with the check node module in parallel. The serial coupling only has three stages, so that the decoding iteration convergence speed is improved, and the flash memory access efficiency is further improved.

A decoder includes a syndrome generator and an error pattern classifier. The syndrome generator generates a first syndrome, a second syndrome, and a third syndrome based on a reception vector and a parity check matrix and outputs the first syndrome, the second syndrome, and the third syndrome, The error pattern classifier receives the first syndrome, obtains symbol error location information obtained based on mapping information between a spotty and adjacent symbol error (SASE) and the first syndrome, changes the first syndrome to a normalized syndrome based on a first received symbol, obtains an adjacent error vector based on mapping information between the normalized syndrome, the second syndrome, and the third syndrome and the SASE, and corrects an error of the reception vector based on the symbol error location information and the adjacent error vector.

An ECC engine of a semiconductor memory device includes an ECC encoder and an ECC decoder. The ECC encoder generates parity data based on main data based on a primitive polynomial and stores a codeword including the main data and the parity data in a target page. The ECC decoder reads the codeword from the target page based on an address to generate a syndrome and corrects at least one error bit in the read codeword based on the syndrome by respectively applying different syndromes to a single bit error in the read codeword, adjacent bit errors and non-adjacent bit errors occurring in non-adjacent two memory cells in the target page. The ECC decoder generates the different syndromes based on a parity check matrix generated as a function of the primitive polynomial. The primitive polynomial has an alpha matrix as a solution belonging to a Galois field.

Memory controllers and memory systems including the same are disclosed. The memory controller is configured to control a memory module, the memory controller comprising: processing circuitry configured to: perform ECC decoding of a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome; determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome; and output a decode status flag indicative of the type of error.

The invention discloses an LDPC partial parallel encoder and encoding method under a DVB-S2 standard, and the encoder comprises an ROM control module which is used for selecting a matrix column weight according to an input code rate, controlling a counter to count to a corresponding ROM address, and selecting a corresponding storage unit at the same time, so as to generate a read address signal and a read enable signal of the corresponding ROM; the ROM storage module is used for reading corresponding parity check matrix information according to the input information of the ROM control module; the check calculation module is used for completing iterative calculation of an intermediate value variable according to the parity check matrix information read from the ROM storage module, calculating a check bit at the same time, and finally outputting the check bit to the de-encapsulation module; the packaging module is used for splicing the input 8-bit data into 360-bit data and outputting the 360-bit data to the ROM control module and the check calculation module; and the de-encapsulation module is used for disassembling the output data into 8-bit data so as to keep the bit width of the 8-bit data consistent with the bit width of the input data. The method has the advantages of low resource consumption and high throughput, and can be used for satellite communication.

A semiconductor memory device includes an array of memory cells, an on-chip error correction code (ECC) engine, a link ECC engine. The link ECC engine receives, in a write operation, a first codeword including first main data and first link parity data from a memory controller, generates a first syndrome including a plurality of syndrome bits based on the first codeword and a first parity check matrix based on the first ECC, generates a decoding status flag indicating whether a transmission error is detected in the first codeword using a property of the first syndrome based on regularity of the first parity check matrix while decoding the first syndrome, corrects an error bit of the first codeword based on the decoded first syndrome, and provides the first main data of the corrected first codeword to the on-chip ECC engine.

The invention discloses an enhanced security digital signature method, system and device based on QC-MDPC and dual Hash, and a storage medium, and relates to the technical field of quantum digital signatures, the method comprises the following steps: based on security requirements and computing resources, selecting parameters to construct a parity check matrix, a disturbance matrix and a reversible permutation matrix, and selecting a Hash function and a decoding algorithm; generating a private key and a public key; carrying out Hash calculation on the message document based on the generated private key, and carrying out operation and decoding operation to generate a digital signature; calculating based on the digital signature and the generated public key, and judging whether the signature is valid or not; according to the method, quantum attacks can be resisted, the security of financial transactions, medical data, Internet of Things equipment communication and government affair information systems can be guaranteed, information is ensured to be real and complete, resources are reasonably utilized, and security support is provided for multi-industry digital transformation.

An LDPC encoder is described with memory for storing a parity check matrix and a calculation unit to encode information bits into a codeword with reference to the parity check matrix. The parity check matrix includes an information part matrix and a parity part matrix. In the parity part matrix, Z*Z sub-matrices are sub-matrices, other than a zero matrix, and are arranged in each of the m rows and m columns. A sub-matrix is a scaled cyclic matrix obtained by shifting elements of an identity matrix by one to the left and multiplying the shifted elements by a scaling element. Except for the scaled cyclic matrix, the remaining sub-matrices are a zero matrix or an identity matrix, and the scaling element is an element allowing the parity part matrix to satisfy a full rank condition on a Galois field.

The application discloses a quasi-cyclic low-density parity-check code decoding method, system, device and medium, acquires a predetermined parity-check matrix; adjusts the parity-check matrix into a target operation matrix composed of a unit matrix and a displacement matrix, the dimensions of the unit matrix and the displacement matrix are both p x p; acquires a target codeword to be decoded corresponding to a current decoding recursion number; splits the target codeword into target sub-codewords with a length of p; in the target operation matrix, determines a target operation sub-matrix corresponding to each target sub-codeword; performs parallel operation on the target sub-codewords and the target operation sub-matrix to obtain a syndrome value of the target codeword; determines a current decoding result of the current decoding recursion number based on the syndrome value, and determines a target decoding result based on the current decoding result. In the application, parallel operation is performed on the corresponding target operation sub-matrix and the target sub-codeword, the operation efficiency of the syndrome value can be improved, and the operation efficiency of the entire decoding method is further improved.

The invention relates to a decoder (30) for decoding low density parity check code words (LDPC code). The decoder comprises at least one core (10) and a memory (20) in which a number NC of predefined configurations is stored. The core is adapted to be dynamically configured with any one of the NC predefined configurations stored in the memory in order to decode an LDPC code word using this configuration. The NC predefined configurations form a subgroup, in the strict sense, of the 5G LDPC configurations defined in the 3GPP TS 38.212 standard. Each configuration corresponds to a triplet of three parameters {K, R, Z}, and to a parity matrix constructed according to at least part of these parameters. K corresponds to a message size encoded by the LDPC code, Z corresponds to an expansion factor of the parity matrix, R corresponds to a coding rate of the LDPC code.Advantageously, the predefined NC configurations include different values ​​of the Z parameter. Figure for abstract: Fig. 5.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a low density parity check (LDPC) code may include a parity check matrix (PCM) with a lifted parity submatrix. The lifted parity submatrix may include an upper-triangular portion having non-zero diagonal elements, a high-degree column portion, an all-zero portion, and a remaining portion, resulting in improved encoding efficiency. In some aspects, a transmitter may encode, in a first encoding operation, the upper-triangular portion and the high-degree column portion, and the transmitter may encode, in a second encoding operation, the all-zero portion and the remaining portion of the lifted parity submatrix. The encoded lifted parity submatrix may be transmitted from the transmitter to a receiver in a PCM as part of an LDPC code. Additionally, a base graph PCM structure may be included in the remaining portion of the lifted parity submatrix. Numerous other aspects are described.

This invention relates to network coding technology and discloses a network coding method based on maximum rank distance code. The method includes: performing network coding on transmitted data to obtain coded data; performing linear addition and multiplication on the coded data to obtain coded data packets; using a preset parity check matrix to perform error detection and location on the coded data packets to obtain an error matrix; and performing rank error correction on the coded data packets based on the error matrix to obtain the original source data. This invention also provides a network coding apparatus, device, and medium based on maximum rank distance code. This invention can reduce the amount of redundant data transmitted in the transmission network and maintain low latency and high data recovery success rate even in complex network environments.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 3 / 4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 144 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.