21 results about "Parity-check matrix" patented technology

This invention relates to network coding technology and discloses a network coding method based on maximum rank distance code. The method includes: performing network coding on transmitted data to obtain coded data; performing linear addition and multiplication on the coded data to obtain coded data packets; using a preset parity check matrix to perform error detection and location on the coded data packets to obtain an error matrix; and performing rank error correction on the coded data packets based on the error matrix to obtain the original source data. This invention also provides a network coding apparatus, device, and medium based on maximum rank distance code. This invention can reduce the amount of redundant data transmitted in the transmission network and maintain low latency and high data recovery success rate even in complex network environments.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 3 / 4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 144 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

An apparatus may include a receiver and one or more processors. The receiver may receive log likelihood ratio (LLR) values corresponding to encoded data that is encoded using a low-density parity-check (LDPC) code. The one or more processors may identify a number of punctured parity bits corresponding to the encoded data, determine that the number of punctured parity bits is less than a threshold, and remove, from a first parity check matrix corresponding to the encoded data, one or more rows corresponding to the number of punctured parity bits to generate a second parity check matrix. The one or more processors may determine, using the LLR values and the second parity check matrix, that there is an error in the LLR values, and an LDPC decoder may decode, based at least on the determination, the LLR values to resolve the error.

This invention discloses a layered decoding method and apparatus for LDPC frames based on mutual information, relating to the field of digital signal transmission in the physical layer of wireless communication. The method includes the following steps: 1) Calculating the LLR value of a given codeword to be decoded, and performing Q-ratio specific-point quantization to maximize mutual information on the entire frame's LLR value; 2) Calculating the PP value of the Q-ratio specific-point quantized LLR value according to Bayes' formula; 3) Layering the PP values ​​of the LLR values ​​of the data to be decoded according to the coefficients of the parity check matrix H; 4) Calculating the information within the information node; 5) Performing parity check node update calculations according to the PMS decoding algorithm to obtain the information value outside the parity check node; 6) Updating the information node using the information value outside the parity check node; 7) Symbol decoding; 8) Calculating the syndrome according to H. If the result of the syndrome is 0 or the maximum number of iterations is reached, outputting the three-frame codeword result; otherwise, returning to step 3) for the next decoding iteration. This invention can effectively improve the decoding processing speed of each frame.

A decoder (30) for decoding low-density parity-check (LDPC) codewords. The decoder includes at least one core (10) and a memory (20) in which a number NC of predefined configurations are stored. The core is suitable for being dynamically configured with any one of the predefined configurations stored in the memory to decode an LDPC codeword using this configuration. The predefined configurations form a sub-group, in the strict sense, of 5G LDPC configurations defined in the 3GPP TS 38.212 standard. Each configuration corresponds to a triplet of three parameters {K, R, Z}, and to a parity matrix constructed according to at least a portion of these parameters. K is a message size encoded by the LDPC code, Z is an expansion factor of the parity matrix, and R is a code rate of the LDPC code.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 1 / 2 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 288 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

This invention relates to an LDPC code decoding method for BeiDou satellite navigation, comprising: Step S1, the receiving end accumulates the output values ​​corresponding to each bit in the codeword generated by the LDPC-CRC concatenated code encoding in the tracking loop to form a corresponding receiving vector; Step S2, performing bit-by-bit hard decision on the receiving vector to obtain a hard decision vector; Step S3, calculating the checksum of the hard decision using a parity check matrix transformed from a 64-element field to a 2-element field to determine whether the hard decision vector includes error bit information; Step S4, when error bit information appears in the hard decision vector, performing LDPC iterative decoding using a bit-flipping algorithm in the 2-element field, iteratively updating the error bits in the hard decision vector according to the error correction vector until the iteration termination condition is met, outputting the decoding result or discarding the receiving vector. This invention reduces decoding complexity and is suitable for practical applications.

A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that correct either errors in data prior to the data being input to the RAID process or residual errors from the RAID process. The ECC schemes can utilize parity bits generated using a parity matrix whose bit patterns have an amount of bits that can be used to identify a location of the memory system from which data corresponding to the respective bit pattern is read.

Certain example embodiments may relate to a 5G and / or 6G communication system for supporting higher data transmission rates than 4G communication systems such as LTE. A method performed by a transmitter in a communication system, which method may include: determining the number of input bits; determining a base matrix on the basis of the number of input bits; determining a lifting size (Z) on the basis of at least one of the number of input bits or the base matrix; determining a parity check matrix on the basis of at least one of the base matrix or the lifting size (Z); and performing encoding on the basis of the parity check matrix and the input bits. The size of the parity check matrix is Z×(k+1) Z, the last column block of the parity check matrix corresponds to parity bits, a Z×kZ column block of the parity check matrix corresponds to information word bits, all of modulo-Z values of differences in cyclic shift values corresponding to circulant permutation matrices constituting a Z×Z circulant matrix are different, and all of the circulant matrices corresponding to the information word bits are composed of three or more circulant permutation matrices.

An encoding method, comprising: on the basis of the number of rows of a parity check matrix (PCM), the number of columns of the PCM, a lifting value, the number of punctures in systematic columns of the PCM, and a code rate, determining a shortening sequence; on the basis of the length of the shortening sequence, the number of rows of the PCM, the number of columns of the PCM, and the lifting value, determining a bit sequence to be encoded; and on the basis of the shortening sequence, the PCM and the lifting value, encoding the bit sequence to be encoded, so as to obtain an encoded bit sequence.

Disclosed are an encoding method, a decoding method, a communication node and a storage medium. The encoding method comprises: determining a bit sequence to be encoded (110); determining a shortened sequence on the basis of the length of the bit sequence to be encoded and at least one of the following parameters: a lifting value and a code rate (120); and on the basis of a parity check matrix (PCM), the shortened sequence, a shortened systematic column size and the lifting value, encoding the bit sequence to be encoded, so as to obtain an encoded bit sequence (130).

The application discloses an encoding method, a decoding method, a communication node and a storage medium. The encoding method comprises the following steps: determining a parity check matrix PCM of a base graph BG from a first matrix set, the first matrix set comprising P matrices in a second matrix set and T-P matrices in a third matrix set, the matrices in the second matrix set being different from the matrices in the third matrix set, P being a natural number, T being a positive integer, and P < T; and encoding a to-be-encoded sequence according to the PCM of the BG and a lifting value of the PCM of the BG to obtain an encoded bit sequence.

A method for performing encoding on the basis of a parity check matrix of a low density parity check code according to the present embodiment comprises the steps of: generating a parity check matrix by a terminal, wherein the parity check matrix corresponds to a characteristic matrix, each component of the characteristic matrix corresponds to a shift index value determined through a modulo operation between a corresponding component in a basic matrix and Zc, which is a lifting value, and the basic matrix is a 42 x 52 matrix; and performing encoding of input data, by the terminal, using the parity check matrix, wherein the lifting value is associated with the length of the input data.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 5 / 6, a second parity check matrix corresponding to a first exponent matrix comprising 384 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

An illustrative decoder includes: a syndrome calculator, a location finder, and an error corrector. The syndrome calculator has an array of logic gates to obtain syndrome values as a product of a receive message vector and a parity check matrix, the syndrome values including at least a three ten-bit syndrome values S1, S2, and S3. The location finder derives a number of errors from the syndrome values, and uses a second array of logic gates to obtain two polynomial roots as a product of a syndrome value vector and a quadratic solution matrix when the number of errors is two, the quadratic solution matrix corresponding to a determination of a quadratic equation's trailing coefficient value s, a determination of the quadratic equation's roots, and a reversal of a variable substitution. The location finder further determines a bit index for each of the polynomial roots.

A decoding method includes: using a syndrome calculation check circuit to calculate a syndrome value of variable node Vi of a parity check matrix based on multiple input bits; rotating the syndrome value of variable node Vi into the direction of variable node Vi+1 to generate an estimated syndrome value of variable node Vi+1; rotating the syndrome value of variable node Vi−1 into the direction of variable node Vi−Δ to generate a rotated syndrome information; performing a weighted-sum calculation based on multiple rotated syndrome information to generate a flipping function value; and comparing the flipping function value with a flipping threshold to generate a flipping result; the syndrome calculation check circuit determines whether to modify / flip a specific bit according to the flipping result.

The present invention relates to a 5G or pre-5G communication system supporting a higher data transmission rate after a 4G communication system such as LTE. The present invention relates to a method and apparatus for encoding a channel in a communication or broadcasting system supporting a parity check matrix having various sizes. The method for encoding a channel includes determining a block size of a parity check matrix, reading a sequence for generating the parity check matrix, and transforming the sequence by applying previously defined operations to the sequence based on the determined block size.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 5 / 6 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 96 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

The present disclosure provides a decoding method and a memory system that decodes data and estimates a weighted check sum of the decoded data to determine whether the decoding is successful. The weighted check sum is computed based on a first set and a second set, the first set being associated with weights of high order nodes of an irregular parity check matrix, the second set being associated with weights of low order nodes of the irregular parity check matrix.

This application provides a method and apparatus for information transmission, which can reduce the decoding delay of information at the receiving end. The method includes: a first communication device obtaining a parity check matrix based on a first LDPC matrix, a first expansion factor, and shift values ​​corresponding to the first LDPC matrix; any first shift value in the set of first shift values ​​corresponding to a first element and any second shift value in the set of second shift values ​​corresponding to a second element satisfy at least one of a first condition or a second condition; the first element and the second element are two elements in the first LDPC matrix that are row-adjacent, column-adjacent, and both non-zero; the first LDPC matrix is ​​a base matrix or a matrix obtained by improving a base matrix; the first communication device sends information encoded using the parity check matrix to a second communication device; the second communication device decodes the received information to be decoded based on the parity check matrix to obtain a decoded bit sequence.

This application relates to the field of communication technology and discloses an encoding method, a decoding method, a communication device, and a communication system. Based on this method, since the positions of the parity bits in the second bit sequence are swapped, it is equivalent to swapping the corresponding columns of the parity check matrix. Therefore, the puncturing position during rate matching can be changed, which helps to improve decoding performance.