285 results about "Parity-check matrix" patented technology

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 3 / 4, a second parity check matrix corresponding to a first exponent matrix comprising 576 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 5 / 6, a second parity check matrix corresponding to a first exponent matrix comprising 384 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

The present technology relates to a transmission device, a transmission method, a reception device, and a reception method capable of ensuring good communication quality in data transmission using an LDPC code. The LDPC coding is performed on the basis of the parity check matrix of the LDPC code with the code length N of 1224 or 1152 bits and the coding rate r of 144 / 1224 or 144 / 1152. The parity check matrix includes an A matrix of M1 rows and K columns represented by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure of M1 rows and M1 columns, a Z matrix which is a zero matrix of M1 rows and N−K−M1 columns, a C matrix of N−K−M1 rows and K+M1 columns, and a D matrix which is an identity matrix of N−K−M1 rows and N−K−M1 columns. The A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing the positions of the elements of 1 of the A matrix and the C matrix for every 36 columns, and is a predetermined table. The present technology can be applied to, for example, data transmission using an LDPC code.

The invention provides an optical-electric hybrid ultra-low time delay communication method and system, and relates to the technical field of communication, and the method comprises the steps: outputting a global synchronous clock signal with clock jitter less than 1ppm, dynamically dividing micro time slot resources in an orthogonal frequency division multiplexing symbol period, and generating a dynamically adjusted micro time slot resource distribution result; calculating an optimal phase offset matrix of the metasurface intelligent reflecting surface through a depth deterministic strategy gradient algorithm to obtain an optimized electromagnetic wave propagation path; generating a global optimization check matrix by aggregating the locally trained lightweight error correction model gradient of each node to obtain a compensated data stream; and constructing a causal graph model dynamic pruning high-entropy path to minimize causal entropy, through multi-agent reinforcement learning, taking time delay-energy efficiency as a game target to decide an optimal modulation order and a subcarrier switching strategy, and obtaining an optimized stable communication link. According to the invention, high-reliability and low-delay communication basic support is provided for high-precision intelligent manufacturing.

Techniques are disclosed for reducing overhead during hybrid automatic repeat request (HARQ) operations performed by a user equipment (UE) during wireless communication. The UE receives a message over the wireless network and obtains a parity check matrix (PCM) associated with a received message. Rows of the PCM are assigned to respective groups of a plurality of groups, where the respective groups have corresponding one or more parity checks as determined by the PCM. The UE generates a feedback message including a plurality of bits, wherein an individual bit of the plurality of bits indicates whether a corresponding respective group of the plurality of groups include one or more unsatisfied parity checks. The UE then transmits the feedback message to a base station of the wireless network.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 2 / 3, a second parity check matrix corresponding to a first exponent matrix comprising 768 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 1 / 2, a second parity check matrix corresponding to a first exponent matrix comprising 1152 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

The invention belongs to the technical field of communication, and particularly relates to a multiplication active code decoding method based on an SO-ORBGRAND decoder. The SO-ORBGRAND decoder outputs soft information by calculating a correct posterior probability of a conjecture code word sequence, and high-performance decoding is realized through soft information exchange and optimization processing between the row decoder and the column decoder. In the iteration process, a method for judging the validity of the code word through the check matrix is designed by utilizing the polarization characteristic of the multiplication active code, so that the iteration is supported to jump out in advance to reduce the complexity. The invention provides a multiplication active code decoding algorithm based on an SO-ORBGRAND decoder, and compared with various non-system multiplication active code decoding algorithms and the performance of traditional long-code polarization codes, the method has remarkable advantages in error correction performance; a method for judging the validity of the code word through the check matrix by utilizing the polarization characteristic design of the multiplication positive code is provided, the complexity is reduced while the judgment success rate is improved, and the implementation overhead is reduced.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 1 / 2 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 288 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

In an aspect, digital communication coding methods (or simply coding methods) are provided, said methods comprising providing families of quasi-cyclic low-density parity check, LDPC, codes each represented by a single equation. Said single equation is derived from a geometry whose nature implies good error correcting properties for each of the LDPC codes and allows quasi-cyclic parity check matrices to be constructed for geometric LDPC codes of exceedingly long length, up to and exceeding four hundred thousand bits. The construction of such check matrices is not possible by any other known method. The LDPC codes have different lengths and different rates and the families of LDPC codes are provided with a guarantee of minimum distance. The geometric and quasi-cyclic properties of the LDPC codes allow low complexity decoding with very low frame error rates. Systems, computing systems and computer programs suitable to perform such coding methods are also provided.

Methods, systems, and devices for wireless communication are described to support replacing values of one or more information bit vectors with one or more corresponding sets of parity bits. A first wireless device may replace an information bit vector with a parity bit vector, using a set of information bits of the information bit vector and based on a parity check matrix, which may result in generating the set of information bits at an information bit vector corresponding to a parity bit column of the parity check matrix, during encoding. The first wireless device may perform a transmission to a second wireless device, which may receive the transmission, decode the set of information bits to the information bit vector corresponding to the parity bit column. The second wireless device may replace other bit estimates of a vector corresponding to an information bit column with the set of information bits.

The embodiment of the invention provides a coding and decoding method and device and a storage medium, relates to the technical field of communication, and can reduce the storage space requirement of coding. The method comprises the steps that a parity check matrix is determined, the dimension of the parity check matrix is determined based on the dimension of a binary extension matrix, the binary extension matrix is obtained by hashing an index matrix based on a lifting factor, and the lifting factor is determined based on the order of a binary basic matrix, an information bit sequence and a non-binary low-density parity check code NB-LDPC code; and according to the parity check matrix or a generation matrix corresponding to the parity check matrix, performing NB-LDPC coding on the information bit sequence to obtain a coding sequence.

The invention discloses a bit flipping decoding method and device for a low-density parity check code and a related medium. The method comprises the following steps of: 1, setting a target parameter; step 2, performing calculation based on the original code word and the check matrix to obtain a syndrome, and if the syndrome is judged to meet a first preset condition, entering step 3; 3, calculating to obtain an energy value of a corresponding bit by using an exclusive-or result between the original code word and the overlapped code word and a syndrome; 4, when the number of iterations is larger than the number of predicted effective times, it is judged that the energy value meets a second preset condition, and the energy value is updated to be the overturning threshold value; 5, performing flipping on the bits of which the energy values are greater than or equal to the flipping threshold value; and step 6, repeating the step 2 to the step 5 until the syndrome is equal to a preset value or the number of iterations reaches the maximum number of iterations, and outputting a decoding result. According to the method, the step 2 to the step 5 are repeated, so that the decoding speed can be improved and the calculation complexity can be reduced while the strong error correction capability is ensured.

Devices, systems, and methods for improving performance of an iterative decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, performing, on the noisy codeword for a first number of iterations, a message passing algorithm between a plurality of variable nodes and a plurality of check nodes that represent a parity matrix of the LDPC code, assigning, based on comparing an asymmetric ratio to a threshold, a set of asymmetric LLRs to a set of LLRs (that were initialized using symmetric LLRs) used in the message passing algorithm, and determining, subsequent to performing the message passing algorithm on the noisy codeword for a second number of iterations, a candidate version of the transmitted codeword.

Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.

An LDPC encoder is described with memory for storing a parity check matrix and a calculation unit to encode information bits into a codeword with reference to the parity check matrix. The parity check matrix includes an information part matrix and a parity part matrix. In the parity part matrix, Z*Z sub-matrices are sub-matrices, other than a zero matrix, and are arranged in each of the m rows and m columns. A sub-matrix is a scaled cyclic matrix obtained by shifting elements of an identity matrix by one to the left and multiplying the shifted elements by a scaling element. Except for the scaled cyclic matrix, the remaining sub-matrices are a zero matrix or an identity matrix, and the scaling element is an element allowing the parity part matrix to satisfy a full rank condition on a Galois field.

An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.

Methods, systems, and devices for host error control matrix are described. A host device may implement a parity check matrix for generating error control information with a relatively low likelihood that a multi-bit error in a codeword associated with the error control information is mistaken for a single-bit error. The host device may implement a parity check matrix patterned such that when the error control information is generated, there is a relatively low likelihood that an error code resulting from a comparison of the error control information will yield an indication of a single-bit error when a multi-bit error occurs. For example, the host device may compare first error control information generated for a codeword and transmitted to a memory device with second error control information generated after receiving the codeword from the memory device, and generate an error code using the results of the comparison.

Provided are an encoding method and apparatus, a decoding method and apparatus, and a storage medium. The encoding method comprises: determining a parity check matrix, wherein the dimension of the parity check matrix is determined on the basis of the dimension of a binary extended matrix, the binary extended matrix is obtained by hashing an exponential matrix on the basis of a lifting factor, and the lifting factor is determined on the basis of a binary fundamental matrix, an information bit sequence, and the order of a non-binary low density parity check code (NB-LDPC); and performing NB-LDPC encoding on the information bit sequence on the basis of the parity check matrix or a generator matrix corresponding to the parity check matrix, to obtain an encoding sequence.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 5 / 6 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 96 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

The disclosure generally relates to improvements of a log-likelihood ratios (LLRs) memory structure and memory capacity of a decoding hardware (also referred to as a decoder) in decoding a sequence of codewords encoded with a low-density parity-check (LDPC) code (e.g. a quasi-cyclic (QC) LDPC code). Further, the disclosure relates to the optimization of a processing schedule of a parity check matrix (PCM) describing the LDPC code so as to reduce or minimize the number of patch LLRs that need to be (simultaneously) stored in an LLR memory of a decoder.

The invention discloses an LDPC encoder based on a DVB-S2 protocol, a transmitting terminal and a test platform, and the LDPC encoder comprises an information bit matrix multi-port input RAM which is used for storing input information bits; the check matrix multi-port ROM is used for storing a check matrix; the accumulative sum matrix RAM is used for storing the accumulative sum matrix generated by the accumulative sum matrix calculation module; the check bit matrix RAM is used for storing a check bit matrix; the check matrix calculation module reads a check matrix from the check matrix multi-port ROM, and the check matrix is converted into a cyclic shift matrix through preprocessing; the accumulative sum matrix calculation module is used for reading information bits from the information bit matrix multi-port input RAM, executing loop right shift and accumulative operation, and calculating to obtain an accumulative sum matrix; and the check bit matrix initialization module is used for calculating a check bit matrix initialization vector according to a calculation result of the accumulation and matrix calculation module.

The disclosure generally relates to improvements of a log-likelihood ratios (LLRs) memory structure and memory capacity of a decoding hardware (also referred to as a decoder) in decoding a sequence of codewords encoded with a low-density parity-check (LDPC) code (e.g. a quasi-cyclic (QC) LDPC code). Further, the disclosure relates to the optimization of a processing schedule of a parity check matrix (PCM) describing the LDPC code so as to reduce or minimize the number of patch LLRs that need to be (simultaneously) stored in an LLR memory of a decoder.

The invention discloses a flash memory error correction method and system based on adaptive learning, and relates to the technical field of data storage.The flash memory error correction method comprises the steps that flash memory voltage distribution and error code positions are collected in real time, and dynamic feature vectors are generated in combination with environmental parameters; constructing a hypergraph neural network based on the dynamic feature vectors, obtaining error propagation risk scores of the storage areas, and generating a priority list; based on the priority list, the check connectivity of the low-density parity check matrix is adjusted through matrix reconstruction, and a sparse check matrix is formed; an initialization parameter and a solution vector are generated based on the decoder ready state signal, sampling iteration and threshold judgment are carried out, and a decoding result is output; and when decoding fails, performing multi-device parameter updating by adopting aggregation optimization, and performing decoding again to output final correction data. According to the method, collaborative error correction is optimized through multi-device parameter aggregation, so that the limitation of single-device decoding is solved, the global error correction performance is optimized, and the fault-tolerant capability is enhanced.

There is provided a decoding apparatus for decoding a low density parity check (LDPC) code, wherein the decoding apparatus includes a memory a memory configured to store a scheduling table indicating a desired processing order of a plurality of rows included in a parity check matrix and a plurality of columns included in each of the rows of the parity check matrix, and processing circuitry configured to decode the LDPC code based on the scheduling table, the decoding including performing processing on at least one column included in a second scheduled row of the parity check matrix before processing of all columns included in a first scheduled row of the parity check matrix has been completed.

The invention discloses a high-code-rate QC-LDPC check matrix construction method and device for NAND, a medium and a product, and relates to the technical field of channel coding, and the method comprises the steps: firstly, generating an initial check matrix which is uniform in row weight distribution and is free of a four-ring structure; secondly, traversing a preset shift value range for each non-zero item of the initial check matrix, and selecting a shift value which enables the number of six rings to be minimum to generate an intermediate check matrix; and finally, based on the number of the six rings in which each non-zero item participates in the intermediate check matrix, sequentially eliminating the non-zero items participating in the most six rings to obtain a target check matrix. According to the method, the four-ring, six-ring and global balance is progressively optimized, so that the error correction performance of the check matrix is remarkably improved, the decoding time delay is reduced, and the reliability requirement of a high-bit-rate NAND flash memory is met.

A memory device and method for a partial checksum calculation using a sub-matrix with flexible media coverage inside of a memory device (i.e., NAND) of a memory system. The memory device includes: a plurality of memory cells; a control circuit configured to read a codeword sequence from the plurality of memory cells, and determine a sub-matrix including multiple non-zero circulants selected from particular matrix rows of a parity check matrix used in a controller of the memory system, the multiple non-zero circulants including non-zero row circulants for each matrix row; and a partial checksum calculator configured to perform a partial checksum calculation on a syndrome sequence based on the codeword sequence and the sub-matrix.

A transmitter is provided that shapes uniformly-distributed bits into a non-uniformly distributed bits according to a parity check matrix of a linear code such that a product of the parity check matrix and the non-uniformly distributed bits equals the uniformly-distributed bits. Similarly, receiver is provided that recovers the uniformly-distributed bits from the non-uniformly distributed bits through a multiplication of the non-uniformly-distributed bits with the parity check matrix.

Transformer neural network based decoder for decoding Quantum Error Correction Codes (QECC), comprising, an input layer, a plurality of decoding layers, and an output layer. The input layer is adapted to receive initial noise estimation computed by a noise estimator for noise injected to syndrome bits of codewords encoded using QECC and transmitted over transmission channel(s) subject to interference, and create embeddings for the syndrome bits. The decoding layers adapted to compute an estimated logical operator matrix of each codeword, each comprises a self-attention layer constructed according to a mask indicative of a relation between the embeddings derived from a parity-check matrix of the error correction code. The plurality of decoding layers are trained using a combined loss function directed to minimize LER, BER, and error rate of the noise estimator. The output layer is adapted to produce a vector representing predicted soft error of the codeword's logical operator matrix.

The invention relates to an eight-ring QC-LDPC (Quasi-Cyclic Low Density Parity Check) code construction method based on a subtraction construction search algorithm. According to the method, a first row is fixed by using a Golomb Ruler sequence, the last two rows are obtained by using a search algorithm constructed based on subtraction to form an index matrix meeting a condition without 4 and 6 rings, and finally, the index matrix is correspondingly expanded to obtain a parity check matrix of the index matrix, so that four rings and six rings do not exist in a Tanner graph of the check matrix, the required storage space is small, and hardware implementation is easy. A simulation result shows that compared with an SS-QC-LDPC code, a DDS-QC-LDPC code, a GR-QC-LDPC code, an LETS-QC-LDPC code and a GRS-QC-LDPC code which have the same code rate and code length, the SC-QC-LDPC code constructed by the method has the advantages that the net coding gain is improved to a certain degree, and the constructed SC-QC-LDPC code has better waterfall region performance in a high signal-to-noise ratio region and has no obvious error leveling phenomenon.