21results about "Error coding/decoding sychronisation" patented technology

A forward error correction (FEC) synchronization method includes establishing a link between a source terminal and a sink terminal, transmitting a tagged symbol periodically from the source terminal to the sink terminal, identifying the tagged symbol by the sink terminal after the tagged symbol is received by the sink terminal, collecting a plurality of symbols transmitted from the source terminal for generating a plurality of FEC blocks received by the sink terminal after the tagged symbol is successfully identified, and synchronizing the plurality of FEC blocks between the source terminal and the sink terminal according to the tagged symbol. The tagged symbol includes predefined patterns.

A system includes a communication link coupled to an encoder and a decoder. The communication link includes a set of wires. The encoder is configured to encode a first block of input data to form a first codeword and to encode a second block of the input data to form a second codeword. The encoder is configured to generate a boundary bit based on at least one bit from each of the first codeword and the second codeword, and to send encoded data via the communication link. The encoded data includes a first set of bit values of the first codeword, a second set of bit values of the second codeword, and the boundary bit, which is located between the first set of bit values and the second set of bit values. The decoder is configured to decode the encoded data to generate a representation of the input data.

A method and apparatus are provided for performing consistency testing for a Bose-Chaudhuri-Hocquenghem (BCH) error corrected first sub-frame of navigation message broadcast from a satellite of a GNSS. Consistency testing is performed by comparing BCH encoded portion(s)s of data symbols with elements of look up table(s) to see if such portions are similar to element(s) of the look up table(s).

A method for link transition in a USB device includes transmitting a plurality of first RS-FEC blocks by a first transmitter (S502), receiving an UNBOND set by a receiver (S504), waking up a second transmitter by a LASM when the receiver receives the UNBOND set (S506), transmitting a training sequence by the second transmitter (S508), transmitting a specific pattern sequence by the second transmitter after finishing transmitting the training sequence (S510), determining whether a current RS-FEC block to be transmitted by the first transmitter is a DESKEW block (S512), stopping transmitting the specific pattern sequence if the current RS-FEC block is determined to be the DESKEW block (S514), and transmitting a plurality of second RS-FEC blocks by the first transmitter and the second transmitter (S516).

Communication terminals, systems and methods are disclosed herein, In an embodiment, a method for improving communication throughput when experiencing periodic blockages includes generating at least one outer code block including a plurality of sync data elements, writing the sync data elements from the at least one outer code block to a same column of at least one interleaver including a plurality of rows and a plurality of columns, and writing additional data elements from the outer code block to other columns of the at least one interleaver.

A forward error correction (FEC) synchronization method includes establishing a link between a source terminal and a sink terminal, transmitting a tagged symbol periodically from the source terminal to the sink terminal, identifying the tagged symbol by the sink terminal after the tagged symbol is received by the sink terminal, collecting a plurality of symbols transmitted from the source terminal for generating a plurality of FEC blocks received by the sink terminal after the tagged symbol is successfully identified, and synchronizing the plurality of FEC blocks between the source terminal and the sink terminal according to the tagged symbol. The tagged symbol includes predefined patterns.

A method of operating a digital radio receiver (2) is provided. The method comprises: a) receiving an incoming radio signal comprising an incoming symbol sequence (102); b) selecting a portion of the incoming symbol sequence (102); c) determining a first error between the selected portion of the incoming symbol sequence (102) and a first predetermined symbol sequence (11) using a difference metric; d) determining, using the difference metric, a set of second errors between the selected portion of the incoming symbol sequence (102) and a respective set of second predetermined symbol sequences (13), each formed by prepending different length portions of a predetermined preamble symbol sequence (104) to a beginning of the first predetermined symbol sequence (11); and e) determining a minimum error from the first error and the set of second errors. If the first error is not the minimum error, a different portion of the incoming symbol sequence (102) is selected and steps c) to e) are repeated. If the first error is the minimum error, a following portion of the incoming symbol sequence (102) is decoded to produce a data payload.

The invention discloses a bit field effective information retrieval method, a storage medium and a device, and the method comprises the following steps: S1, carrying out bit streaming on digital field receiving information, and unifying the digital field receiving information into a binary bit stream; s2, obtaining convolution feature values of the first array and the synchronous code array; s3, acquiring a synchronous code of digital domain receiving information from the binary bit stream, performing self-correlation processing to obtain a self-correlation value, and generating a second array; s4, multiplying the second array by the first array bit by bit, counting an accumulation result, and comparing the accumulation result with the convolution characteristic value of the synchronous code array; s5, determining the position of a synchronization head; and S6, acquiring effective information of the bit field from the position of the synchronization head. According to the method, bit domain processing can be carried out on the digital domain synchronization head, feature code calculation is carried out through the bit domain, then full-bit-domain searching is carried out through the feature code, condition judgment of accurate judgment is achieved, the retrieval efficiency is improved, and the misjudgment probability is reduced.

An arrangement for providing privacy in a communication network. In the arrangement privacy is applied in two steps, wherein the first part comprises using a Hamming code privatizing data in a network. After applying the Hamming code, it is determined how much additional differential privacy is required for fully privatizing the information. Then the information is fully privatized using a differential privacy method.

An arrangement for providing privacy in a 3G communication network. In the arrangement privacy is applied in two steps, wherein the first part comprises using a Hamming code, ordered such that adjace

A CAN bit stream sampling device for a controller area network (CAN) controller, the device configured to receive a bit stream from a CAN transceiver, the device configured to: detect a rising edge in the bit stream; separately detect a falling edge in the bit stream; and generate a recovered non-return-to-zero coded bit stream based on at least the detected falling edge and the detected rising edge.

Systems and techniques for conditionally processing compute resources are described herein. A data payload is received. Parity data is removed from the data payload to generate a codeword dataset. Frames are identified in the codeword dataset. Headers of the frames are evaluated using a conditional decoding map. The frames are marked based on a destination in the headers found in the conditional decoding map. A set of target codewords are identified from the frames based on the marking. Remaining frames of the frames outside the set of target codewords are discarded. The set of target codewords is transmitted to a buffer of a conditional decoder. Codewords from the buffer are decoded using the conditional decoder.

A wireless communications device includes a receiver having a phase detector configured to extract frequency offset and provide a corresponding error signal generated based on a baseband version of a received radio frequency signal and an expected transmitted data signal. The receiver has a phase-locked loop configured to generate an error correction signal based on a phase of the error signal and a predicted instantaneous phase of the error signal. The receiver has a correction circuit configured to provide a corrected baseband version of the received radio frequency signal based on the baseband version of the received radio frequency signal and the error correction signal. The receiver may have a re-encoding-based processing circuit configured to provide the expected transmitted data signal based on a preliminarily decoded symbol.

The application provides an adaptive SerDes architecture and power consumption adjustment method based on FEC, which comprises an analog front end, an analog-to-digital converter, a digital signal processor, a sending side forward error correction encoder, a receiving side forward error correction decoder, a microprogram controller and the like, wherein the sending side forward error correction encoder encodes data by adding an additional error correction code to the transmission data; the receiving side forward error correction decoder decodes the transmission data, identifies and corrects errors occurring in the data transmission process through the added error correction code; the microprogram controller is used for real-time monitoring of the sending side forward error correction encoder and the receiving side forward error correction decoder, and reading back the log information of the sending side forward error correction encoder and the receiving side forward error correction decoder. The technical scheme of the application can adaptively balance the signal quality and power consumption of the SerDes, and has good applicability in different product scenarios and different PVT states of chips.

This disclosure describes systems, methods, and devices related to over-puncture mitigation. A device may generate a frame comprising a payload having a payload size associated with a number of bits. The device may determine a low-density parity-check (LDPC) codeword size based on the payload size. The device may calculate a number of codewords based on the payload size. The device may calculate a number of shortening bits and a number of LDPC padding bits based on the number of codewords. The device may calculate a number of orthogonal frequency division multiplexing (OFDM) symbols for containing the number of codewords. The device may cause to send the frame with the number of OFDM symbols to a station device.

Communication terminals, systems and methods are disclosed herein. In an embodiment, a method for improving communication throughput when experiencing periodic blockages includes generating at least one outer code block including a plurality of sync data elements, writing the sync data elements from the at least one outer code block to a same column of at least one interleaver including a plurality of rows and a plurality of columns, and writing additional data elements from the outer code block to other columns of the at least one interleaver.

Systems and techniques for are described herein. A data payload is received. Parity data is removed from the data payload to generate a codeword dataset. Frames are identified in the codeword dataset. Headers of the frames are evaluated using a conditional decoding map. The frames are marked based on a destination in the headers found in the conditional decoding map. A set of target codewords are identified from the frames based on the marking. Remaining frames of the frames outside the set of target codewords are discarded. The set of target codewords is transmitted to a buffer of a conditional decoder. Codewords from the buffer are decoded using the conditional decoder.

A system includes a communication link coupled to an encoder and a decoder. The communication link includes a set of wires. The encoder is configured to encode a first block of input data to form a first codeword and to encode a second block of the input data to form a second codeword. The encoder is configured to generate a boundary bit based on at least one bit from each of the first codeword and the second codeword, and to send encoded data via the communication link. The encoded data includes a first set of bit values of the first codeword, a second set of bit values of the second codeword, and the boundary bit, which is located between the first set of bit values and the second set of bit values. The decoder is configured to decode the encoded data to generate a representation of the input data.