66results about How to "Reduce hardware size" patented technology

Modular or cartridge-type membrane units utilize hollow, cylindrical tubular housings or receivers to house strings of removable membrane modules (elements) and normally comprise arrays of pipes that act as membrane module housings. A pseudo header for fluidly interconnecting the array of pipes reduces weight and cost. The pseudo header may comprise portions that are buried within skid components such as the toe bar. An internal low friction coating permits a larger number of membrane cartridges to be utilized in any cylindrical tubular membrane housing. A center feed pseudo header permits flow in two directions through the tubular membrane housing to double hydraulic capacity.

A data transmission method and a data transmission system not requiring a large delay unit for multiplexing and composition and capable of reducing the hardware scale, wherein when transmitting data among multiple points from a plurality of terminals arranged in a network, when the data at multiple points are transmitted to the terminals, in the network, identical packets are added different time stamps in accordance with the transmission delays, whereby the data shifted in accordance with the transmission delays are transmitted.

A subcarrier allocating apparatus allocating data to be transmitted to a plurality of orthogonal subcarriers in an orthogonal frequency division multiplexing (OFDM) system, the apparatus including: a logical index generator (142) generating a logical index for allocating a data subcarrier to a physical index, the logical index being included with only data subcarriers and the physical index indicating a location of a substantial subcarrier within a symbol; an intermediate index converter (144) converting the logical index into an intermediate index by performing a given operation on the generated logical index and a pilot location constant; and a physical index converter (146) converting the intermediate index into a physical index based on the number of data subcarriers on the left and right sides of a null subcarrier for insertion of a guard interval formed by the null subcarrier.

The invention discloses an underwater sub-wavelength resolution ratio three-dimensional imaging method. The underwater sub-wavelength resolution ratio three-dimensional imaging method includes the following steps: (1) a sound signal is emitted; (2) acoustic lens wave beams are formed; (3) the sound signal is received and adjusted; (4) an image is processed and displayed. A two dimensional datum is obtained according to an imaging rule of an acoustic lens, a distance datum is obtained by utilizing an emission time and a receiving time, and a three dimensional underwater sound datum is obtained by combining with an electric signal received by a underwater sound sensor. The three dimensional underwater sound image datum undergoes image enhancement and image segmentation and a three dimensional image of a target is achieved by use of an open-sourcing visualization program library visualization toolkit (VTK). A reflected sound wave is focused through the acoustic lens and forms the wave beam. Hardware circuits of a normal imaging system are greatly reduced. A sub-wavelength image is achieved due to the characteristic of negative refraction of a phonon crystal. The novel underwater sound sensor with a mesoscopic pressure resistance is utilized, the underwater sound sensor responds to an underwater sound signal well, and a faint underwater signal can be effectively transformed.

The invention relates to a control cycle synchronizer of a triple-modular redundancy fault-tolerant computer, which comprises single machines A, B and C, a voting circuit and control cycle interruption management modules arranged in the A, B and C, wherein the single machines A, B and C simultaneously input respective control cycle clocks to the voting circuit; the voting circuit uses an internal voting unit and wired-and logic to carry out a 2-out-of-3 vote on the input control cycles so as to produce a unified control cycle clock; the single machines A, B and C use the unified control cycle clock to response to control cycle interruption; and the control cycle interruption management modules turn off the control cycle interruption after the control cycle interruption is started, and turn on the control cycle interruption of the single machines A, B and C again after a certain time delay. By using the simple circuit design scheme, in the invention, the high-reliability control cycle synchronization control on the triple-modular redundancy fault-tolerant computer is realized, and all simplex fault modes including normally-0 or normally-1 faults as well as clock drift faults (including high-frequency oscillation and frequency downshift) can be tolerated.

A wireless communication apparatus includes a plurality of antenna branches for transmitting and receiving a wireless communication signal, a calibration coefficient calculator for calculating a calibration coefficient for each frequency band, the calibration coefficient correcting an imbalance in phase and amplitude existing between the antenna branches, a coefficient storage memory for storing the calibration coefficient of each frequency band, a calibration coefficient reader for reading the calibration coefficient of a frequency band of one of a transmission signal and a reception signal as a target to be calibrated, a calibration coefficient interpolator for interpolating a calibration coefficient of the frequency band if the coefficient storage memory stores no corresponding calibration coefficient of the frequency band, and a calibration coefficient multiplier for multiplying one of the transmission signal and the reception signal by one of the read calibration coefficient and the interpolated calibration coefficient.

Provided is a method for transforming data using a look-up table. The method includes the steps of: (a) mapping preprocessed input binary data to a constellation diagram divided into four quadrants to output a first complex number; (b) performing addition / subtraction operations between real numbers and between imaginary numbers with respect to the first complex number and a second complex number; and (c) reading a fourth complex from a look-up table in response to the first complex number, the second complex number and a third complex number, the look-up table outputting the fourth complex by performing a subtraction operation on multiplication results between real numbers and between imaginary numbers and an addition operation on multiplication results between the real numbers and the imaginary numbers with respect to the result value of the step (b) and the third complex number. Accordingly, it is possible to reduce the hardware size at the time of IFFT / FFT design and to provide a high-speed, low-power operation.

A multiplication apparatus including a multiplier and multiplicand extractor for dividing the multiplicand into partial multiplicands and dividing the multiplier into partial multipliers, and for generating partial input pairs by combining the partial multiplicands with the partial multipliers, and a multiplication executor including identical partial multiplication modules for receiving the partial input pairs and outputting partial carries and partial products. The apparatus further includes an output generator for combining the partial carries with the partial products according to the execution instruction to generate a final output. For simple multiplications, each of the partial multiplication modules can pass data to and from an adjacent partial multiplication module to calculate the partial carry and the partial product, and pass bits exceeding its own multiplication coverage.

An image sensor test apparatus that emits light to a light receiving surface of an image sensor (DUT) and inputs and outputs electrical signals from a contact part to input and output terminals of the image sensor so as to test the image sensor (DUT) for optical characteristics, which captures an image of the image sensor (DUT) in the state held by a contact arm (315) by a first camera (326), recognizes a relative position of the image sensor (DUT) with respect to the contact part by image processing, adds a precalculated amount of deviation of an optical axis of the image sensor (DUT) with respect to an optical axis of a light source to that relative position to calculate an amount of alignment of the image sensor (DUT), drives a drive unit (322) based on this, and moves a holding side arm (317) abutting against a movable stage (321) with a lock-and L-free mechanism (318) in a free state.

Disclosed herein is a stereo camera module. The stereo camera module according to an exemplary embodiment of the present invention includes a sensor unit having heterogeneous sensors having different number of pixels and a lens unit adjusting an angle of view of the sensor unit.

An LDPC encoder (304) includes a timing adjustment circuit (326) for performing timing adjustment on main data and outputting to a writing circuit (334), a parity generation circuit (328) for performing LDPC encoding on input signal series, generating the parity data, and outputting to the writing circuit (334), and the writing circuit (334) for sequentially receiving the main data and the parity data, and outputting to the storage apparatus via a write pre-compensation unit (305), a driver (306), and the like.

A transmission, including a gear-train and an outer housing enclosing the gear-train, the outer housing including a torque reacting joint coupling a first section of the transmission to a second section of the outer housing, the torque reacting joint including mating indents between the first and second sections.

The invention belongs to the technical field of application of solar power generation grid-connection self-use power supply, and in particular relates to a structure and a method for a solar power grid-connection self-use multi-functional system. In order to endow a solar power generation system with functions of power generation, grid connection and self-use, a technical scheme is changed through a direct current power regulating circuit, a system allocating control circuit, an electronic control switch group and a power on-off controllers, wherein according to technical scheme, the system structure is that solar power generation systems can supply power to alternating loads of users only through storage batteries and inverters, and the internal power path is single. Therefore, when the multi-purpose solar power generation power supply system which can generate power, connect the grids and realize self-use is constructed, the system hardware scale is reduced, the structure of the system and formation of the internal power path are optimized, power consumption and resource waste are reduced, the using efficiency of solar power is greatly improved, and return on investment is greatly increased.

The invention is suitable for the technical field of vehicle-mounted radars, and provides a radar detection method, device and equipment for vehicle, and a storage medium. The method comprises the steps: starting a 77GHz millimeter-wave radar sensor on a vehicle of a user when a radar detection request is detected; collecting the surrounding information of the vehicle of the user through the 77GHzmillimeter-wave radar sensor, and transmitting the drive information of the vehicle of the user to a surrounding vehicle; processing the surrounding information of the vehicle of the user through a radar signal processor on the vehicle of the user, so as to obtain the relative distance and relative speed of the vehicle of the user and a surrounding target object; giving a driving prompt to the user according to the relative distance and relative speed, thereby effectively reducing the hardware size of the radar detection device, and improving the convenience of radar detection of the vehicle.

An image recognition apparatus determines whether an image of a pedestrian is captured in a frame of video data captured by a vehicle mounted camera. A pre-processing unit determines a detection block from within a frame, and cuts out block image data corresponding to the detection block from the frame. Block data with a predetermined size that is smaller than the size of the detection block is created from the block image data. A neuro calculation unit executes neuro calculation on the block data, and calculates an output synapse. A post-processing unit determines whether a pedestrian exists within the detection block on the basis of the output synapse. When a pedestrian is detected, the post-processing unit creates result data, which is obtained by superimposing the detection block within which the pedestrian was detected onto the frame.

A cache memory of the present invention includes: for each cache entry, way 0 to way 3 which hold use flags U indicating whether or not the use flags U have been accessed; and a control unit which: updates, when a cache entry is hit, a use flag U corresponding to the hit cache entry so that the use flag U indicates that the cache entry has been accessed; and reset, in the case where all other use flags in the same set indicates that the cache entries have been accessed herein, the all other use flags so that the use flags indicate that the cache entries have not been accessed; and select a cache entry to be replaced from among the cache entries corresponding to the use flags indicating that the cache entries have not been accessed.

Disclosed are a sort processing method and a sort processing apparatus, which, in a computer or data processing, compare magnitudes of pieces of data input by hardware, rearrange the pieces of data in accordance with a predetermined order and output the rearranged pieces of data. The sort processing apparatus includes first basic cells, each of which is composed of a first data comparator for comparing magnitudes of pieces of input data with each other and for outputting a first select signal, and a first data selector for rearranging said compared pieces of input data in a magnitude order on the basis of said first select signal, wherein said first basic cells having the same number as that of combinations of pieces of input data to be compared are arranged in a pipeline configuration.

The disclosure relates to an unmanned aerial vehicle, a motor control device and method for controlling the same. The motor control method includes: acquiring current attitude information of a load, target attitude information of the load and current operation parameter information of one or more motors on the load, and obtaining control information for controlling the one or more motors in accordance with the acquired information above; transmitting the control information to a shared memory for storage; reading the control information from the shared memory, and controlling operation of the one or more motors in accordance with the control information. In one embodiment, the motor control device does not require cable or PCB wiring to connect a main control unit and an execution unit, reducing the size of hardware. Moreover, with the shared memory, the speed and stability of data interaction between the main control unit and the execution unit may be improved.

In an OFDM receiver, one of a plurality of antennas is selected based on a ratio X of two moving average integration values (first moving average integration value and second moving average integration value) that are calculated from a non-delay symbol and a delay symbol. It could be said that the second moving average integration value represents excessive false information (that is, whether the state of the transmission line is good). Accordingly, determination of the ratio X between the second moving average integration value and the first moving average integration value and selection of one of the plurality of antennas based on the ratio X enables judgment on whether the state of the transmission line is good even during a period other than a guard interval period Tg, that is, during an effective symbol period Tu.

A power amplifier (101) amplifies a high-frequency signal. A coupler (102) monitors the signal power Pmoni amplified by the amplifier (101). A detector (103) carries out linear half-wave rectification of the input above the forward voltage of a diode, integrates it using an RC filter, and produces a detected voltage Vdet. A gain / offset amplifier (104) amplifies the detected voltage Vdet and / or applies an offset voltage to convert the detected voltage Vdet to a desired voltage, and the resulting voltage serves as the gate voltage of the power amplifier (101). As a result, power consumption in a low-power region of a power amplifier is reduced, and hardware is downsized.

This invention is generally concerned with reduced power consumption signal processing methods and apparatus, and in particular with techniques for jointly controlling power supply voltage and clock frequency in a receiver to reduce power consumption. A method of reducing the power consumption of a data receiver is described. The receiver is configured to process a received signal using repeated implementations of substantially the same first data processing element, a rate of said repetitions being determined by a clock frequency of said first data processing element. The method comprises determining a number of repetitions of said repeated implementations of said first data processing element; processing said receiving signal according to said determined number of repetitions; adjusting said number of repetitions in response to a power saving control signal; and jointly reducing said clock frequency and a power supply voltage to said first data processing element in response to said control signal to reduce said receiver power consumption.

Disclosed is an Academy, Research Institute, and Agency (ARIA) encryption / decryption apparatus for encrypting and decrypting input data by repeating a plurality of rounds. The ARIA encryption / decryption apparatus includes a first register storing input data or an intermediate calculation value according to a first control signal; a second register storing a input round key for every round; an exclusive OR operation unit performing an exclusive OR operation on values stored in the first and second registers; a substitution unit substituting a result of the exclusive OR operation on a basis of an ARIA substitution algorithm; a diffusion unit diffusing a result of the substitution in the substitution unit on a basis of an ARIA diffusion algorithm if a current round is not a final round; and a control unit outputting the first control signal so that an output of the diffusion unit is used as the intermediate calculation value if the current round is the final round or an output of the substitution unit is used as the intermediate calculation value if the current round is the final round, and outputting an output of the exclusive OR operation unit as a result of the ARIA encryption / decryption.

The operation unit sequentially calculates the prediction error for each candidate vector based on the pixel data of the odd or even field and the pixel data of the odd or even field of the current image block, and the field comparator detects that the minimum prediction error is obtained among the calculated prediction errors The field motion vector of . The AE storage means stores a plurality of prediction errors calculated by the arithmetic unit on one of the prescribed combinations. The adder adds the prediction error calculated by the arithmetic unit to a corresponding one of the plurality of prediction errors stored in the AE storage device to calculate the prediction error in units of frames. Then, the frame comparator detects a frame motion vector that obtains the smallest prediction error among the calculated prediction errors in units of frames.

Provided are a method and apparatus for buffering image data for motion compensation. One of two buffers of a double register array buffer, i.e., a first buffer, is selected as a buffer in which data corresponding to a row of a block of an image is to be written and the other of the double register array buffer is selected as a buffer from which data corresponding to another row of the block is to be read, thereby speeding up motion compensation processing when compared with the use of a single register array buffer.