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Method and apparatus for power amplification

A technology for power amplification and input power, applied in power amplifiers, parts of amplifying devices, improving amplifiers to improve efficiency, etc., can solve problems such as large power consumption, complex feedback control circuits, and increased hardware scale

Inactive Publication Date: 2001-10-03
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] However, in the existing power amplifying device, in order to expand the dynamic range, a high-frequency variable gain amplifier is provided, a monitor signal is amplified by a control circuit, and a sample-and-hold circuit is used, etc., requiring a complicated feedback control circuit, and there is a hardware scale. growing problem
[0010] In addition, some control signals are required to determine the gain amount of the high-frequency variable power amplifier, so there is also a problem of large power consumption.

Method used

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  • Method and apparatus for power amplification
  • Method and apparatus for power amplification

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Embodiment 1

[0030] In Embodiment 1 of the present invention, a gain / bias amplifier is provided in the power amplification device, and the detection voltage is converted into a desired voltage value as the gate voltage of the power amplifier.

[0031] figure 2 A block diagram of main parts showing a schematic configuration of a power amplifying device according to Embodiment 1 of the present invention.

[0032] exist figure 2 Among them, the power amplifier 101 has at least one current control terminal (for example, a gate terminal of FET), and amplifies high-frequency signals. The coupler 102 monitors the amplified signal power P of the power amplifier 101 moni .

[0033] The detector 103 is an envelope detector composed of diodes, capacitors, resistors, etc., for a certain input voltage (for example, P moni >-5dBm) for linear half-wave rectification, integrated by RC filter to generate detection voltage V det .

[0034] Gain / bias amplifier 104 detects the voltage V det At least ...

Embodiment 2

[0043] Among them, if the amplitude provided by the forward voltage is large enough (high power), the detection can be sufficiently performed in the linear region, but when the amplitude is small (low power), it becomes the nonlinear region of the diode. For detection, envelope detection may not be possible because a sufficient detection voltage cannot be generated.

[0044] Embodiment 2 of the present invention is to solve this problem. In a power amplifying device having the same structure as Embodiment 1, a bias voltage is applied to the positive terminal of the detection diode.

[0045] Figure 4 A block diagram of main parts showing a schematic configuration of the power amplifying device of this embodiment. again, in Figure 4 in, where and figure 2 The same structures are assigned the same symbols, and detailed description thereof will be omitted.

[0046] Such as Figure 4 As shown, in this embodiment, a new diode 301 is connected to the positive terminal of the ...

Embodiment 3

[0051] Among them, generally speaking, the input power is handled by the absolute value representation [dBm] using the logarithm. The diode used in the detector 103 has a linear detection characteristic, and if the detection input power is considered in absolute value [dBm], there is also a logarithmic characteristic between the input power and the detection voltage.

[0052] Furthermore, when the current control of the power amplifier is performed, if the logarithmic characteristic is maintained, the detection voltage characteristic at low power is approximately constant, making it difficult to perform current reduction control.

[0053] Embodiment 3 of the present invention is to solve this problem. In a power amplifying device having the same structure as Embodiment 1, an offset circuit and a logarithmic amplifier are provided at the output end of the detection diode to convert the detection voltage characteristic into a linear characteristic.

[0054] Figure 6 A block di...

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Abstract

A power amplifier (101) amplifies a high-frequency signal. A coupler (102) monitors the signal power Pmoni amplified by the amplifier (101). A detector (103) carries out linear half-wave rectification of the input above the forward voltage of a diode, integrates it using an RC filter, and produces a detected voltage Vdet. A gain / offset amplifier (104) amplifies the detected voltage Vdet and / or applies an offset voltage to convert the detected voltage Vdet to a desired voltage, and the resulting voltage serves as the gate voltage of the power amplifier (101). As a result, power consumption in a low-power region of a power amplifier is reduced, and hardware is downsized.

Description

technical field [0001] The present invention relates to a power amplifying device used in a communication device of a mobile communication system and a power amplifying method thereof. Background technique [0002] Generally, if the gate voltage in the power amplifier is constant, the current will not be lower than a certain value even if the output power is reduced, so the efficiency is low and the current consumption is larger than necessary. [0003] Therefore, the conventional power amplifying device lowers the gate voltage while reducing the output power to expand the dynamic range of the current reduction to the low power range, thereby reducing the power consumption in the low power range. [0004] As a conventional power amplifying device, a device disclosed in JP-A-7-307699 is known. Below, use figure 1 Now, a conventional power amplifying device will be described. figure 1 A block diagram of main parts showing a schematic configuration of a conventional power am...

Claims

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Application Information

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IPC IPC(8): H03F1/02H04B1/04H04B7/26H04J13/00H04W52/04H04W52/52
CPCH03F1/0233H04B2001/045H03F1/02H03F3/24H04B1/40
Inventor 木野村昌宏
Owner PANASONIC CORP
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