1233results about "Computation using non-contact making devices" patented technology

The invention provides a ternary logic gate circuit, a calculation circuit, a chip and electronic equipment. The ternary logic gate circuit provided by the invention can realize addition and subtraction of 1 to an input logic value. Based on the ternary logic gate circuit, 27 univariate functions of ternary logic are utilized, the ternary logic gate circuit is applied to the ternary logic circuit, the purpose of simplifying the structure of the ternary logic circuit can be achieved, the number of transistors in the ternary logic circuit can be reduced, the power consumption of the ternary logic circuit can be reduced, and the reliability of the ternary logic circuit is improved. And the calculation efficiency of the ternary logic circuit is improved.

Various embodiments provide for clock signal distribution within a processor, such as a machine learning (ML) processor, using a photonic fabric.

Various embodiments provide for electro-photonic networks, including a plurality of processing elements connected by bidirectional photonic channels, suited for implementing neural-network models. Weights of the model may be preloaded into memory of the processing elements based on assignments of neural nodes to processing elements implementing them, and routers of the processing elements can be configured to stream activations between the processing elements based on a predetermined flow of activations in the model.

Systems and methods for efficient convolution based on matrix multiply and add (MMA) are described. An example processor having a plurality of processing lanes is configured to perform convolution of a matrix of activation elements and a filter matrix in accordance with a configurable series of instructions including a plurality of MMA instructions and shift instructions while reusing activation elements already loaded to the datapath or associated memory over a plurality of MMA operations. Associated methods are also described.

One embodiment provides a graphics processor comprising a base die including a plurality of chiplet sockets and a plurality of chiplets coupled with the plurality of chiplet sockets. At least one of the plurality of chiplets including first circuitry configured to perform a multi-dimensional matrix multiply accumulate operation to facilitate training for a neural network and second circuitry configured to perform dynamic datatype adjustment during the training for the neural network. The dynamic datatype adjustment is performed based on statistics generated based on output of the multi-dimensional matrix multiply accumulate operation, neural network model metadata, and training metadata associated with training operations to be performed for the neural network.

A circuit includes local computing cells. Each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a first data type, a first sum including (i) a first product of a first input data element and a first weight data element; and (ii) a second product of a second input data element and a second weight data element. Each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a second data type, (i) a second sum of a first portion of a third input data element and a first portion of a third weight data element; and (ii) a third product of a second portion of the third input data element and a second portion of the third weight data element.

The invention belongs to the field of edge computing acceleration, and relates to a fast Fourier transform and neural network reasoning collaborative computing acceleration method, which comprises the following steps of: deploying a computing method which is based on butterfly computing merging and a tensor mapping strategy and is mixed with DFT (Discrete Fourier Transform) and FFT (Fast Fourier Transform) in an operator deployment level; on the interface integration level, a bus interface of a register access path in a tensor accelerator control path is subjected to lightweight reconstruction, so that the bus interface is adaptive to an edge computing platform; in an operation level, a user-defined instruction is introduced into a tensor calculation unit, and an accelerator is enabled to independently complete a whole-process task of FFT signal processing and NN intelligent identification. According to the method, an operation instruction set is expanded on hardware, and delay overhead caused by returning a large amount of intermediate data to a processor is avoided, so that efficient execution of FFT and neural network tasks on unified hardware is guaranteed, and multiple requirements of high real-time performance, high precision and low power consumption are met.

The invention discloses a Chiplet-based matrix chain multiplication accelerator and an acceleration method. The matrix chain multiplication accelerator comprises a first matrix multiplication module, a first external memory interface and a nonlinear processing module, and a second matrix multiplication module and a second external memory interface which are connected with each other through Chiplet. The method comprises the following steps: acquiring operator data of a Transform network and preprocessing the operator data to obtain a matrix chain data stream; based on the matrix chain data stream, performing initialization processing on a matrix chain multiplication accelerator to obtain an initialized matrix chain multiplication accelerator; and inputting the matrix chain data stream into the initialized matrix chain multiplication accelerator for matrix multiplication operation to obtain attention matrix data. According to the embodiment of the invention, the utilization rate of the processing element can be improved, so that the memory access times and the data transmission delay are reduced, and the calculation efficiency is improved. The method can be widely applied to the technical field of computer hardware acceleration.

The disclosure describes hardware compression of sparse matrix content. One embodiment provides a graphics processor, the graphics processor comprising: a base die, the base die comprising a plurality of chiplet slots; and a plurality of chiplets, the plurality of chiplets being coupled with the plurality of chiplet slots. At least one chiplet of the plurality of chiplets comprises: a graphical core cluster comprising a plurality of processing elements; a shared local memory coupled with the plurality of processing elements; a plurality of matrix engines coupled to the shared local memory; and codec circuitry coupled with the shared local memory and the plurality of matrix engines. Codec circuitry is configured to decode matrix data stored in a first format in a shared local memory into a second format for consumption by a plurality of matrix engines.

The present application relates to the technical field of integrated circuits and relates to a matrix operation apparatus based on a flexible RRAM memory-computing array, and solves the problem in the prior art of the inability to reduce the area of the memory-computing array without affecting the precision. The apparatus comprises: the flexible RRAM memory-computing array for outputting cumulative currents of columns of memory-computing units to a multiplexer (MUX) on the basis of multiple rows of inputs; the MUX for selecting the cumulative current of one column of memory-computing units from among the columns of memory-computing units and sending said cumulative current to an analog-to-digital converter (ADC); the ADC for converting the received cumulative current into a digital signal and sending said digital signal to a subtractor; a popcount module for receiving the multiple rows of inputs, obtaining the number of 1 in the multiple rows of inputs, and outputting the number of 1 to a multiplier; the multiplier for multiplying the number of 1 by a fixed value β and sending a product result to the subtractor; and the subtractor for subtracting the product result from the digital signal to obtain a multiply-accumulate result of the matrix. The present application realizes high-precision memory-computing based on a small-area memory-computing array, further enhances energy efficiency, and can be applied to flexible computing chips to create electronic skin.

Electro-photonic networks, including a plurality of processing elements connected by bidirectional photonic channels, suited for implementing neural-network models. Weights of the model may be preloaded into memory of the processing elements based on assignments of neural nodes to processing elements implementing them, and routers of the processing elements can be configured to stream activations between the processing elements based on a predetermined flow of activations in the model.

The invention discloses a fusion multiply-add operation circuit compatible with multiple floating-point number formats, and the circuit comprises an input device which is used for obtaining three floating-point numbers and control information in a fusion multiply-add operation instruction; the input decoding device is used for analyzing the control information and extracting the symbol, the index and the mantissa of each floating-point number; the multiplication correlation device is used for calculating an initial index, a mantissa product and an initial symbol; the addend aligning and shifting device is used for completing addend mantissa aligning and shifting; the additive operation correlation device is used for calculating an addition result, a symbol, a normalized shift bit number and a direction flag bit according to the mantissa product sum; the original result processing device is used for generating an initial rounding bit, a normalized shift pasting bit and intermediate result data; and the final result output device is used for outputting a final operation result compatible with the IEEE-754 or Point floating-point number according to the rounding information. The circuit area and power consumption are remarkably reduced through hardware integration, and meanwhile the calculation efficiency is improved.

The invention provides a multiply-accumulate operation method and device for extremely low precision training, and the method comprises the steps: obtaining an operated part and to-be-operated data, and the to-be-operated data comprises one or more of floating point, fixed point and logarithm data formats; if the high-precision floating-point number exists in the data to be calculated, decomposing the high-precision floating-point number into the sum of two low-precision floating-point numbers; floating-point, fixed-point and logarithm data formats in the data to be calculated are decoded to be uniform formats of symbols, indexes and mantissas, and input data in the uniform formats are generated; performing multi-term dot product on the input data with the unified format to realize combined calculation of data formats with different precision; and adding the combined calculation result and the calculated part sum by adopting an advanced random rounding method. The method can support the combined calculation among various formats, reduces the bit width of the accumulator on the premise of maintaining the precision requirement by using an advanced random rounding method, and reduces the operation cost and improves the training efficiency under extremely low precision compared with the existing operation hardware.

A generative machine learning model, such as a convolutional neural network (CNN), can be trained with solutions from a topology optimization solver for a solution for a topology of a set of structures so that the generative machine learning model can generate a plurality of alternative designs for a structure that are alternative topology optimizations (for the structure) for a set of initial setup parameters. The generative model when being trained includes a generative network and a discriminator network. The generative model can be trained using outputs from a CNN autoencoder for densities and a CNN autoencoder for strain energies.

Methods and systems relating to computational hardware are disclosed herein. One disclosed method for executing a multiplication computation using a computational hardware block includes storing a first operand and a second operand for the multiplication computation. The first operand includes a first set of bit strings. The second operand includes a second set of bit strings. The method also includes multiplying the first set of bit strings and the second set of bit strings in a set of temporal phases using the computational hardware block. Each temporal phase uses a different group of bit strings from the first set of bit strings and the second set of bit strings. A cardinality of the set of temporal phases is determined by a fidelity control value. The fidelity control value adaptively sets a fidelity of execution of the multiplication computation.

A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.

The invention provides a complex operation lightweight architecture and method based on an FPGA, the architecture comprises a main scheduling module, a calculation module and a floating point operator module, the calculation module comprises a storage unit and a calculation unit, the storage unit obtains and caches input data of a target algorithm, and the main scheduling module carries out the calculation of the target algorithm according to the operation sequence of the target algorithm. The target algorithm is divided into a plurality of calculation steps, and corresponding operation enable signals are generated and transmitted to the calculation unit; the calculation unit obtains target parameters required by calculation steps from the storage unit according to the operation enable signal, obtains floating point operator units required by the calculation steps from the floating point operator module, and executes the calculation steps to determine an operation intermediate result; and storing the operation intermediate result in a storage unit, generating an operation completion signal and transmitting the operation completion signal to a main scheduling module to control the next calculation step until a final operation result is obtained. Therefore, the FPGA architecture with low power consumption and miniaturization is realized.

The embodiment of the invention discloses an internal memory, a chip and related electronic equipment. A target computing unit of the internal memory comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, one group of first-level multipliers is connected with one second-level multiplier through one adder tree; the group of first-level multipliers comprises a plurality of pairs of first multipliers, and each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers respectively receive data to perform multiplication operation, and respectively input output results into the first adder to perform addition operation; each second adder receives the output results of the plurality of first adders or the second adder at the upper level to carry out addition operation, and respectively inputs the output results to the second adder at the lower level or the third adder; and each third adder receives the output results of the plurality of second adders to carry out addition operation, and inputs the output results to the secondary multiplier to carry out multiplication operation. By implementing the embodiment of the invention, the memory computing capability can be improved.

A hardware accelerator including tiles arranged in a systolic array. At each of the tiles, the systolic array receives a first input block that includes first input matrix elements of a first input matrix. In each of a plurality of multiplication iterations, at each of the tiles, the systolic array receives a respective second input block. The systolic array computes tile products of the first input matrix elements and second input matrix elements included in the second input blocks. The systolic array adds the tile products to column-wise partial sums and transmits the column-wise partial sums to subsequent tiles along accumulator rings included in array columns of the systolic array. In a subset of the multiplication iterations, the systolic array outputs product block rows of a product matrix. The product block rows each include product matrix blocks computed as rows of the column-wise partial sums.

Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a TCAM array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, weights in a weight matrix may be programmed in SRAMs of a TCAM bit cell array. Each SRAM may operate as a multiplier that performs a multiplication between the stored weight to an input activation value applied at a search line in the TCAM bit cell array. The two SRAMs within a TCAM bit cell may operate independently to receive independently two input activation values on their respective select lines, and to perform a multiplication operation with the stored weight in each respective SRAM.

Multiply and accumulate (MAC) operations typically involve extremely large amounts of data and large numbers of operations. As such, they are extremely computationally intensive, involving large numbers of data transfers and consuming large amounts of time and power. To address these problems, the following presents methods of realizing a MAC engine in a 3D NAND flash die. The engine takes as input two vectors and outputs their dot product. The dot product of two vectors is the building block of matrix multiplication. The 3D NAND MAC engine presented here can be used to implement modern machine learning algorithms, in particular Neural Networks. The two vector operands are not programed into the NAND memory cells, therefore the endurance of the device is not compromised.

Methods and systems for generating geometric models of pitched roofs of buildings based on multiview imagery are provided. An example method involves establishing a three-dimensional coordinate space for the multiview imagery, displaying, through an annotation platform, multiview imagery depicting the pitched roof from different points of view, and providing, through the annotation platform, functionality for a user to define a perimeter of the pitched roof, define a ridge line of the pitched roof, and define at least part of a roof facet of the pitched roof by connecting the ridge line of the pitched roof to the perimeter of the pitched roof.

Disclosed is an attention mechanism-supporting accelerator, used for implementing a matrix multiplication operation, a scaling operation, or nonlinear activation processing involved in an attention mechanism. A weight cache state machine module is used for controlling the flow of weight data from a system bus to a weight cache unit. A thread cache state machine module is used for controlling the flow of thread data from the system bus to a thread cache unit. An attention tensor processing unit state machine module is used for controlling the loading and flow of the thread data and the weight data from different directions into a two-dimensional systolic array. The thread data is controlled to be delivered to the next processing unit in each period, and the weight data is propagated to each processing unit in a corresponding direction in the form of broadcasting. A computation result of the two-dimensional systolic array is delivered to different branches on the basis of whether nonlinear activation processing needs to be executed. According to the present invention, data padding is performed on a matrix so that the matrix is aligned with the systolic array data flow, thereby accelerating an attention mechanism having a variable sequence length by using hardware.

The present disclosure relates to a multiplier, a multiply-accumulate circuit, and a convolution operation unit. The multiplier includes: one or more selection circuits, each of the one or more selection circuits respectively configured to select a target preset multiple of a first operand from a preset multiple of a first operand as a fourth operand according to a corresponding third operand, wherein the target preset multiple is equal to a value of the third operand; and a partial product summing circuit, each of one or more input terminals of the partial product summing circuit respectively connected to an output terminal of corresponding one of at least one or more selection circuits, wherein the partial product summing circuit is configured to calculate a partial product sum of one or more fourth operands from the one or more selection circuits.

The invention discloses a hybrid precision storage and calculation control circuit based on a Sense-Switch type pFLASH. The hybrid precision storage and calculation control circuit comprises an NOR FLASH type SSpF storage and calculation array, a hybrid precision array controller, a hybrid precision shift adder and an AD module. The NOR FLASH type SSpF storage and calculation array is used for realizing convolution operation; the mixed precision array controller divides the NOR FLASH type SSpF memory calculation array according to the configured calculation precision, and completes input control and output sampling of 4, 8 or 16-bit convolution operation, and 4-bit weight programming and reading; the mixing precision shift adder performs shift addition on the output of the mixing precision array controller according to the sequence and the channel according to the configured calculation precision to obtain a 4, 8 or 16-bit convolution calculation result; the AD module is used for converting current output of the NOR FLASH type SSpF storage array into voltage output and converting an analog signal into a 4-bit digital signal. According to the method, 4, 8 or 16-bit convolution calculation can be realized in parallel, and the calculation precision can be configured.

The invention provides a matrix multiplication pipeline calculation method and device, an AI chip, electronic equipment, a medium and a program product, and relates to the field of artificial intelligence, in particular to the field of chips. According to the specific implementation scheme, in response to a matrix multiplication request, a plurality of general calculation components and a plurality of special calculation components in a chip are triggered in parallel, and in each conversion round, the general calculation components obtain matrix element types required by conversion from a first matrix and a second matrix and identify a conversion completion state; and under each calculation round, when the special calculation part queries that each conversion matrix element needing to be calculated in the current calculation round is converted, each conversion matrix element is acquired from the matched general calculation part to execute matrix multiplication calculation. The general calculation part and the special calculation part are executed in parallel, so that the time consumption of data type conversion and the time consumption of matrix multiplication can be mutually masked, the performance of the special calculation part is fully exerted, and the efficiency of matrix multiplication calculation and the performance of an AI chip are improved.

A processing-in-memory (PIM) device may include a plurality of memory banks configured to provide plural groups of weight data, a global buffer configured to provide plural sets of vector data, and a plurality of multiplication / accumulation (MAC) operators configured to perform MAC operations of the plural groups of weigh data and the plural sets of vector data. Each of the plurality of MAC operators includes a plurality of multiple operation circuits. Each of the plurality of multiple operation circuits is configured to perform an arithmetic operation in a first operation mode, a second operation mode, or a third operation mode according to first to third selection signals.

The invention discloses a control method and device of a non-volatile majority gate circuit and a summing circuit based on a memristor, and belongs to the technical field of microelectronic logic operation. In the majority gate circuit, the three memristors respectively and correspondingly input logic values a, b and c to be subjected to majority gate logic operation, and the result of the logic operation is determined by a voltage comparator according to the comparison result of the common node voltage and the reference voltage; by changing the voltage of the positive electrode of the memristor, two kinds of majority gate logics of M (a, b, c) and # imgabs0 # can be realized; in the implementation process of different types of majority gate logics, the number of memristors does not need to be increased, two kinds of majority gate logic operation can be achieved with few devices and high calculation speed, the two kinds of majority gate logics are complete, and any Boolean function can be achieved by combining the two kinds of majority gate logics; on the basis, the requirements for multifunctional logic in practical application can be met with high integration level and high calculation speed.

One embodiment provides a graphics processor comprising a base die including a plurality of chiplet sockets and a plurality of chiplets coupled with the plurality of chiplet sockets. At least one of the plurality of chiplets include a graphics core cluster including a plurality of processing elements, a shared local memory coupled with the plurality of processing elements, a plurality of matrix engines coupled with the shared local memory, and codec circuitry coupled with the shared local memory and the plurality of matrix engines. The codec circuitry is configured to decode matrix data stored in the shared local memory in a first format into a second format for consumption by the plurality of matrix engines.

Disclosed is a reconfigurable module-lattice-based key encapsulation mechanism (ML-KEM) post-quantum cryptography system and method using memory-based numbers theoretic transform (NTT). A post-quantum cryptography method of a post-quantum cryptography system including a plurality of internal submodules includes reconfiguring the plurality of internal submodules by variably selecting one security level from among the plurality of security levels; reconfiguring execution of the plurality of internal submodules to be changed through a main controller; and variably processing data according to the selected security level to perform key generation, encapsulation, and decapsulation through the reconfigured plurality of internal submodules.