501results about "Computation using non-contact making devices" patented technology

The invention discloses a fusion multiply-add operation circuit compatible with multiple floating-point number formats, and the circuit comprises an input device which is used for obtaining three floating-point numbers and control information in a fusion multiply-add operation instruction; the input decoding device is used for analyzing the control information and extracting the symbol, the index and the mantissa of each floating-point number; the multiplication correlation device is used for calculating an initial index, a mantissa product and an initial symbol; the addend aligning and shifting device is used for completing addend mantissa aligning and shifting; the additive operation correlation device is used for calculating an addition result, a symbol, a normalized shift bit number and a direction flag bit according to the mantissa product sum; the original result processing device is used for generating an initial rounding bit, a normalized shift pasting bit and intermediate result data; and the final result output device is used for outputting a final operation result compatible with the IEEE-754 or Point floating-point number according to the rounding information. The circuit area and power consumption are remarkably reduced through hardware integration, and meanwhile the calculation efficiency is improved.

A generative machine learning model, such as a convolutional neural network (CNN), can be trained with solutions from a topology optimization solver for a solution for a topology of a set of structures so that the generative machine learning model can generate a plurality of alternative designs for a structure that are alternative topology optimizations (for the structure) for a set of initial setup parameters. The generative model when being trained includes a generative network and a discriminator network. The generative model can be trained using outputs from a CNN autoencoder for densities and a CNN autoencoder for strain energies.

The embodiment of the invention discloses an internal memory, a chip and related electronic equipment. A target computing unit of the internal memory comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, one group of first-level multipliers is connected with one second-level multiplier through one adder tree; the group of first-level multipliers comprises a plurality of pairs of first multipliers, and each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers respectively receive data to perform multiplication operation, and respectively input output results into the first adder to perform addition operation; each second adder receives the output results of the plurality of first adders or the second adder at the upper level to carry out addition operation, and respectively inputs the output results to the second adder at the lower level or the third adder; and each third adder receives the output results of the plurality of second adders to carry out addition operation, and inputs the output results to the secondary multiplier to carry out multiplication operation. By implementing the embodiment of the invention, the memory computing capability can be improved.

Techniques are discussed herein for generating and evaluating driving simulations based on synthetic scenarios. Simulated objects may be controlled based on parameters determining the attributes and behaviors of the objects, and scenarios may be synthetically modified by changing the parameters for a simulated object. For a driving scenario with a synthetic simulated object, a simulation system may analyze driving log data to determine a probability or prevalence associated with the driving scenario. In various examples, the simulation system may determine marginal density estimates for individual attributes of the simulated object, as well as a cumulative distribution function modeling the dependence between the attributes. The joint probability distribution determined for the synthetic simulated object can be used for evaluating the efficacy of the simulation and the performance of the simulated vehicle controllers.

A hardware accelerator including input memory that receives first and second input matrices. The hardware accelerator further includes processing circuitry including one or more tiles that each include a respective tensor processor configured to receive a first and second input block of the first and second input matrices. Each tile receives a first block scale factor associated with rows of the first input block and a second block scale factor associated with columns of the second input block. Each tile multiplies the first input block by the second input block, applies the first block scale factor to rows of the result block, and applies the second block scale factor to columns of the result block to obtain a scaled result block. The processing circuitry further includes an accumulator that accumulates scaled result blocks to obtain a scaled result matrix, and output memory that receives and output the scaled result matrix.

The invention discloses a high-speed fixed-point multiplication circuit. The multiplication circuit is mainly composed of a multiplier coding module, a partial product generation module, a partial product compression module and a traveling wave carry adder module. The multiplier coding module is composed of a radix-4-Booth coding algorithm and an opposite number generation module, and is used for carrying out three-bit block coding on input multiplication data and generating an opposite number of a multiplicand in advance. The partial product generation module generates a plurality of groups of partial products with symbol extension according to the multiplicand coded signal. And the partial product compression module adopts an improved Wallace compression structure to perform layered compression on the partial product. And the traveling wave carry adder module sums the two groups of results output by compression and outputs a multiplication result. According to the invention, multiplication accumulation series can be reduced, the switching times of invalid signals in the circuit can be reduced, and the longest delay path in an operation link can be shortened, so that fixed-point multiplication which is high in speed, low in power consumption and more favorable for a comprehensive tool in structure is realized.

Certain aspects of the present disclosure provide techniques and apparatus for efficiently performing operations using data compression. An example method generally includes identifying, for a block of data samples, a number of leading bits to remove from each data sample in the block of data samples. A block of compressed data samples is generated based on the identified number of leading bits and truncation of a number of least significant bits from each data sample in the block of data samples. A bitstream including the block of compressed data samples and an indication of a type of compression applied to the block of data samples is generated and output for further processing.

One variation of a method includes: accessing a descriptor of a project; extracting a set of language signals from the descriptor; accessing a set of input parameters and a set of output characteristics; querying a language model for a range of values of input parameters exhibited within historical engineering solutions correlated with the set of language signals; accessing a virtual model for the project and a function representing a relationship between the set of input parameters and the set of output characteristics; for each analysis instance in a count of analysis instances, defining a combination of values of input parameters within corresponding ranges and based on the virtual model, the function, and the combination of values, executing the analysis instance to calculate a set of values of output characteristics; and rendering representations of combinations of values of input parameters and sets of values of output characteristics within a user interface.

A method for generating an online landscape design for a property includes first providing a computing system comprising at least a memory storing computer-executable instructions of a landscaping application, and a processor coupled to the memory. The landscaping application comprises a calculator engine, a landscape design engine, and a scoring engine. Next, calculating a landscape score of a property by retrieving landscape data from online databases and comparing an existing landscape design of the property to the retrieved landscape data via the scoring engine. Next, determining property landscape improvements by the scoring engine, and then generating an improved landscape design for the property based on the property landscape improvements of the scoring engine using the landscape design engine. Next, calculating an improved landscape score of the improved design via the scoring engine and displaying a 3D-image of the property with the improved landscape design and the improved score.

A RELU neuron chip circuit belongs to the field of chip circuits, and is characterized by comprising a vector summation circuit, a shift circuit, a subtraction circuit, a logic judgment circuit, an input port and an output port, the input ports comprise a data input port, a weight input port, a bias data input port and a data counting port; the output port comprises a data output port and a logic output port; by directly realizing the function of the neurons on the chip circuit, when a neural network system calls a certain neuron to carry out corresponding function calculation, data input and output can be directly carried out at the bottommost circuit level, so that a large amount of data cross-layer conversion time is saved. Only after the whole neural network completes one time of complete training or judgment operation, the operation result of the bottom layer circuit can be transmitted to the high layer from the bottom layer circuit in a cross-layer mode and displayed in a human eye recognizable mode. Therefore, the overall operation performance of the neural network system is improved.

According to the technical scheme, the large-scale logic optimization multiplier verification method is characterized in that a four-stage pipeline processing mode is adopted, the first stage is a partial adder tree recovery stage, and the second stage is a partial adder tree recovery stage; the second stage is an architecture generation stage; the third stage is a function verification stage; and the fourth stage is an equivalence checking stage. The verification capability is improved in a breakthrough manner and is far better than that of an existing method; the innovative three-stage decomposition strategy significantly reduces the calculation complexity, the ILP algorithm optimizes resource allocation, the multi-stage scheduling balances the calculation load, and the QACO algorithm efficiently explores the design space, so that the RefSCAT-2.0 framework provided by the invention becomes the most effective solution for verifying a large-scale logic optimization multiplier at present. From the perspective of practice, the technical blank of large-scale logic optimization multiplier verification is filled up, and important tool support is provided for reliability guarantee of key computing systems such as artificial intelligence chips, high-performance CPUs and GPUs.

The invention discloses an approximate multiplier, an operation method thereof, a processor and a chip, and belongs to the field of integrated circuits. The approximate multiplier comprises a high-order processing circuit, a low-order processing circuit, a high-low-order fusion circuit and an error compensation circuit, and the high-order processing circuit adopts a plurality of negative deviation approximate addition units, performs approximate addition on a high-order area of a partial product step by step and outputs an error signal; the low-order processing circuit adopts a positive deviation addition unit to process the low-order area to generate an intermediate result of positive deviation; the fusion circuit merges the high and low position results and outputs an initial multiplication result; the error compensation circuit compensates the result high order according to the error signal to offset the deviation. According to the approximate multiplier provided by the invention, the comprehensive performance of the multiplication unit in the aspects of area, power consumption and speed can be improved while the basic calculation precision is ensured.

Devices, systems, and methods for secure modular addition and subtraction are provided. A modular adder and subtractor circuit with masking circuit includes an arithmetic to Boolean (A2B) conversion operator configured to convert (i) a second sum and (ii) a value determined based on a first sum, to Boolean resulting in first and second Boolean values, a shifter configured to (i) make a most significant bit of the first Boolean value a least significant bit resulting in a shifted first Boolean value and (ii) make the most significant bit of the second Boolean value a least significant bit resulting in a shifted second Boolean value, and a Boolean to arithmetic (B2A) conversion operator, configured to convert a representation of the shifted first Boolean value and a representation of the shifted second Boolean value to arithmetic representation resulting in first and second arithmetic values, respectively.

Methods and systems for improved prediction and generation of structure interiors are provided. In one embodiment a method is provided that includes receiving exterior imagery of the structure and determining an exterior surface of the structure with a machine learning model. The exterior surface may enclose exterior portions of the structure. The machine learning model may further determine exterior features of the structure and may determine, based on the exterior surface of the exterior features, an interior model of the structure. A three-dimensional representation of interior and exterior portions of structure may be generated based on the exterior surface and the interior model.

The invention relates to the technical field of digital circuits, in particular to a high-speed and high-precision operational circuit for arcsine and arccosine functions, which comprises a preprocessing circuit for inputting a variable value of an initial function and outputting an input end connected with a first-order sub-function circuit and a second-order sub-function circuit. The output end of the first-order sub-function circuit and the output end of the second-order sub-function circuit are connected with the two input ends of the connecting circuit respectively, the output end of the connecting circuit is connected with the post-processing circuit, and an operation result is output. The preprocessing circuit processes the initial function to obtain a target original function with a definition domain and a value domain normalized to a target interval. The first-order sub-function circuit and the second-order sub-function circuit respectively process a target original function to obtain a first result and a second result; the connection circuit multiplies the two to obtain a third result; and the post-processing circuit multiplies the third result to obtain a final result. Therefore, the problems of complicated operation, high delay, high storage occupation, interpolation error and the like in related technologies are solved.

The invention relates to an in-memory processing device and an in-memory processing package with asymmetric internal and external bandwidths. In one embodiment, an in-memory processing (PIM) device includes a processing unit die configured to communicate with an external device over an external bandwidth, and a storage die configured to communicate with the processing unit die over an internal bandwidth. The external bandwidth and the internal bandwidth are asymmetrically configured to operate at different data transfer rates.

The invention provides a floating point index operation method, a tensor processor, equipment and a storage medium. The floating point index operation method comprises the following steps: converting a first equation into a second equation taking 2 as a bottom and taking a target floating point number multiplied by a reciprocal of ln2 as an index, and obtaining an integer term of an index of the second equation; obtaining a first decimal item of an index of the second equation, splitting the first decimal item into a fixed-point number item and a first floating-point number item, and obtaining a first index operation result corresponding to the fixed-point number item from a preset table; calculating a second exponential operation result of the integer term and multiplying the first exponential operation result by the second exponential operation result to obtain an initial natural exponential operation result of the target floating-point number; and performing Taylor expansion calculation on the first floating-point number item to obtain a third exponential operation result, and multiplying the initial natural exponential operation result of the target floating-point number by the third exponential operation result. According to the embodiment of the invention, the floating point index operation efficiency can be improved on the premise of ensuring the floating point index operation precision.

A server (200) includes a userland APL (230) that cooperates with an accelerator (212) while bypassing an OS (220). The userland APL (230) includes an ACC-NIC common data parsing part (232) that parses reception data in which an input data format of an ACC utilizing function and an NIC reception data format are made common.

Disclosed in the embodiments of the present application are an internal memory, a chip and a related electronic device. A target processing unit (202) of an internal memory (102) comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, wherein one group of primary multipliers is connected to one secondary multiplier by means of one adder tree; one group of primary multipliers comprises a plurality of pairs of first multipliers; each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers separately receives data to perform multiplication operations, and separately inputs output results into one first adder for addition operations; each second adder receives output results of a plurality of first adders or the upper-level second adder, so as to perform addition operations, and separately inputs the output results into the lower-level second adder or one third adder; and each third adder receives output results of a plurality of second adders to perform addition operations, and inputs the output results into one secondary multiplier for multiplication operations. Implementing the embodiments of the present application can improve the processing capability of the internal memory.

The application discloses a low-delay sequence detection device for CPO photoelectric signal reception, comprising an adaptive module and a plurality of partitioned forward-looking parallel detectors, the partitioned forward-looking parallel detectors comprising partitioned and branch metric calculation modules, trellis merging modules and decision modules connected in sequence, the partitioned and branch metric calculation modules being used for partitioning and branch metric calculation of PAM4 signals based on tap coefficients and ISI coefficients provided by the adaptive module for input signals, the trellis merging modules being used for trellis signal merging calculation of path metrics of synchronization blocks and backtracking blocks according to obtained branch metrics, and the decision modules being used for decision of input signals to obtain binary PAM4 signals according to obtained path metrics, and the adaptive module being used for adaptive update of tap coefficients and ISI coefficients. The application aims at CPO photoelectric signal reception while reducing the complexity, power consumption and delay of PAM4 signal sequence detection technology.

An apparatus and method for in-memory computation with weight update circuitry. The apparatus includes a memory array for storing a plurality of weight sets and a read circuit for reading the plurality of weight sets. The first weight buffer is used for storing a first weight set in a plurality of weight sets, and the write driver circuit is used for writing the first weight set into the first weight buffer during a single write clock pulse period. A plurality of first multiplier circuits receive a first set of weights from the first weight buffer and a first set of data inputs from the data input channels 0-N. Each of the first multiplier circuits receives a corresponding first weight of the first set of weights and a first data input of the first set of data inputs, and multiplies the first weight with the first data input to provide a partial product. The adder tree is used for summing the partial products and providing an accumulation result.

A jet aircraft maneuvering characteristic simulation system for a single propeller aircraft includes a power lever, speed brakes, and a controller. The power lever is configured to change a thrust of the single propeller aircraft. The speed brakes are provided on respective right and left sides of the single propeller aircraft. The controller is configured to, in response to an operation of the power lever to raise the thrust of the single propeller aircraft, deploy both the right and the left speed brakes to cause an increase in speed of the single propeller aircraft to be moderate, and control the speed brakes to cause a force in a yaw direction and a force in a roll direction to be generated that act against a turning tendency of the single propeller aircraft by making amounts of the deployment of the right and the left speed brakes different from each other.

This application provides a data processing method and a readable storage medium based on a matrix processor. The method includes: reading W first elements from a first matrix and sending the W first elements to a computing unit of the matrix processor for calculation; wherein W is greater than the width N of the first matrix and less than or equal to the number K of the computing units of the matrix processor; repeating the above steps until the number of remaining elements in the first matrix is ​​less than W; and in response to the number of remaining elements in the first matrix being non-zero, sending the remaining elements to the computing unit for calculation. This method can improve the utilization rate of the matrix processor's computing units, reduce the number of calculation cycles, shorten the calculation time, and fully utilize the computing units of the matrix processor.

The utility model discloses a digital signal processor (DSP) sampling conditioning circuit, which relates to the technical field of digital signal processing, and is characterized in that the output end of a voltage stabilizing circuit is connected with the input end of an anti-phase proportion operation circuit, and the output end of the anti-phase proportion operation circuit is connected with one input end of an adder circuit; the other input end of the adder circuit is connected with the output end of the sensor, and the output end of the adder circuit is connected with the input end of the DSP. According to the utility model, the measurement precision of the DSP can be improved.

The invention provides a data processing method and device, electronic equipment, a storage medium and a program product, and the method comprises the steps: obtaining texture data corresponding to a target operation instruction under the condition that the target operation instruction is received; under the condition that the texture data is floating point type data, generating first operation data according to mantissa bit data of the texture data, and generating second operation data according to index bit data and sign bit data of the texture data; performing operation processing on the first operation data and the weight parameter by utilizing a normalization operation unit corresponding to the normalization data to obtain a first operation result, combining the second operation data and the first operation result to obtain to-be-adjusted operation data, and performing data format conversion on the to-be-adjusted operation data to obtain a second operation result; and determining a target operation result of the target operation instruction according to the second operation result. According to the embodiment of the invention, waste of computing resources can be avoided, and the occupancy rate of the circuit area is reduced.

The invention relates to the technical field of current detection, in particular to a current sensor of an operational amplifier summing circuit, which comprises a frequency converter output end, a frequency converter load end, a precision resistor, an isolation acquisition chip, an operational amplifier circuit, a summing circuit and a singlechip ADC (Analog to Digital Converter) sampling port, and is characterized in that the precision resistor is connected with the frequency converter output end and the frequency converter load end through a welding copper bar; the isolation acquisition chip is connected with the precision resistor in a welding mode, the precision resistor outputs analog signals through voltage of the operational amplifier circuit and the summing circuit, the analog signals are acquired to an ADC sampling port of the single-chip microcomputer through the isolation acquisition chip, and the single-chip microcomputer calculates an actual current value. The detection precision is higher, the Ohm law and precise resistance sampling are adopted, analog signals are output to a sampling port of the single chip microcomputer ADC to calculate the actual current value, the current detection precision can be within + / -0.5% and is far higher than the 3% deviation of a traditional Hall sensor, the precise requirement of a control system is met, and the phenomenon of fault false alarm is reduced.

Disclosed embodiments relate to an accelerator for sparse-dense matrix instructions. In one example, a processor to execute a sparse-dense matrix multiplication instruction, includes fetch circuitry to fetch the sparse-dense matrix multiplication instruction having fields to specify an opcode, a dense output matrix, a dense source matrix, and a sparse source matrix having a sparsity of non-zero elements, the sparsity being less than one, decode circuitry to decode the fetched sparse-dense matrix multiplication instruction, execution circuitry to execute the decoded sparse-dense matrix multiplication instruction to, for each non-zero element at row M and column K of the specified sparse source matrix generate a product of the non-zero element and each corresponding dense element at row K and column N of the specified dense source matrix, and generate an accumulated sum of each generated product and a previous value of a corresponding output element at row M and column N of the specified dense output matrix.