7 results about "Modular arithmetic" patented technology

Techniques for fully homomorphic encryption are described. In some examples, a fully homomorphic encryption includes a butterfly compute circuitry to support a polynomial integer multiplication in response to an instance of a single instruction of a first type, wherein the instance of the single instruction is at least to include one or more fields for a register file address for a first source operand of the integer multiplication, one or more fields for a register file address for a second source operand of the integer multiplication, and one more fields for a register file address for a result of the integer multiplication, wherein the butterfly compute circuitry is to additionally support modular arithmetic operations.

This invention discloses a reconfigurable circuit for public-key cryptography algorithms. This circuit combines coarse / sub-coarse-grained reconfigurable circuits with microcontroller circuits. The sub-coarse-grained reconfigurable unit array employs a reconfigurable multiplier array from a multi-level reconfigurable NTT circuit to support NTT's underlying modular arithmetic. The coarse-grained reconfigurable units, through parameter configuration and data interconnection configuration, are used to implement large integer modular exponentiation and elliptic curve scalar multiplication. Based on the novel multi-level reconfigurable NTT circuit provided in this invention, quantum-resistant cryptographic algorithms can be implemented while also supporting traditional public-key cryptographic algorithms, thus offering advantages such as a small algorithm engine area and high flexibility.

This invention discloses a quantum circuit construction method, a ciphertext decryption method, and related devices. The quantum circuit construction method involves performing LUP matrix decomposition on the matrix corresponding to a preset fixed polynomial to obtain L-type, U-type, and P-type matrices. Then, a quantum circuit is constructed based on the L-type, U-type, and P-type matrices obtained by decomposition and a preset modular arithmetic unit. The quantum circuit can calculate the multiplication operation between an arbitrary polynomial and a fixed polynomial in the finite field GF(p,k). The quantum circuit can be used to efficiently generate multiplication operation data in GF(p,k), and the generated multiplication operation data can be used to accelerate the cracking of ciphertext in classical encryption algorithms.

Techniques for fully homomorphic encryption are described. In some examples, a fully homomorphic encryption includes a butterfly compute circuitry to support a polynomial integer multiplication in response to an instance of a single instruction of a first type, wherein the instance of the single instruction is at least to include one or more fields for a register file address for a first source operand of the integer multiplication, one or more fields for a register file address for a second source operand of the integer multiplication, and one more fields for a register file address for a result of the integer multiplication, wherein the butterfly compute circuitry is to additionally support modular arithmetic operations.

Techniques for key encapsulation mechanism (KEM) and digital signature authentication (DSA) are described. In some examples, at least one reconfigurable butterfly execution circuit that is reconfigurable to execute modular arithmetic instructions for both key encapsulation mechanism (KEM) and digital signature authentication (DSA) using polynomial data is provided. In some examples, number theoretic transform (NTT) circuitry to perform NTT operations and inverse number theoretic transform (iNTT) circuitry to perform iNTT operations, wherein the NTT and iNTT circuitry have a decimation-in-time (DIT) configuration is also provided.

This invention relates to the field of business forecasting and management, specifically to a complex business planning method based on a data platform and multi-agent collaboration. First, it acquires logical sequence deviations and physical environment jitter in parallel, and constructs a multi-dimensional evaluation benchmark using modular arithmetic and a sliding window algorithm, effectively solving the problems of sequence number flipping misjudgment and single-delay fluctuation interference. Second, it introduces a thermodynamic dissipation model to calculate the residual potential energy of missing data, causing it to decay non-linearly with waiting time, and combines business priority and network stability to calculate the real-time utility value of new data. Finally, it constructs a dynamic energy barrier by comprehensively considering buffer backlog depth, and determines whether to break the sequence rules by calculating a jump decision factor. This invention can effectively eliminate head-of-line blocking, ensure the real-time performance of high-priority control commands, and improve the robustness and consistency of industrial distributed collaborative computing.

A method for distributing a number K network connections from a host computer (host) to a smaller number M of core-affined receive queues (RXQs) of a data storage system (DSS) includes, by the host, allocating source network port identifiers (port IDs) from M identifier-defined groups, and using the allocated port IDs for respective network connections to the DSS. The DSS performs receive flow steering of host network traffic among the RXQs based on rules associating the M groups of port IDs with corresponding ones of the RXQs. In an example, port IDs are allocated and assigned to groups based on a modular arithmetic technique, and the DSS uses a modular operation on the port IDs of received network traffic to direct the traffic to respective cores, promoting balanced core utilization as well as alignment of requests to cores via the RXQs, with system performance benefit.