16 results about "Modular arithmetic" patented technology

Techniques for fully homomorphic encryption are described. In some examples, a fully homomorphic encryption includes a butterfly compute circuitry to support a polynomial integer multiplication in response to an instance of a single instruction of a first type, wherein the instance of the single instruction is at least to include one or more fields for a register file address for a first source operand of the integer multiplication, one or more fields for a register file address for a second source operand of the integer multiplication, and one more fields for a register file address for a result of the integer multiplication, wherein the butterfly compute circuitry is to additionally support modular arithmetic operations.

The present invention discloses a method and system for extracting and identifying spatial features of data. The data identification method includes: obtaining current power data, and determining a current power data spatial feature library by using the data spatial feature extraction method; obtaining a historical data spatial feature library, and determining a sensitive data spatial feature library by using preset sensitive data features and the historical data spatial feature library; performing modular arithmetic on the current power data spatial feature library and the sensitive data spatial feature library to determine the identification result of the current power data. The present invention solves the problem of low identification accuracy of traditional sensitive data identification methods that do not consider the application scenarios of data. Based on the matching and identification of spatial feature vectors, it realizes the accurate identification of sensitive data in a large amount of power data, and further supports the automatic identification of power sensitive data, improves the identification efficiency, and further improves the data security protection level.

The invention relates to the field of information security, in particular to a bilinear pairing hardware module design optimization method and device for an algorithm. The method comprises the following steps: dividing an algorithm into a plurality of independent executable modules, namely a modular operation layer, a bottom calculation logic layer and an advanced module layer; technical optimization is carried out on operation of a modular operation layer, a bottom calculation logic layer and an advanced module layer, and the number of modular operation times and the number of elliptic curve point operation times in bilinear pairing calculation are reduced. According to the method, bilinear pairwise calculation is decomposed into a plurality of independent modules through modular design, the modular operation times and the elliptic curve point operation times in the bilinear pairwise calculation are remarkably reduced, and therefore the overall calculation efficiency is improved.

Embodiments of the present application provide a modulus finger operator, a quantum circuit, a decryption method and device, equipment and medium, and relate to the field of quantum technology. The modulus finger operator comprises: a plurality of modulus double multipliers; each modulus double multiplier corresponds to a quantum bit in a first register one by one; the quantum states |A m‑1 > of each quantum bit in the first register respectively represent bits from high to low of a quantum superposition state |A m‑2 > respectively; the modulus double multiplier corresponding to the quantum state |A m‑3 > is used for evolving an operation result |X n > of a previous modulus double multiplier for the second register into |X n > when the quantum state |A n > is |1>, wherein R represents a first preset value, and K represents a second preset value; the input of the first modulus double multiplier comprises an initial state of an auxiliary quantum bit in the second register; n≤m-1. The function of modulus finger operation can be realized through the quantum circuit.

This invention discloses a reconfigurable circuit for public-key cryptography algorithms. This circuit combines coarse / sub-coarse-grained reconfigurable circuits with microcontroller circuits. The sub-coarse-grained reconfigurable unit array employs a reconfigurable multiplier array from a multi-level reconfigurable NTT circuit to support NTT's underlying modular arithmetic. The coarse-grained reconfigurable units, through parameter configuration and data interconnection configuration, are used to implement large integer modular exponentiation and elliptic curve scalar multiplication. Based on the novel multi-level reconfigurable NTT circuit provided in this invention, quantum-resistant cryptographic algorithms can be implemented while also supporting traditional public-key cryptographic algorithms, thus offering advantages such as a small algorithm engine area and high flexibility.

A method for distributing a number K network connections from a host computer (host) to a smaller number M of core-affined receive queues (RXQs) of a data storage system (DSS) includes, by the host, allocating source network port identifiers (port IDs) from M identifier-defined groups, and using the allocated port IDs for respective network connections to the DSS. The DSS performs receive flow steering of host network traffic among the RXQs based on rules associating the M groups of port IDs with corresponding ones of the RXQs. In an example, port IDs are allocated and assigned to groups based on a modular arithmetic technique, and the DSS uses a modular operation on the port IDs of received network traffic to direct the traffic to respective cores, promoting balanced core utilization as well as alignment of requests to cores via the RXQs, with system performance benefit.

A basic arithmetic unit, an arithmetic apparatus and method, and a computer-readable storage medium. The basic arithmetic unit comprises a plurality of modular arithmetic basic addition units, a plurality of selection units and a plurality of concatenation units, the modular arithmetic basic addition units comprising a first modular arithmetic basic addition unit and a second modular arithmetic basic addition unit, wherein the first modular arithmetic basic addition unit is configured to perform an operation on lower bits of an operand to obtain a plurality of lower-bit operation results; the second modular arithmetic basic addition unit is configured to perform an operation on higher bits of the operand to obtain a plurality of higher-bit operation results, the higher-bit operation results including with-carry results and without-carry results; the plurality of selection units are configured to select corresponding with-carry results or without-carry results on the basis of whether carries from the lower-bit operation results to the higher bits occur, and output the with-carry results or without-carry results to the concatenation units; an operation result is determined on the basis of the highest bits of concatenation results; and the plurality of concatenation units are configured to concatenate the higher-bit operation results with the lower-bit operation results to obtain concatenation results.

This invention discloses a quantum circuit construction method, a ciphertext decryption method, and related devices. The quantum circuit construction method involves performing LUP matrix decomposition on the matrix corresponding to a preset fixed polynomial to obtain L-type, U-type, and P-type matrices. Then, a quantum circuit is constructed based on the L-type, U-type, and P-type matrices obtained by decomposition and a preset modular arithmetic unit. The quantum circuit can calculate the multiplication operation between an arbitrary polynomial and a fixed polynomial in the finite field GF(p,k). The quantum circuit can be used to efficiently generate multiplication operation data in GF(p,k), and the generated multiplication operation data can be used to accelerate the cracking of ciphertext in classical encryption algorithms.

The invention discloses a quantum processor for dihedral group coset separation and a quantum state coding method, and relates to the technical field of quantum computing. The quantum processor comprises a first mapping circuit and a second mapping circuit; the first mapping circuit acts on a first register sigma gt; n, a second register tau gt; and a third register 0gt; a Z-CONT gate of n is in a quantum state tau gt of the second register; the value is 0gt; if yes, setting the quantum state sigma gt of the first register; n is mapped to the third register, so that the quantum state of the third register is 0 gt; n is evolved into sigma gt; n; the second mapping circuit acts on the first register sigma gt; n, a second register tau gt; and a third register [sigma] gt; a modular arithmetic unit of n in a second registered quantum state tau gt; the weight is 1gt; if yes, setting the first register sigma gt based on the number q of rotation operations in representative elements of the dihedron group; n is subjected to modular operation, and a first register sigma gt is established based on a modular operation result; n is equal to the quantum state sigma gt of the third register; n is equal to 0. Dihedron group coset separation can be realized by using a quantum computer.

A signed integer modular multiplication apparatus includes input part receiving first signed integer, second signed integer, modular arithmetic divisor P, positive integer n, and constant R; multiplication part; and upper bit acquisition part. multiplication part calculates first product of 2n bits in length from second signed integer and constant R, multiplication part calculates second product of 2n bits in length from first product and first signed integer, upper bit acquisition part performs integer approximation on result of signed n-bit right shift on second product to acquire first upper bits, multiplication part calculates third product of 2n bits in length from first upper bits and modular arithmetic divisor P, and upper bit acquisition part performs integer approximation on result of signed n-bit right shift on third product to acquire second upper bits. Constant R is a reciprocal of modular arithmetic divisor P by calculation of signed integer modulo22n.

Techniques for fully homomorphic encryption are described. In some examples, a fully homomorphic encryption includes a butterfly compute circuitry to support a polynomial integer multiplication in response to an instance of a single instruction of a first type, wherein the instance of the single instruction is at least to include one or more fields for a register file address for a first source operand of the integer multiplication, one or more fields for a register file address for a second source operand of the integer multiplication, and one more fields for a register file address for a result of the integer multiplication, wherein the butterfly compute circuitry is to additionally support modular arithmetic operations.

Techniques for key encapsulation mechanism (KEM) and digital signature authentication (DSA) are described. In some examples, at least one reconfigurable butterfly execution circuit that is reconfigurable to execute modular arithmetic instructions for both key encapsulation mechanism (KEM) and digital signature authentication (DSA) using polynomial data is provided. In some examples, number theoretic transform (NTT) circuitry to perform NTT operations and inverse number theoretic transform (iNTT) circuitry to perform iNTT operations, wherein the NTT and iNTT circuitry have a decimation-in-time (DIT) configuration is also provided.

In accordance with an embodiment, a method includes determining whether a frame received from a communication bus is encoded according to a particular communication protocol and is addressed to a particular electronic device; increasing a frame count value when the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device based on the determination, wherein increasing the frame count value comprises increasing a count of a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit; setting a frame count status bit based on comparing the frame count value to threshold values, and transmitting a frame comprising the frame counter status bit over the communication bus, and resetting the frame count value at an end of a monitoring time interval.

This invention relates to the field of business forecasting and management, specifically to a complex business planning method based on a data platform and multi-agent collaboration. First, it acquires logical sequence deviations and physical environment jitter in parallel, and constructs a multi-dimensional evaluation benchmark using modular arithmetic and a sliding window algorithm, effectively solving the problems of sequence number flipping misjudgment and single-delay fluctuation interference. Second, it introduces a thermodynamic dissipation model to calculate the residual potential energy of missing data, causing it to decay non-linearly with waiting time, and combines business priority and network stability to calculate the real-time utility value of new data. Finally, it constructs a dynamic energy barrier by comprehensively considering buffer backlog depth, and determines whether to break the sequence rules by calculating a jump decision factor. This invention can effectively eliminate head-of-line blocking, ensure the real-time performance of high-priority control commands, and improve the robustness and consistency of industrial distributed collaborative computing.

The invention discloses a multi-distribution noise generation device based on modular operation, which adopts 3D-HCM chaotic mapping, can regulate and control the distribution and amplitude of random numbers by changing parameters, and further realizes the generation of different distribution noises, so that the regulation and control of noise distribution can be realized only by changing the parameters of an upper computer. Then the three paths of random numbers are sent to a noise sequence generation module, it is guaranteed that a chaotic mapping original iteration noise sequence controlled by parameters can be output, a new noise sequence obtained through internal function regulation and control and external function regulation and control can also be output, the sequence of output noise is further enriched, and more requirements are met. The noise sequence output management module carries out subsequent operation on the three noise sequences, and when any one of the generated three noise sequences is selected to be directly output to a subsequent module, randomly distributed noise can be directly generated, or real-time output of the noise can be realized by using an assembly line method and splicing iteration output and then outputting the spliced iteration output. Therefore, the output bandwidth is improved. Meanwhile, random numbers generated by the three-dimensional chaotic mapping iteration module are high in randomness, so that the randomness of generated noise is enhanced.

A method for distributing a number K network connections from a host computer (host) to a smaller number M of core-affined receive queues (RXQs) of a data storage system (DSS) includes, by the host, allocating source network port identifiers (port IDs) from M identifier-defined groups, and using the allocated port IDs for respective network connections to the DSS. The DSS performs receive flow steering of host network traffic among the RXQs based on rules associating the M groups of port IDs with corresponding ones of the RXQs. In an example, port IDs are allocated and assigned to groups based on a modular arithmetic technique, and the DSS uses a modular operation on the port IDs of received network traffic to direct the traffic to respective cores, promoting balanced core utilization as well as alignment of requests to cores via the RXQs, with system performance benefit.