995 results about "Hardware implementations" patented technology

High-level synthesis (HLS) is a complex design flow that exploits the benefit of modern language features such as loops, inheritance, templates, etc. for rapid prototyping of hardware designs. Hardware engineers explore various design space parameters in a time-consuming trial-and-error approach to meet a target design specification. This invention provides a framework where machine learning methods are integrated with Bayesian optimization (BO) to accelerate hardware design in HLS. This tool is built around the context of HLS pragma exploration and kernel transformation. It can produce best set of pragma installments to determine parameters by optimizing on multi-objective functions, such as reduction of digital signal processor, flip-flop, look-up table, power consumption, and latency. The method uses classical deep neural network and quantum neural network for reinforcement meta learning to predict the synthesis characteristics and synthesizability under a given time budget. A large language model can also assist transpilation to modify the original codes so that the best tradeoff between hardware complexity, latency, and power consumption is realized.

The invention provides a power domain control software architecture and a controller thereof, the software architecture comprises an application layer developed based on an AUTOSAR standard, a runtime environment and a basic software layer, the application layer comprises a plurality of modularized software components, the software components package service logic functions of the controller to be integrated, the software components are provided with an AUTOSAR-based ARXML file definition interface, and the AUTOSAR-based ARXML file definition interface is used for defining the service logic functions of the controller to be integrated. According to the method, the interface compatibility can be improved, seamless integration of application layers across controllers can be realized, and the development parallelism is enhanced by kernel deployment of independently packaged software components according to the real-time performance of functions. The runtime environment generates an inter-core communication agent code, constructs a virtual bus and routes a service request of an application layer component to the basic software layer, and the basic software layer provides system-level service for the application layer through a virtual bus interface of the runtime environment, so that the application layer does not need to directly operate hardware, software and hardware decoupling is realized, and the service performance of the application layer is improved. And smooth realization of software fusion and integration is promoted.

The invention discloses a nonlinear equalization method, device and equipment and a storage medium, and relates to the technical field of communication, and the method comprises the steps: obtaining a floating point tap coefficient of an original equalizer, and carrying out the low-order quantization of the floating point tap coefficient, and obtaining an integer tap coefficient; constructing a target equalizer based on the integer tap coefficient; and compensating nonlinear distortion of a to-be-processed signal based on the target equalizer to obtain a recovered signal. Through the mode, the low-order quantization is performed on the tap coefficient of the equalizer, and the traditional floating-point number is converted into the low-order integer for representation, so that the storage space and the calculation complexity are remarkably reduced, the hardware implementation efficiency can be optimized and the power consumption can be reduced while the transmission performance is ensured.

Approaches presented herein provide for the generation, transmission, and upsampling of content for presentation using devices with varying graphics capabilities. Various computing devices can include integrated GPUs or other limited capacity hardware that may be unable to support higher performance graphics upscaler algorithms, and can thus default to using a process such as hardware-implemented bilinear filtering for upscaling, resulting in lower quality displayed images. An adaptive filter can be used to reduce the number of texture accesses needed per pixel, which can provide for improved perceptive quality and increased device support. A number of input samples to be taken for an output pixel location can be adapted to the capacity of the device to perform the upsampling, where a reduced number of samples or “taps” per pixel can significantly reduce the resource capacity needed to perform upscaling and interpolation using a Catnumm-Rom filter or Lanczos filter, implemented as a GPU shader, and allow higher quality upscaling on limited capacity systems.

The invention discloses a signal sampling method for a multi-channel signal converter, and the method comprises the steps: carrying out the synchronous and parallel sampling of an analog signal source according to a multi-channel signal collection module, so as to obtain multi-channel original signal sequence data; performing inter-channel time delay calibration and amplitude normalization processing on the multichannel original signal sequence data to obtain a calibrated multichannel signal data set; the invention relates to the technical field of signal processing. According to the signal sampling method for the multi-channel signal converter, the multi-channel signal converter improves the data consistency and accuracy through the technologies of synchronous sampling, time delay calibration, amplitude normalization and the like, meanwhile, precision adjustment of self-adaptive filtering, dynamic threshold segmentation and entropy driving is adopted, signal interference and abnormal data are reduced, and the signal quality is improved. The non-uniform resampling and compression technology is adopted to optimize the storage and transmission efficiency, key data is ensured to be transmitted preferentially, hardware is accelerated through an FPGA, and the real-time performance and the processing capacity of the system are improved.

The invention discloses a wafer level chip system design space construction and rapid parameter search method. The method comprises the steps of task graph definition, prefabricated member parameter quantification, joint model construction based on task graph features and prefabricated member features, and Bayesian optimization implementation strategy. According to the technical scheme, construction and search of the design space can be guided, so that the number of times of calling a simulator is reduced, and construction of the design space of the wafer-level chip system architecture, efficient parameter search and performance evaluation are achieved. The method can be used for agile design and hardware implementation of a multi-chip integrated wafer-level chip system architecture.

The embodiments herein provide a secure computing resource set identification, evaluation, and management arrangement, employing in various embodiments some or all of the following highly reliable identity related means to establish, register, publish and securely employ user computing arrangement resources in satisfaction of user set target contextual purposes. Systems and methods may include, as applicable, software and hardware implementations for Identity Firewalls; Awareness Managers; Contextual Purpose Firewall Frameworks for situationally germane resource usage related security, provisioning, isolation, constraining, and operational management; liveness biometric, and assiduous environmental, evaluation and authentication techniques; Repute systems and methods assertion and fact ecosphere; standardized and interoperable contextual purpose related expression systems and methods; purpose related computing arrangement resource and related information management systems and methods, including situational contextual identity management systems and methods; and / or the like.

The invention discloses a TFHE-oriented programmable bootstrap hardware implementation system, and the system comprises a vector calculation module which is used for executing an analog-to-digital switching step in a TFHE-oriented programmable bootstrap algorithm on an LWE ciphertext; the rotary register is used for caching and rearranging the LWE ciphertext; the function calculation module is used for executing a blind rotation step in a TFHE-oriented programmable bootstrap algorithm on the rearranged LWE ciphertext and the analog-to-digital switching result to obtain a blind rotation result; the vector calculation module is also used for executing a sample extraction step and a key switching step in a TFHE-oriented programmable bootstrap algorithm on the blind rotation result to obtain a decrypted ciphertext; when the function calculation module executes the blind rotation step, the polynomial in the rearranged LWE ciphertext and the analog-digital switching result is decomposed into a plurality of sub-polynomials through a number theory conversion unit, and the sub-polynomials are subjected to parallel calculation. The method can reduce the use amount of hardware units, and is high in decryption success rate, high in performance and small in area.

Systems and methods are provided for analog hardware realization of neural networks. The method includes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology to an equivalent analog network of analog components including operational amplifiers and resistors. Each operational amplifier represents an analog neuron of the equivalent analog network, and each resistor represents a connection between two analog neurons. The method also includes computing a weight matrix based on the weights of the trained neural network. The method also includes generating a resistance matrix for the weight matrix. The method also includes pruning the equivalent analog network to reduce the number of operational amplifiers or the resistors, based on the resistance matrix, to obtain an optimized analog network of analog components.

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

The invention relates to the technical field of system-on-chip service interrupt processing, in particular to a hardware Sequence-based SoC interrupt processing method, which comprises the following steps of: pre-programming an interrupt processing instruction sequence into an instruction random access memory (RAM), and configuring an instruction set, a sequence processor and an interrupt priority strategy of a task scheduler Sequence; receiving the interrupt signal by a task scheduler, and selecting a corresponding sequence processor according to an interrupt type; for the interrupt with low priority, the Sequencer directly executes the pre-stored instruction sequence to complete the interrupt response; and for high-priority interruption, the Sequencer caches the state of the register and sends a message packet to notify the CPU to perform cooperative processing. According to the method, interrupt autonomous response is achieved through hardware Sequence, zero CPU intervention is achieved in low-priority interrupt, a lightweight message mechanism is adopted in high-priority interrupt, and bandwidth occupation and power consumption are reduced while efficiency is improved.

This disclosure describes supporting distributed graphics and compute engines in a multi-dielet processor, such as, for example, a multi-dielet graphics processing unit (GPU), architectures and synchronization in such architectures. Each multi-dielet processor includes a hardware-implemented remapping capability and / or a hardware-implemented memory barrier capability.

The invention discloses a method, a processor and a system for realizing RISC-V architecture to run an X86 instruction set through hardware, and the method comprises the steps: judging whether there is an equivalent RISC-V standard instruction for replacing an X86 instruction, and if there is an equivalent RISC-V standard instruction, determining the X86 instruction and the equivalent RISC-V standard instruction as a first instruction and a second instruction respectively; if the X86 instruction does not exist, whether a non-equivalent RISC-V standard instruction replacing the X86 instruction exists or not is judged, if yes, whether the execution efficiency of the non-equivalent RISC-V standard instruction meets a preset requirement or not is judged, and if yes, it is determined that the X86 instruction and the non-equivalent RISC-V standard instruction are a third instruction and a fourth instruction respectively; if not, an RISC-V custom instruction replacing the X86 instruction is determined, and the X86 instruction and the RISC-V custom instruction are determined to be a fifth instruction and a sixth instruction respectively; and obtaining an instruction processing result which takes the first or third or fifth instruction as input and correspondingly takes the second or fourth or sixth instruction as output, and storing the instruction processing result in a hardware device. According to the method, the X86 instruction set can be quickly and efficiently operated by the RISC-V architecture.

According to the heterogeneous multi-core chip power consumption state control system and the heterogeneous multi-core chip provided by the invention, the power consumption state request of each sub power supply domain is received through the set system hardware power consumption management module, and the driving signal is sent to the corresponding sub power supply domain according to the preset hardware time sequence, so that the corresponding sub power supply domain enters the target state; generating a PMU control signal; and the power management module drives an internal voltage regulator to execute corresponding regulation operation according to the PMU control signal. A special control processor (SCP) is not needed, the system hardware power consumption management module realized by pure hardware is adopted to directly control the power consumption state of each sub power supply domain in the heterogeneous multi-core SoC, the software processing delay is eliminated, the response speed is high, the static power consumption of the power consumption management module is remarkably reduced, and the system is particularly suitable for an ultra-low power consumption scene and has a wide application prospect. And hardware-level surge current protection is realized in a multi-core power-on process.

The invention discloses a data processing method, electronic equipment, a medium and a computer program product, and relates to the technical field of computers, and the data processing method comprises the following steps: firstly, arranging feature data blocks by taking batches as elements, arranging weight data blocks by taking output channels as elements, and accessing feature data and weight data more orderly in convolution calculation; then, a proper storage mode is selected by judging the scale of network data and a set threshold value; when the data scale is smaller than a set threshold value, convolution calculation is carried out after data are loaded in an on-chip storage mode, data reading delay can be reduced, and the calculation response speed can be increased; when the data scale is large, an off-chip memory access mode is adopted to load data while convolution calculation is carried out, so that idle calculation resources caused by waiting for all the data to be loaded are avoided. In this way, the convolution calculation part for feature extraction of the reinforcement learning front end can be cooperatively deployed to the block matrix calculation architecture, resource reuse is achieved, and hardware implementation complexity and hardware resource consumption are effectively reduced.

The invention relates to a random calculation processing unit and method based on a self-adaptive compensation mechanism, and the method employs a self-adaptive compensation core formed by solidifying a lightweight neural network to replace a conventional solidification compensation rule, and the self-adaptive compensation core can carry out the random calculation according to two operands participating in multiplication. And an optimal compensation parameter is dynamically predicted in real time for compensation. According to the scheme, the calculation error of random calculation is accurately, continuously and individually compensated in a data driving mode, and hardware implementation is performed by adopting a constant coefficient multiplier technology, so that the self-adaptive compensation core has extremely low area and power consumption overhead in hardware. Compared with the prior art, the method has the advantages that the fidelity of random calculation can be greatly improved on the premise that the hardware cost is not remarkably increased, and a new effective way is provided for constructing a high-performance and high-energy-efficiency random calculation neural network accelerator.

The invention relates to the technical field of multi-modal feature fusion, in particular to a training method of a multi-cause regulation AI large model and an intelligent decision making system. Through data preprocessing, feature expression optimization, class center construction of support data, efficient distance calculation, dynamic parameter adjustment and a self-adaptive hyper-parameter and field self-adaptive strategy, the multi-cause regulation AI large model is obtained; according to the technical scheme, the robustness and accuracy of model training are remarkably improved. Meanwhile, the modularized hardware implementation scheme ensures the high efficiency and stability of the overall operation of the system, and can adapt to the requirements of the data size and the field change, thereby providing an efficient, stable and intelligent neural network model training platform for an intelligent decision-making system.

The utility model provides an aircraft control assembly rapid troubleshooting test device, comprising a test host computer and a test circuit board, the test host computer sends a test control instruction to the test circuit board, and the test circuit board outputs a discrete signal for the test of a to-be-tested device to the to-be-tested device after receiving the test control instruction. And after the to-be-tested device receives the test discrete signal, test feedback information is transmitted to the test circuit board, and the test circuit board sends the test feedback information to the test upper computer, so that the test upper computer processes the test feedback information to judge whether the function of the to-be-tested device is normal or not. Compared with a traditional test bench test method, the method has the advantages that functions which cannot be realized by a traditional test bench can be realized by using existing software and hardware, the time for completing the test of a single aircraft control assembly is shorter, the test efficiency is higher, a more efficient and effective test program is realized, and the overall quality and reliability of the aircraft control assembly are improved.

Systems, apparatus, and methods for real-time guided encoding. In one exemplary embodiment, an image processing pipeline (IPP) is implemented within a system-on-a-chip (SoC) that includes multiple stages, ending with a codec. The codec compresses video obtained from the previous stages into a bitstream for storage within removable media (e.g., an SD card), or transport (over e.g., Wi-Fi, Ethernet, or similar network). While most hardware implementations of real-time encoding allocate bit rate based on a limited look-forward (or look-backward) of the data in the current pipeline stage, the exemplary IPP leverages real-time guidance that was collected during the previous stages of the pipeline.

The invention discloses a floating-point number index maximum value searching circuit and an in-memory computing chip. The searching circuit comprises an SRAM (Static Random Access Memory) unit matrix which comprises a plurality of rows and columns of SRAM units, wherein each unit comprises NMOS (N-channel Metal Oxide Semiconductor) tubes N1-N5 and PMOS (P-channel Metal Oxide Semiconductor) tubes P1 and P2; n1, N2, P1 and P2 are in reverse cross coupling to form a pair of storage nodes Q and QB; the grid electrode of the N5 is connected with a node QB; the grid electrode of the N3 in the ith row is connected with a word line WLLlt; igt; the grid electrode of the N4 is connected with a word line WLRlt; igt; ; the drain electrode of each column of N5 is connected in series with the source electrode of the next column of N5, and the source electrode of the first column of N5 is connected with a signal SELlt; igt; the N5 drain electrode of the last column is connected with a signal PRE; in the jth column, N3 is a corresponding node Q and a bit line BLlt; jgt; the transmission tube N4 is a corresponding node QB and a bit line BLBlt; jgt; and a transmission tube. According to the invention, the number of searching cycles is saved, the calculation time is shortened, the subsequent calculation amount is reduced, the efficiency is improved, the power consumption is reduced, and the defects of relatively high power consumption, complex hardware implementation, relatively long calculation delay and the like of an existing circuit are overcome.

The embodiment of the invention provides a calculation method and device for elliptic curve encryption scalar multiplication, electronic equipment and a computer readable storage medium, and relates to the technical field of information encryption. The method comprises the following steps: determining a base point G and each group of sub-scalar quantity k on an elliptic curve, wherein each group of sub-scalar quantity k is obtained by coding a scalar quantity K based on a window method; reading a first result Rd corresponding to the actual value of the sub-scalar k from an SRAM (Static Random Access Memory) for each group of sub-scalar; determining a Q point on the elliptic curve according to the first result Rd corresponding to each group of sub-scalar k; wherein the first result Rd corresponding to the actual value of the sub-scalar k is obtained from the preset SRAM, and the method further comprises the following steps of: aiming at each possible value of each group of sub-scalar k, performing scalar multiplication on the base point G and the possible value through a point addition and point doubling operator realized by hardware to obtain the first result Rd corresponding to the possible value, and writing the first result Rd into the SRAM. According to the embodiment of the invention, the scalar multiplication operation efficiency is improved.

Circuitry for performing neural-network calculations includes a plurality of compute circuits, arranged in parallel with respective inputs and outputs, to receive function arguments for a node of a neural network on their respective inputs, compute values of a plurality of activation functions using the function arguments, and provide the values on their respective outputs. Each compute circuit of the plurality of compute circuits is to compute the values of a respective activation function of the plurality of activation functions. The circuitry also includes a multiplexor to select between the respective outputs of the plurality of compute circuits and to provide the values on a selected output as activation-function values for the node of the neural network, based on an activation-function selection signal.

The invention provides an instruction pipeline processing method of a processor and the processor. A processor includes: a control module; the control module is set to execute the branch instruction speculatively according to the branch prediction direction when detecting that the first instruction subjected to initial decoding is the branch instruction, and execute the branch instruction if detecting that the second instruction subjected to initial decoding is the function call instruction or the function return instruction before the speculation execution result of the first instruction is generated. If yes, pausing all operations after the instruction processing assembly line performs initial decoding on the second instruction, and blocking the instruction fetching operation of the instruction processing assembly line on the next instruction until a speculation execution result of the first instruction is obtained; wherein the operation after the initial decoding comprises the step of carrying out a push-in or push-out operation of a return address stack (RAS) according to the second instruction. According to the technical scheme, the pollution risk caused by speculative execution of the branch instruction to the return address stack can be shielded, so that the hardware implementation logic of the return address stack is simplified, and the circuit area and power consumption are saved.

The invention discloses a CXL protocol extension method, device and system based on the Ethernet. The method comprises the following steps of: carrying out long-distance expansion interconnection on a CXL (Compute Express Link) protocol by using Ethernet as a physical transmission medium; by bearing the CXL protocol on the Ethernet, the range of memory pooling is expanded from the rack level to the whole data center (kilometer level), and the potential of the CXL technology is thoroughly released; through protocol translation, label management and flow control realized by pure hardware, an operating system kernel and a software protocol stack are bypassed, so that the end-to-end memory access delay is far lower than that of any software-based network storage scheme, and a reliable request-response tracking and timeout retransmission mechanism is realized through a hardware label manager. By distinguishing the control flow and the data flow, differentiated QoS guarantee is provided for different types of memory flows, and the stability of the system under high load is ensured.

The invention provides a convolutional neural network weight mapping and pixel-level reasoning simulation method based on a memory computing architecture of a memristor, which comprises the following steps of: for any convolutional neural network input, abstracting all weight parameters of the input convolutional neural network into rectangular models with a plurality of sizes by using a mapping method, and reasonably segmenting the rectangular models to obtain a pixel-level reasoning simulation model; storing in a memristor array group; a neural network reasoning process is divided into a plurality of periods by using a simulation method, and the serial number and the row and column number of a memristor array working in each period, the output pixel value of a network layer and the scale of pixels needing to be cached and allowed to be released are simulated, so that pixel-level network full-pipeline simulation is realized. The method is suitable for any convolutional neural network, provides an important basis for hardware implementation such as on-chip cache capacity design and inter-memristor array feature map pipeline design, and has a wide application prospect.

The present invention relates to a neural network parameter optimization method and a neural network computation method and apparatus suitable for hardware implementation. The neural network parameter optimization method suitable for hardware implementation according to the present invention may include transforming an existing parameter of a neural network into a signed parameter and a magnitude parameter having a single value for each channel and generating an optimized parameter by pruning the transformed magnitude parameter. Accordingly, the present invention provides a neural network parameter optimization method and a neural network computation method and apparatus thereof, which optimize a large amount of computation and parameters of a convolutional neural network to be effective in hardware implementation, thereby achieving minimal accuracy loss and maximum computation speed.

A method and an apparatus for decoding channel codes received from a noisy communication channel are provided. The method comprises: demodulating the received channel codes to obtain a demodulated data vector; and decoding, using a compute-in-memory (CIM), the demodulated data vector to obtain one or more candidate output codewords, the demodulated data vector is decoded with a guessing random additive noise decoding (GRAND) algorithm to obtain a candidate output codeword. By leveraging CIM technique for GRAND implementation, due to the intrinsic small size of memory cells relative to logic gates, the integration of storing and computing operations (e.g. multiply-and-accumulate (MAC) operation on the input vector with the weight matrix) in memory cells enables concurrently evaluating a multitude error patterns, therefore substantially reduce the worst-case latency of GRAND hardware implementation.

The invention discloses a lattice cryptographic modular multiplication method and a modular multiplier based on an improved plantard algorithm, which eliminate the post-processing overhead of the traditional modular multiplication method by preprocessing twiddle factors in the level of the modular multiplication method. In hardware implementation, shift-addition is adopted to replace a complex multiplier, a dynamic bit width truncation technology is combined, the bit width of intermediate data is compressed from 39 bits to 21 bits, and logic resource consumption is greatly reduced, so that modular multiplication operation in a lattice password digital signature scheme can be quickly and efficiently completed.

Disclosed is a test device to test the operation of an MMC by fabricating only one or several SMs constituting the MMC testing under real-time operating conditions. The test device for a modular multi-level converter (MMC) includes a simulation model of an MMC having at least one arm to which sub modules (SMs) are serially connected, at least one test target SM among the serially connected SMs being replaced with a dependent voltage source; an arm current simulation circuit including an equivalent SM that implements the test target SM as actual physical hardware and an inverter that supplies current to the equivalent SM; and a control unit configured to control the arm current simulation circuit to correspond to an operation of the simulation model and set a voltage corresponding to a charge / discharge voltage of the equivalent SM of the arm current simulation circuit to the dependent voltage source.

A speculative decoding system may include integrated circuits (ICs), a router, and a processing unit. The ICs may implement different models that can perform different types of tasks. The router may route an input prompt, which may include one or more input tokens, to an IC based on the task to be performed using the input prompt. The IC may include hardware implementations of operators in a model. The IC may generate speculative token(s) from the input prompt by running the operators in the model. The speculative token(s) may be drafted to the processing unit. The processing unit may validate the speculative token(s) and generate output token(s) by executing another model, which may be larger than the model executed by the IC. The processing unit may validate multiple speculative tokens in parallel. Key-value pairs generated by the IC may be used by the processing unit for executing the other model.