326 results about "Hardware implementations" patented technology

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

According to the heterogeneous multi-core chip power consumption state control system and the heterogeneous multi-core chip provided by the invention, the power consumption state request of each sub power supply domain is received through the set system hardware power consumption management module, and the driving signal is sent to the corresponding sub power supply domain according to the preset hardware time sequence, so that the corresponding sub power supply domain enters the target state; generating a PMU control signal; and the power management module drives an internal voltage regulator to execute corresponding regulation operation according to the PMU control signal. A special control processor (SCP) is not needed, the system hardware power consumption management module realized by pure hardware is adopted to directly control the power consumption state of each sub power supply domain in the heterogeneous multi-core SoC, the software processing delay is eliminated, the response speed is high, the static power consumption of the power consumption management module is remarkably reduced, and the system is particularly suitable for an ultra-low power consumption scene and has a wide application prospect. And hardware-level surge current protection is realized in a multi-core power-on process.

Disclosed is a test device to test the operation of an MMC by fabricating only one or several SMs constituting the MMC testing under real-time operating conditions. The test device for a modular multi-level converter (MMC) includes a simulation model of an MMC having at least one arm to which sub modules (SMs) are serially connected, at least one test target SM among the serially connected SMs being replaced with a dependent voltage source; an arm current simulation circuit including an equivalent SM that implements the test target SM as actual physical hardware and an inverter that supplies current to the equivalent SM; and a control unit configured to control the arm current simulation circuit to correspond to an operation of the simulation model and set a voltage corresponding to a charge / discharge voltage of the equivalent SM of the arm current simulation circuit to the dependent voltage source.

The invention discloses a 3D Gaussian splash rendering optimization method based on a Unity engine in VR, and relates to the technical field of computer graphics. PLY point cloud files are converted into SOG high-compression formats containing multi-level LOD information, after low-transparency Gaussian points are removed, Morton coding sorting is carried out on the center coordinates of the Gaussian points, and then the 3D Gaussian splash rendering optimization method based on the Unity engine in VR is realized. The method comprises the following steps: constructing an octree spatial index containing a spatial bounding box and multiple LOD data, removing Gaussian points in a grading manner according to a camera distance, selecting an LOD hierarchy, carrying out deep barrel sorting on visible Gaussian points, executing drawing by taking a barrel as a unit, and combining near-to-far sorting, an improved mixed equation and screen space edge removal and amplification operation to obtain a target image. According to the method, through multi-dimensional optimization such as loading, space elimination and rendering, the loading efficiency of the VR equipment is improved, the rendering burden is reduced, Tile-Based hardware is adapted, and smooth operation of 3D Gaussian splashing on the VR all-in-one machine is realized.

The invention discloses a chip mounter service logic control method and system based on an abstract component and a medium, and relates to the technical field of industrial automation control, and the system comprises a command cache queue module which is configured to receive and cache commands issued from an upper layer; the command parameter verification module is configured to verify the legality of the command parameters cached by the command cache queue module in real time; the user command monitoring module is configured to distribute the commands passing the verification to different units according to command types; and the equipment control flow monitoring module is configured to monitor a command execution state of a hardware layer, and if the command execution state is not received within a specified time, an overtime event is reported to the user command monitoring module and a system is coordinated to enter a safe state. According to the scheme, a unified business logic control center and an abstracted component control model are constructed, component cooperative control logic is completely stripped from specific hardware implementation, and centralization, closed-loop and uniqueness of command execution are achieved.

The invention relates to the technical field of pulse neural network computing hardware, in particular to a neural network computing circuit of a pulse self-attention mechanism. According to the method, invalid or inefficient pulse events are dynamically screened through the hardware mask module, the operation number is remarkably reduced, and calculation path delay and logic resource occupation are reduced; meanwhile, in order to adapt to novel networks with binary architecture such as QKFormer, calculation and storage of a V matrix are eliminated, and storage resources and calculation resources are further reduced; in addition, the event coding module only generates active neuron events, and input sparsity is achieved. A configurable IF neuron model is adopted, exponential operation is avoided, hardware implementation is facilitated, and the method is suitable for binary network deployment. The modular architecture can support function extension, assembly line and parallel work; and the parallelism degree of the design can be determined according to the actual data pulse distribution rate. Event driving and mask pruning are combined, so that the overall computing resources of the circuit are greatly reduced, and the power consumption is reduced.

The invention relates to a configurable decompression circuit supporting COO and Bi tmap compression algorithms, and belongs to the field of integrated circuits. According to the hybrid compression method suitable for the circuit, after sparseness analysis is carried out on weight matrixes of all layers of a neural network, COO compression based on a coordinate type sparse matrix or Bitmap compression based on bitmap masks is selected according to the sparseness characteristics of different layers, so that the storage space is optimized; comprising a control module, a first selector, a second selector, a bitmap description memory, a coordinate index memory, a numerical memory, a converter, a COO decoder and a decompression data storage module, decoding of two compression formats of COO and Bi tmap can be supported, and the operation efficiency and flexibility of a neural network processor are improved. The method effectively reduces the weight storage demand of the neural network, enhances the adaptability of the compression algorithm, and is suitable for hardware implementation of an efficient neural network model.

The application discloses a pixel counting method and device for a dashed line mask calculation and a storage medium, and specifically comprises: pixel counting schemes for the dashed line mask calculation in a non-MSAA scene and in an MSAA scene are respectively given. The application has simple calculation mode, reduces mask calculation complexity, is beneficial to hardware implementation, saves calculation time delay and reduces power consumption, and simultaneously solves problems and defects of an existing scheme in the MSAA scene.

The invention discloses a hardware acceleration method and system for a ZSTD data compression algorithm based on an FPGA. Unified hardware implementation and collaborative optimization are carried out on three key links of LZ77 character matching, Huffman coding and finite state entropy coding in the ZSTD data compression algorithm. According to the system, a multi-channel parallel LZ77 character matching hardware architecture is adopted, and character matching is executed on continuous positions in a plurality of parallel windows at the same time. A modular design and a deep pipeline structure are adopted, and a buffer and pipeline mechanism is introduced among modules such as an LZ77 matching module, a Huffman coding module and a finite state entropy coding module. The 375MB / s compression throughput can be achieved under the 100MHz clock frequency, the compression speed is remarkably increased while the compression ratio is guaranteed, and the method is suitable for scenes with high requirements for compression performance of data centers, edge computing and embedded systems and has high practicability and popularization value.

The invention discloses a borrowing type successive approximation analog-to-digital converter adopting a back propagation neural network for calibration. The borrowing type successive approximation analog-to-digital converter comprises a system composed of a positive and negative capacitance digital-to-analog converter adopting a three-stage split bridge type capacitor array, a bootstrap sampling switch, an automatic return-to-zero comparator, an SAR logic control unit, an original-to-binary module and a BPNN calibration engine. Bootstrap sampling switches are respectively arranged at the tail ends of the positive and negative capacitance digital-to-analog converters, a comparator is connected with the output ends of the two, and the output is connected with an SAR logic control unit; the original-to-binary module converts the code generated by the SAR logic control unit into a binary code; and a BPNN calibration engine receives the code and performs calibration calculation by using a trained back propagation neural network model. By implementing the converter disclosed by the invention, hardware implementation can be simplified while high performance is ensured, so that the ADC realizes efficient and accurate signal conversion under a 180-nanometer BCD process, and power consumption and cost are reduced.

The present disclosure relates to a computer- or hardware-implemented method (100) for identifying entities, comprising the steps of: a) providing (110) inputs from a plurality of sensors to a network of a plurality of nodes; b) generating (120) an activity level by each node of the network based on the inputs from the plurality of sensors; c) comparing (130) the activity level of each node to a threshold level; d) setting (140) the activity level for each node to a preset value or retaining the generated activity level based on the comparing step; e) calculating (150) a total activity level as the sum of all activity levels of the nodes of the network; f) repeating (160) steps a)-e) until a local minimum in the total activity level is reached; and g) once a local minimum in the total activity level is reached, utilizing (170) the distribution of activity levels at the local minimum to identify measurable entity characteristics. The present disclosure further relates to a computer program product and an entity identification device (300).

Provided are a hardware implementation method and a hardware implementation device of a Montgomery algorithm. A REDC operation of the Montgomery algorithm includes a first multiplication operation, a second multiplication operation, a third multiplication operation, a fourth multiplication operation, and a subtraction operation, the third multiplication operation depends on a result of the second multiplication operation, a clock cycle for the REDC operation includes a first clock cycle for multiplication operation and a second clock cycle for subtraction operation, the hardware implementation method includes: replacing the second clock cycle with an additional clock cycle for multiplication operation by adjusting a calculation flow of the REDC operation; performing the first multiplication operation, the second multiplication operation, and the third multiplication operation by a first multiplier, wherein the first multiplication operation includes a first multiplier and a second multiplier; and performing the fourth multiplication operation by a second multiplier. The hardware implementation method can save multiplier resources without reducing hardware performance.

The application discloses a continuous resonator network computing method based on a resistive memory array, and belongs to the fields of semiconductors, analog computing and integrated circuits. The application sequentially decomposes resonator network computing into three parts of logic computing, matrix-matrix-vector multiplication operation and sign taking computing, and sequentially connects a feedback loop formed by a logic element, a resistive memory array and an operational amplifier to realize hardware, takes a voltage corresponding to a to-be-decomposed hyper vector as input, and obtains a voltage of a corresponding decomposition signal at an output end after the circuit is stable, so that self-convergent resonator network computing in a continuous time domain is realized. Compared with existing resonator network computing implementation schemes, the application can fully exert the performance advantages of analog computing, does not need discrete iteration and data transfer, thereby reducing hardware overhead and operation complexity, and greatly improving speed, energy efficiency and area efficiency.

The embodiment of the invention discloses a data transmission method, a data transmission device and a data transmission system, which can be compatible with the existing 400ZR +, 800ZR and 800ZR + DSP (Digital Signal Processor) framing scheme, are more beneficial to hardware implementation, and can also be suitable for scenes adopting multi-wave or multi-subcarrier transmission in the future, such as 800Gbps multi-subcarrier transmission adopting QPSK (Quadrature Phase Shift Keying) modulation, 1.2 Tbps multi-subcarrier transmission adopting 16QAM (Quadrature Amplitude Modulation) modulation and 1.6 Tbps multi-subcarrier transmission adopting 16QAM modulation. And even transmission scenes with higher speed such as 2.4 T / 3.2 T and the like can be realized. The method comprises the steps that W data frames are sent, in one polarization direction, the number of symbols included in any data frame is 87552, each data frame comprises 12 subframes, the number of symbols included in each subframe is 7296, and W is an even number.

This application belongs to the field of channel coding technology. This application provides a WSC-assisted encoding and decoding method for PC-Polar codes. The embodiments disclosed herein can be used in any communication system employing PC-Polar codes with minimal impact on the overall design of the communication system. By assisting in the verification of multiple candidate paths, the correct path can be identified more accurately, resulting in additional coding gain compared to PC-Polar codes in simulations. The PC-Polar code is endowed with link-layer frame error detection and indication functions, allowing the system to definitively determine whether the decoding result is correct, thus enhancing the reliability of the communication system. The introduced WSC coding has low code rate loss overhead, low computational complexity, and is easy to implement in hardware, achieving a good balance between performance gain and overhead.

The invention discloses an Ethernet data transmission method and device, equipment and a storage medium, and relates to the technical field of communication, the method is applied to a receiving end, and the method comprises the following steps: receiving code stream data obtained by inserting a protection frame code block into a coding code stream of a physical coding sub-layer by a sending end from a physical link; performing framing processing on the code stream data to obtain frame description information of the lossless protection frame; performing alignment processing on the lossless protection frames on different physical links based on the frame description information; and eliminating redundant frames from the aligned lossless protection frames according to frame serial numbers in the frame description information to obtain lossless protection frames with continuous frame serial numbers, and sending the lossless protection frames to the downstream. By sinking Ethernet service lossless protection from a data frame level to a code block level of a physical coding sub-layer, service protection overhead is allocated to a code stream with finer granularity, the effective bandwidth utilization rate of data transmission is remarkably improved, the processing frequency is reduced from a high frequency of the data frame level to a low frequency of the code block level, and the hardware implementation difficulty is reduced.

The invention discloses an AES encryption and decryption hardware implementation method based on an RISCV vector encryption and decryption expansion architecture, and belongs to the technical field of data encryption, and the method comprises the steps that an RISCV instruction set carries out vector expansion on AES encryption and decryption, in the AES encryption process, an initial round corresponds to a vaesz.vs instruction, a middle round corresponds to a vaesem.[ vv, vs] instruction, a final round corresponds to a vaesef.[ vv, vs] instruction, in the AES decryption process, the initial round corresponds to the vaesz.vs instruction, and in the AES decryption process, the middle round corresponds to the vaesef.[ vv, vs] instruction. The middle round corresponds to a vaesdm. [vv, vs] instruction, and the final round corresponds to a vaesdf. [vv, vs] instruction, so that the area of a chip can be reduced, the cost is reduced, the flexibility, modularization and extensible architecture design of hardware and software are enhanced, different platforms from embedded computing to high-performance computing can be easily adapted, and a solid foundation is provided for evolution and customization of a future cryptographic algorithm; and the encryption processor architecture is promoted to develop towards a more efficient, more open and more customizable direction.

An exemplary sliding window scheduling method and system are disclosed. The exemplary sliding window scheduling method and system can schedule multiple packets in a given scheduling frame with a sliding window scheduling frame. The scheduling operation can be performed using bitmap operators and can achieve a lowest time complexity of O(1) per matching computation and per port using distributed parallelization hardware. The exemplary sliding window scheduling method and system can be performed in the context of a queue-proportional scheduler (QPS) as well as iSLIP. In alternative embodiments, the SW-QPS operation can be performed in a batching window rather than in a sliding window.

According to the information processing method and device, a first LDPC base matrix can be divided into two types of G * G sub-matrixes, the row weight of each G * G sub-matrix is not larger than 1, and the column weight of each G * G sub-matrix is not larger than 1, so that the hardware implementation complexity is low, and a longer code length can be supported under the same hardware. Moreover, the first region of the first LDPC basis matrix comprises the second type of sub-matrixes with at least two element arrangement modes, so that interleaving can be realized, and long codes are supported. Moreover, the first region of the first LDPC basis matrix comprises a second type of sub-matrix in an element arrangement mode, so that the gain in the aspect of decoding parallelism can be provided.

The application discloses a Spike-BP on-chip learning method and system based on a Ca-LIF neuron model and a processor, wherein a trainable linear leakage parameter and a positive and negative double-channel pulse transmitter mechanism based on calcium gating are adopted; for the Ca-LIF neuron model, a linear leakage operation can be realized only by subtraction, complex leakage compensation operations can be avoided when a gradient matrix is solved, hardware implementation complexity is reduced, a large amount of calculation resources of subsequent hardware design is saved, and the performance of pulse neural network training is improved.

FIELD: computing technology.SUBSTANCE: invention can be used for hardware implementation of the evaluation of random number generators (RNG) based on repeating codes in the output sequence from the RNG. A random number generator quality analyser includes a shift register, a decoder, a comparison unit, a counter, a logarithm calculator, a divider, and a square root calculator, wherein the first input of the device is connected to the input of the shift register, the output of which is connected to the first input of the comparison unit, the second input of the device is connected to the input of the decoder, the output of which is connected to the second input of the comparison unit, the output of which is connected to the input of the counter, the output of which is connected to the input of the logarithm calculator and to the input of the divider, built on the basis of the CORDIC algorithm, the output of which is connected to the input of the square root calculator, the output of which is connected to the output of the device, wherein the output of the logarithm calculator is connected to the input of the divider.EFFECT: expanding the information field for assessing the quality of the RNG operation during hardware implementation.2 cl, 5 dwg

The invention belongs to the technical field of hardware design, and provides a sharing operation method, system and equipment of a network acceleration unit and a medium, and the method comprises the step of configuring a shared general register, an exclusive general register and an exclusive special register group for multiple hosts in a single network acceleration unit. Each host accesses the register through the low-speed bus based on the unique identifier. And the acceleration unit performs data interaction with each host through a high-speed bus according to the configuration of the register. When the host operation is processed, the management message and the data transmission message are distinguished by judging whether the basic communication resource register group is accessed or not, and high-order modification and resource mapping are carried out on a load data address in the data transmission message. When an external data packet is received, a target host is determined through analysis and address matching, and resource identifier mapping and data access are carried out. According to the invention, each host is ensured to have independent communication resources and data channels, the complexity and the cost of hardware implementation are reduced, and the resource utilization rate and the system expansibility are improved.

Innovations in range asymmetric numeral systems (“RANS”) encoding and decoding are described herein. Some of these innovations relate to hardware implementations of RANS decoding that organize operations in two stages, which can improve computational efficiency of RANS decoding. Other innovations relate to adapting RANS encoding / decoding to different distributions or patterns of values for symbols. For example, RANS encoding / decoding can be adapted by switching a default symbol width (number of bits per symbol), adjusting the symbol width on a per-fragment basis for different symbol fragments, switching between different static probability models on a per-fragment basis for different symbol fragments, and / or selectively flushing (or preserving) a state of a RANS decoder on a per-fragment basis for different symbol fragments. In many cases, such innovations can improve compression efficiency while also providing computationally efficient performance.

The application discloses a code rate control method for inhibiting super-large I frame. According to the coding state of a current video sequence, the upper limit value of the coding bit number of the I frame which will not cause code rate control abnormality is calculated. According to the actual coding bit number, the quantization parameter and the intra-frame coding complexity of the previous coded I frame, in combination with the upper limit value of the coding bit number and the intra-frame coding complexity of the to-be-coded I frame, the lower limit value of the quantization parameter of the to-be-coded I frame is calculated. According to the quantization parameter of the previous coded P frame or B frame, the quantization parameter of the to-be-coded I frame which has inhibiting effect on the breathing effect is calculated. The larger value of the lower limit value of the quantization parameter of the to-be-coded I frame and the quantization parameter of the to-be-coded I frame which has inhibiting effect on the breathing effect is selected as the quantization parameter of the to-be-coded I frame, which is used in the actual coding process of the to-be-coded I frame. The application takes the video frame level quantization parameter as the operation core of the code rate control algorithm, which is more suitable for hardware implementation.

The invention relates to the technical field of vehicle-mounted Ethernet diagnostic message monitoring, in particular to an automatic monitoring method for a vehicle-mounted Ethernet diagnostic message, which comprises the following steps of: connecting a tested controller or a real vehicle through an industrial personal computer (carrying Wireshark software) and a vehicle-mounted Ethernet converter, installing a Lua environment and writing a script; protocol value mapping, interpreter registration, field definition and analysis function logic are achieved through scripts, Wreshark captures messages in real time to automatically analyze protocol levels, abnormal messages are marked, and data can be arranged through Python; according to the automatic monitoring method for the vehicle-mounted Ethernet diagnosis message, special software and hardware are not needed, full-process automation is achieved, monitoring efficiency and analysis accuracy are improved, protocol compatibility is expanded, the use threshold is reduced, cost is optimized, and the monitoring requirement of the vehicle-mounted Ethernet from research and development to after-sale is met.

Encryption system with an application-specific integrated circuit (ASIC) which has a permanent memory for the non-volatile storage of the operating system (OS) of a processor and software modules for encrypting the data memory of the processor and which has a hardware-implemented encryption algorithm, characterized in that a security module (SM) is integrated in the ASIC for autonomous booting of the operating system (OS), consisting of: - a symmetric cryptosystem (SK) for processing symmetric keys, - an asymmetric cryptosystem (AK) for the use of public and private keys, - a module for generating cryptographic hash functions (KH), - a module for the secure exchange of keys using hardware-implemented key exchange protocols (SP), - a key storage (SS) for the secure storage of root keys (WS), which are protected by appropriate measures in the physical structures of the ASIC and - a key management system (SMS) for the secure introduction of authenticated-encrypted key packets, and that the security module (SM) communicates with a central processing unit (CPU) via a communication interface (CS1), and that the central processing unit (CPU) communicates with at least one internal storage (IS) and one external storage (ES), as well as with at least one internal persistent storage (IP) and one external persistent storage (EP), such that the operating system (OS) is loaded by a second-stage bootloader (SSB) stored in the external persistent storage (EP), and then the operating system (OS) loads the applications, the second-stage bootloader (SSB) itself being decrypted and loaded by a first-stage bootloader (FSB) stored in the internal persistent storage (IP), and a public key (PUBOS) to verify the operating system (OS).and a symmetric key (KOS) to decrypt the operating system (OS), and that the contents of the internal memory (IS) and the external memory (ES) are decrypted by the security module (SM) during read accesses by the central management unit (CMU) or other modules integrated on the ASIC, and re-encrypted during write accesses by the same.

The invention discloses a waveform recognition implementation method based on waveform template matching of an FPGA (Field Programmable Gate Array), which adopts a flexible template configuration mechanism to support self-defined waveform recognition, does not need to depend on deep learning and large-scale data training, and meanwhile, through a configurable frequency parameter and a dynamic zero calibration mechanism, the waveform recognition can be realized. And the method is suitable for different precision, frequency range and direct current bias scenes. On the hardware implementation level, the parallelism and assembly line characteristics of the FPGA are fully exerted, an n-path parallel processing architecture is constructed, a lightweight result processing strategy of intra-group iteration updating to inter-path preferential selection is matched, storage resource occupation is remarkably reduced, and the recognition speed and reliability are guaranteed through a dual-mode judgment mechanism of rapid matching and full-quantity matching. According to the method, the defects of a traditional template matching method are overcome, meanwhile, the problems that a deep learning scheme is difficult to deploy, high in computing power requirement and high in data dependence are solved, and the practical value of the system in multiple scenes is remarkably improved.

The invention discloses an encoder protocol conversion method and module applied to a servo driving device, and belongs to the technical field of servo control, and the method comprises the steps: constructing and storing a simulation algorithm which is used for converting first state data, obtained through A-Format protocol conversion, of an absolute value encoder into first state data; converting and simulating second state data output by the SSI encoder according to a preset variable parameter; obtaining first state data output by the current encoder and a preset variable parameter, generating second state data, and sending the second state data to the servo driver supporting the SSI protocol; the preset variable parameters are used for configuring the updating frequency of the state data and the cutting bit number of the position data and setting a single-circle or multi-circle working mode, the compatibility of a traditional servo driver to an encoder supporting an A-Format protocol can be effectively expanded through the scheme, a protocol conversion algorithm is achieved through hardware, and the reliability of the servo driver is improved. Robustness is high, delay is low, data transmission is stable, and power consumption is low; encoder parameters can be configured and stored, and compatibility with all absolute value encoders in the market is high.

The application discloses a Monte Carlo metric SC-Flip decoding method based on LLR absolute value interval, and the method comprises the following steps: according to a GA construction algorithm, a bit channel is divided into information bits and frozen bits; LLR absolute value intervals are divided into subintervals, and error probabilities of the subintervals are obtained through Monte Carlo simulation; Monte Carlo metrics are simplified, and the simplified Monte Carlo metric values are calculated according to the error probabilities of the subintervals; SC decoding is performed according to root node LLR values received from a receiver, if CRC check is successful, decoding is ended, otherwise leaf node LLR values are arranged in descending order of the Monte Carlo metric values, flip indexes of the first T Monte Carlo metric values are obtained; unflipped index positions are found from the T flip index positions in sequence to redecode, if CRC check is successful or T times of decoding are completed, decoding is ended. The simplified Monte Carlo metric only needs to perform addition operation, and is convenient for hardware implementation; and error correction performance is not lost; and at low flip times, error correction performance is obviously improved.

The application provides a decoding method, an encoding method, a device, a chip and a computing device. The method comprises the following steps: a decoding device acquires a first matrix, and then decodes a first code word vector according to the first matrix to obtain a decoding result. The first matrix is a 0-1 matrix representing elements in a second matrix on a polynomial ring. The second matrix is a check matrix on a finite field 2q, and the number of rows is r and the number of columns is n. A first polynomial corresponding to the polynomial ring is a q-th irreducible polynomial on a binary field. The number of 1s in the first matrix is less than the number of 1s in the 0-1 matrix representation of the second matrix. The first code word vector comprises k information code elements and r check code elements, and n=k+r. Each code element comprises q data units, and each data unit comprises at least one bit. The scheme can effectively reduce the hardware implementation complexity and cost of RS encoding and decoding.