539 results about "Hardware implementations" patented technology

The invention provides a power domain control software architecture and a controller thereof, the software architecture comprises an application layer developed based on an AUTOSAR standard, a runtime environment and a basic software layer, the application layer comprises a plurality of modularized software components, the software components package service logic functions of the controller to be integrated, the software components are provided with an AUTOSAR-based ARXML file definition interface, and the AUTOSAR-based ARXML file definition interface is used for defining the service logic functions of the controller to be integrated. According to the method, the interface compatibility can be improved, seamless integration of application layers across controllers can be realized, and the development parallelism is enhanced by kernel deployment of independently packaged software components according to the real-time performance of functions. The runtime environment generates an inter-core communication agent code, constructs a virtual bus and routes a service request of an application layer component to the basic software layer, and the basic software layer provides system-level service for the application layer through a virtual bus interface of the runtime environment, so that the application layer does not need to directly operate hardware, software and hardware decoupling is realized, and the service performance of the application layer is improved. And smooth realization of software fusion and integration is promoted.

The invention discloses a signal sampling method for a multi-channel signal converter, and the method comprises the steps: carrying out the synchronous and parallel sampling of an analog signal source according to a multi-channel signal collection module, so as to obtain multi-channel original signal sequence data; performing inter-channel time delay calibration and amplitude normalization processing on the multichannel original signal sequence data to obtain a calibrated multichannel signal data set; the invention relates to the technical field of signal processing. According to the signal sampling method for the multi-channel signal converter, the multi-channel signal converter improves the data consistency and accuracy through the technologies of synchronous sampling, time delay calibration, amplitude normalization and the like, meanwhile, precision adjustment of self-adaptive filtering, dynamic threshold segmentation and entropy driving is adopted, signal interference and abnormal data are reduced, and the signal quality is improved. The non-uniform resampling and compression technology is adopted to optimize the storage and transmission efficiency, key data is ensured to be transmitted preferentially, hardware is accelerated through an FPGA, and the real-time performance and the processing capacity of the system are improved.

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

This disclosure describes supporting distributed graphics and compute engines in a multi-dielet processor, such as, for example, a multi-dielet graphics processing unit (GPU), architectures and synchronization in such architectures. Each multi-dielet processor includes a hardware-implemented remapping capability and / or a hardware-implemented memory barrier capability.

According to the heterogeneous multi-core chip power consumption state control system and the heterogeneous multi-core chip provided by the invention, the power consumption state request of each sub power supply domain is received through the set system hardware power consumption management module, and the driving signal is sent to the corresponding sub power supply domain according to the preset hardware time sequence, so that the corresponding sub power supply domain enters the target state; generating a PMU control signal; and the power management module drives an internal voltage regulator to execute corresponding regulation operation according to the PMU control signal. A special control processor (SCP) is not needed, the system hardware power consumption management module realized by pure hardware is adopted to directly control the power consumption state of each sub power supply domain in the heterogeneous multi-core SoC, the software processing delay is eliminated, the response speed is high, the static power consumption of the power consumption management module is remarkably reduced, and the system is particularly suitable for an ultra-low power consumption scene and has a wide application prospect. And hardware-level surge current protection is realized in a multi-core power-on process.

The invention relates to a random calculation processing unit and method based on a self-adaptive compensation mechanism, and the method employs a self-adaptive compensation core formed by solidifying a lightweight neural network to replace a conventional solidification compensation rule, and the self-adaptive compensation core can carry out the random calculation according to two operands participating in multiplication. And an optimal compensation parameter is dynamically predicted in real time for compensation. According to the scheme, the calculation error of random calculation is accurately, continuously and individually compensated in a data driving mode, and hardware implementation is performed by adopting a constant coefficient multiplier technology, so that the self-adaptive compensation core has extremely low area and power consumption overhead in hardware. Compared with the prior art, the method has the advantages that the fidelity of random calculation can be greatly improved on the premise that the hardware cost is not remarkably increased, and a new effective way is provided for constructing a high-performance and high-energy-efficiency random calculation neural network accelerator.

Circuitry for performing neural-network calculations includes a plurality of compute circuits, arranged in parallel with respective inputs and outputs, to receive function arguments for a node of a neural network on their respective inputs, compute values of a plurality of activation functions using the function arguments, and provide the values on their respective outputs. Each compute circuit of the plurality of compute circuits is to compute the values of a respective activation function of the plurality of activation functions. The circuitry also includes a multiplexor to select between the respective outputs of the plurality of compute circuits and to provide the values on a selected output as activation-function values for the node of the neural network, based on an activation-function selection signal.

The invention provides an instruction pipeline processing method of a processor and the processor. A processor includes: a control module; the control module is set to execute the branch instruction speculatively according to the branch prediction direction when detecting that the first instruction subjected to initial decoding is the branch instruction, and execute the branch instruction if detecting that the second instruction subjected to initial decoding is the function call instruction or the function return instruction before the speculation execution result of the first instruction is generated. If yes, pausing all operations after the instruction processing assembly line performs initial decoding on the second instruction, and blocking the instruction fetching operation of the instruction processing assembly line on the next instruction until a speculation execution result of the first instruction is obtained; wherein the operation after the initial decoding comprises the step of carrying out a push-in or push-out operation of a return address stack (RAS) according to the second instruction. According to the technical scheme, the pollution risk caused by speculative execution of the branch instruction to the return address stack can be shielded, so that the hardware implementation logic of the return address stack is simplified, and the circuit area and power consumption are saved.

The invention discloses a CXL protocol extension method, device and system based on the Ethernet. The method comprises the following steps of: carrying out long-distance expansion interconnection on a CXL (Compute Express Link) protocol by using Ethernet as a physical transmission medium; by bearing the CXL protocol on the Ethernet, the range of memory pooling is expanded from the rack level to the whole data center (kilometer level), and the potential of the CXL technology is thoroughly released; through protocol translation, label management and flow control realized by pure hardware, an operating system kernel and a software protocol stack are bypassed, so that the end-to-end memory access delay is far lower than that of any software-based network storage scheme, and a reliable request-response tracking and timeout retransmission mechanism is realized through a hardware label manager. By distinguishing the control flow and the data flow, differentiated QoS guarantee is provided for different types of memory flows, and the stability of the system under high load is ensured.

Disclosed is a test device to test the operation of an MMC by fabricating only one or several SMs constituting the MMC testing under real-time operating conditions. The test device for a modular multi-level converter (MMC) includes a simulation model of an MMC having at least one arm to which sub modules (SMs) are serially connected, at least one test target SM among the serially connected SMs being replaced with a dependent voltage source; an arm current simulation circuit including an equivalent SM that implements the test target SM as actual physical hardware and an inverter that supplies current to the equivalent SM; and a control unit configured to control the arm current simulation circuit to correspond to an operation of the simulation model and set a voltage corresponding to a charge / discharge voltage of the equivalent SM of the arm current simulation circuit to the dependent voltage source.

A speculative decoding system may include integrated circuits (ICs), a router, and a processing unit. The ICs may implement different models that can perform different types of tasks. The router may route an input prompt, which may include one or more input tokens, to an IC based on the task to be performed using the input prompt. The IC may include hardware implementations of operators in a model. The IC may generate speculative token(s) from the input prompt by running the operators in the model. The speculative token(s) may be drafted to the processing unit. The processing unit may validate the speculative token(s) and generate output token(s) by executing another model, which may be larger than the model executed by the IC. The processing unit may validate multiple speculative tokens in parallel. Key-value pairs generated by the IC may be used by the processing unit for executing the other model.

This invention discloses a bitrate control method at the image block level for P-frames and / or B-frames. Step S1: Obtain the inter-frame coding mode candidates and their prediction costs for each image block to be encoded. Step S2: Select the minimum prediction cost to characterize the inter-frame coding complexity of the image block to be encoded; use the sum of the inter-frame coding complexities of all image blocks within a video frame as the inter-frame coding complexity of that video frame. Step S3: Calculate the target number of coding bits for each image block to be encoded within the P-frame or B-frame to be encoded. Step S4: Calculate the Lagrange multipliers for the image block to be encoded within the P-frame or B-frame to be encoded. Step S5: Perform video encoding on the image block to be encoded, and then adjust the target number of coding bits for the next image block to be encoded within the P-frame or B-frame to be encoded. This invention has low hardware overhead and low implementation cost; it does not introduce a large number of complex floating-point operations, reducing the difficulty and cost of hardware implementation.

The invention relates to a matrix decomposition device and method based on a memristor cross array, which are suitable for efficient hardware implementation of singular value decomposition (SVD), the memristor cross array receives a conductance value mapped by a Grubrum matrix constructed by a to-be-decomposed matrix and a bit line input voltage converted by a bit line column vector, and outputs a corresponding current; converting the corresponding current into a voltage vector; performing normalization processing on the voltage vector to obtain a normalized vector; judging whether convergence occurs or not; performing normalization processing on the steady-state voltage vector to obtain a final output vector; and according to the final output vector, main characteristic values are extracted based on a first normalization circuit, and main singular values and corresponding singular matrixes are calculated. Compared with the prior art, the high parallel computing characteristic of the memristor cross array is utilized, efficient operation and hardware acceleration of matrix decomposition are achieved, the method has the advantages of being low in power consumption, high in speed and good in expansibility, and the method is suitable for application scenes such as artificial intelligence, signal processing and large-scale matrix operation.

The invention discloses a 3D Gaussian splash rendering optimization method based on a Unity engine in VR, and relates to the technical field of computer graphics. PLY point cloud files are converted into SOG high-compression formats containing multi-level LOD information, after low-transparency Gaussian points are removed, Morton coding sorting is carried out on the center coordinates of the Gaussian points, and then the 3D Gaussian splash rendering optimization method based on the Unity engine in VR is realized. The method comprises the following steps: constructing an octree spatial index containing a spatial bounding box and multiple LOD data, removing Gaussian points in a grading manner according to a camera distance, selecting an LOD hierarchy, carrying out deep barrel sorting on visible Gaussian points, executing drawing by taking a barrel as a unit, and combining near-to-far sorting, an improved mixed equation and screen space edge removal and amplification operation to obtain a target image. According to the method, through multi-dimensional optimization such as loading, space elimination and rendering, the loading efficiency of the VR equipment is improved, the rendering burden is reduced, Tile-Based hardware is adapted, and smooth operation of 3D Gaussian splashing on the VR all-in-one machine is realized.

The invention discloses a low-delay hardware implementation method and device for communication between CPUs, and relates to the technical field of computers. The method comprises the following steps: receiving initialization configuration information from a sending CPU (Central Processing Unit), including an initial address and a space size of a memory of the sending CPU and an initial address and a space size of a memory of a receiving CPU; and monitoring a sending tail pointer updated by the sending CPU, and determining whether to read the to-be-sent data from the internal memory of the sending CPU to the internal cache of the hardware communication module based on the initialization configuration information, the sending tail pointer and a sending head pointer maintained by the hardware communication module. And monitoring a receiving head pointer updated by the receiving CPU, and determining whether to write the to-be-written data in the internal cache into the memory of the receiving CPU based on the initialization configuration information, the receiving head pointer and a receiving tail pointer maintained by the hardware communication module. And the hardware communication module transmits data between the sending CPU memory and the receiving CPU memory in a direct memory access mode.

The invention belongs to the field of switch chips, and relates to a hardware and software combined PCIE address translation and networking design device and method, the hardware and software combined PCIE address translation and networking design device comprises an address translation unit, a built-in CPU and firmware and a TLP transceiving unit, the address translation unit comprises a control register and an address or BDF translation module for implementing TLP address or BDF translation; the firmware is used for completing the simulation of the iEP, and the simulation method is that software is used for completing the response to a received configuration request TLP, so that a DSP and an EP are simulated; and the TLP receiving and transmitting unit connects the built-in CPU to a switching network, so that the built-in CPU receives and transmits a TLP data packet. According to the PCIe switching chip, a tree topology structure of a traditional PCIe switching chip can be broken through, and any needed network topology structure can be flexibly connected through software configuration; a plurality of hosts and devices can be connected at any port as required; the required iEP is realized by using internal firmware, the function of the iEP can be realized by more flexible programming, and the design cost is reduced compared with the method for realizing the iEP by using hardware.

The invention is notably directed to a hardware system (1) designed to implement an artificial neural network (ANN). The hardware system basically includes a neural processing apparatus (15), e.g., involving as crossbar array structure, one or more lookup table circuits (17), and one or more processing units (18). The neural processing apparatus is configured to implement M artificial neurons, where M≥1. The lookup table circuits are configured to implement a lookup table (LUT). The system further includes M′ processing units, where M≥M′≥1. Each processing unit is connected by at least one neuron, in order to be able to access a first value outputted by each connected neuron. In addition, each processing unit is connected to a LUT circuit, in order to efficiently access parameter values of a set of parameters from the LUT. Finally, each processing unit is configured to output a second value, corresponding to a value of a mathematical function taking said first value as argument. The mathematical function is otherwise determined by the set of parameters, the parameter values of which are accessed by each processing unit from the LUT, in operation. I.e., the mathematical function is defined (and thus determined) by a set of parameters, the values of which are efficiently retrieved from the hardware-implemented LUT. This results in a substantial acceleration of the computations of the function outputs, beyond the acceleration that may already be achieved within the neural processing apparatus and the processing units themselves. As a result, the neuron outputs can be more efficiently processed, prior to being passed to a next neuron layer. The invention is further directed to a method of operating such a hardware system.

The invention relates to the field of video coding, and provides a coding mode determination method and device, electronic equipment, a storage medium and a program product. The method comprises the following steps: in response to acquiring coefficients of a group included in a transformation block in a video frame, starting to perform coding cost calculation on the group through all the coefficients when all the coefficients included in any group are acquired, and performing coding cost calculation of a plurality of groups in the transformation block in parallel; wherein the transform block comprises a plurality of groups, each group comprises a plurality of coefficients, and the coding cost of the group comprises the cost that the group is not coded and the cost that the group is coded in at least one coding mode; and according to the calculated coding cost of the plurality of groups, determining the groups for coding in the transform block and the coding mode of the groups for coding. According to the method disclosed by the embodiment of the invention, the parallel computing degree of hardware is improved, and the complexity and time delay of hardware implementation are reduced.

The invention relates to a signal detection method, device and equipment, a medium and a product. The method comprises the following steps: acquiring a target receiving signal to be detected and a Monte Carlo tree corresponding to a transmitting signal; under the condition that the current node in the Monte Carlo tree is completely expanded, for each child node of the current node, shifting processing is carried out based on the number of access times of the child node, the exploration value of the child node is determined, and the optimal child node of the current node is determined based on the reward value and the exploration value of the child node. Adding the optimal child node into a current search path corresponding to the current iterative search process, taking the optimal child node as a new current node until the current search path is searched, and determining a reward value corresponding to each node in the current search path; and determining a target transmitting signal corresponding to the target receiving signal based on the reward value of each node in the Monte Carlo tree when a preset iteration end condition is satisfied. By adopting the method, the hardware implementation complexity can be reduced.

The invention discloses a data acquisition method, device and system, a chip and electronic equipment, and relates to the technical field of wireless communication, node data acquisition of a communication baseband chip can be realized through hardware, the method comprises the following steps: receiving first frame data and second frame data, the first frame data and the second frame data being continuous data frames; storing the first frame data in a first storage space; and in response to reading at least part of the first frame data, storing the second frame data in a second storage space which is not overlapped with the first storage space. In this way, software participation can be reduced, system overhead can be reduced, and power consumption of system operation can be saved. And for two continuous frames of data, the storage spaces are not overlapped, so that the risk of data coverage caused by software reset is avoided, the error risk caused by excessive intervention of software is released, and the real-time performance of the system is remarkably improved.

An integrated circuit (IC) device may implement a speech recognition model with a transformer-based architecture. The IC device may include an embedder unit, etched mind unit(s), a layer normalizer unit, a sampler unit, and a flow control unit. The embedder unit may be a hardware implementation of an embedder in the model. The etched mind unit(s) may be a hardware implementation of matrix multiplications and additions in the model. The layer normalizer unit may implement a layer normalizer in the model. The sampler unit may implement a sampler in the model. The sampler unit may use comparators to find the largest value of a vector received from the etched mind unit(s). The sampler unit may determine the index of the largest value and output a predicted token. The flow contour unit may orchestrate the other components of the IC device based on a timing sequence of the model.

The invention discloses a chip mounter service logic control method and system based on an abstract component and a medium, and relates to the technical field of industrial automation control, and the system comprises a command cache queue module which is configured to receive and cache commands issued from an upper layer; the command parameter verification module is configured to verify the legality of the command parameters cached by the command cache queue module in real time; the user command monitoring module is configured to distribute the commands passing the verification to different units according to command types; and the equipment control flow monitoring module is configured to monitor a command execution state of a hardware layer, and if the command execution state is not received within a specified time, an overtime event is reported to the user command monitoring module and a system is coordinated to enter a safe state. According to the scheme, a unified business logic control center and an abstracted component control model are constructed, component cooperative control logic is completely stripped from specific hardware implementation, and centralization, closed-loop and uniqueness of command execution are achieved.

The invention discloses a dynamic multi-thread memory access management method, and relates to the technical field of computers, in particular to a dynamic multi-thread memory access management method and device.The method comprises the following steps that a plurality of memory access requests outside a processor and / or inside the processor are obtained, and a first request queue is formed; wherein the memory access request comprises a thread identifier, an access type and a target memory address; dynamically sequencing the memory access requests in the request queue according to a preset priority rule, and calculating the memory access request with the highest priority; wherein the priority rule comprises at least one of a thread priority rule, a request source priority rule and a memory address priority rule; obtaining and executing the memory access request with the highest priority; the memory resource allocation efficiency can be effectively improved, the system adaptability and flexibility are enhanced, the hardware implementation complexity is simplified, and the response delay is reduced.

The invention relates to the technical field of pulse neural network computing hardware, in particular to a neural network computing circuit of a pulse self-attention mechanism. According to the method, invalid or inefficient pulse events are dynamically screened through the hardware mask module, the operation number is remarkably reduced, and calculation path delay and logic resource occupation are reduced; meanwhile, in order to adapt to novel networks with binary architecture such as QKFormer, calculation and storage of a V matrix are eliminated, and storage resources and calculation resources are further reduced; in addition, the event coding module only generates active neuron events, and input sparsity is achieved. A configurable IF neuron model is adopted, exponential operation is avoided, hardware implementation is facilitated, and the method is suitable for binary network deployment. The modular architecture can support function extension, assembly line and parallel work; and the parallelism degree of the design can be determined according to the actual data pulse distribution rate. Event driving and mask pruning are combined, so that the overall computing resources of the circuit are greatly reduced, and the power consumption is reduced.

The invention relates to a configurable decompression circuit supporting COO and Bi tmap compression algorithms, and belongs to the field of integrated circuits. According to the hybrid compression method suitable for the circuit, after sparseness analysis is carried out on weight matrixes of all layers of a neural network, COO compression based on a coordinate type sparse matrix or Bitmap compression based on bitmap masks is selected according to the sparseness characteristics of different layers, so that the storage space is optimized; comprising a control module, a first selector, a second selector, a bitmap description memory, a coordinate index memory, a numerical memory, a converter, a COO decoder and a decompression data storage module, decoding of two compression formats of COO and Bi tmap can be supported, and the operation efficiency and flexibility of a neural network processor are improved. The method effectively reduces the weight storage demand of the neural network, enhances the adaptability of the compression algorithm, and is suitable for hardware implementation of an efficient neural network model.

The invention provides a cache consistency processing method and device, equipment and a storage medium, and the method comprises the steps: when a write operation or an atomic operation is carried out on a first copy in any first last-stage cache, forwarding the write operation or the atomic operation to a second last-stage cache, discarding the first copy in the first last-stage cache of the first copy, and storing the first copy in the second last-stage cache of the first copy; and performing write operation or atomic operation on the second copy in the second last-stage cache to obtain a processed second copy. In the technical scheme, write operations or atomic operations in other last-stage caches are all forwarded to the last-stage caches corresponding to the corresponding high-bandwidth memories, so that the last-stage caches are subjected to unilateral operations or atomic operations, tedious consistency steps in the prior art are avoided, the protocol and hardware implementation complexity is greatly simplified, and the implementation efficiency is improved. Therefore, the performance optimization is realized.

The application discloses a pixel counting method and device for a dashed line mask calculation and a storage medium, and specifically comprises: pixel counting schemes for the dashed line mask calculation in a non-MSAA scene and in an MSAA scene are respectively given. The application has simple calculation mode, reduces mask calculation complexity, is beneficial to hardware implementation, saves calculation time delay and reduces power consumption, and simultaneously solves problems and defects of an existing scheme in the MSAA scene.

The invention discloses a hardware acceleration method and system for a ZSTD data compression algorithm based on an FPGA. Unified hardware implementation and collaborative optimization are carried out on three key links of LZ77 character matching, Huffman coding and finite state entropy coding in the ZSTD data compression algorithm. According to the system, a multi-channel parallel LZ77 character matching hardware architecture is adopted, and character matching is executed on continuous positions in a plurality of parallel windows at the same time. A modular design and a deep pipeline structure are adopted, and a buffer and pipeline mechanism is introduced among modules such as an LZ77 matching module, a Huffman coding module and a finite state entropy coding module. The 375MB / s compression throughput can be achieved under the 100MHz clock frequency, the compression speed is remarkably increased while the compression ratio is guaranteed, and the method is suitable for scenes with high requirements for compression performance of data centers, edge computing and embedded systems and has high practicability and popularization value.

The invention discloses a borrowing type successive approximation analog-to-digital converter adopting a back propagation neural network for calibration. The borrowing type successive approximation analog-to-digital converter comprises a system composed of a positive and negative capacitance digital-to-analog converter adopting a three-stage split bridge type capacitor array, a bootstrap sampling switch, an automatic return-to-zero comparator, an SAR logic control unit, an original-to-binary module and a BPNN calibration engine. Bootstrap sampling switches are respectively arranged at the tail ends of the positive and negative capacitance digital-to-analog converters, a comparator is connected with the output ends of the two, and the output is connected with an SAR logic control unit; the original-to-binary module converts the code generated by the SAR logic control unit into a binary code; and a BPNN calibration engine receives the code and performs calibration calculation by using a trained back propagation neural network model. By implementing the converter disclosed by the invention, hardware implementation can be simplified while high performance is ensured, so that the ADC realizes efficient and accurate signal conversion under a 180-nanometer BCD process, and power consumption and cost are reduced.

The present disclosure relates to a computer- or hardware-implemented method (100) for identifying entities, comprising the steps of: a) providing (110) inputs from a plurality of sensors to a network of a plurality of nodes; b) generating (120) an activity level by each node of the network based on the inputs from the plurality of sensors; c) comparing (130) the activity level of each node to a threshold level; d) setting (140) the activity level for each node to a preset value or retaining the generated activity level based on the comparing step; e) calculating (150) a total activity level as the sum of all activity levels of the nodes of the network; f) repeating (160) steps a)-e) until a local minimum in the total activity level is reached; and g) once a local minimum in the total activity level is reached, utilizing (170) the distribution of activity levels at the local minimum to identify measurable entity characteristics. The present disclosure further relates to a computer program product and an entity identification device (300).