13 results about "Asynchronous circuit" patented technology

The embodiment of the invention relates to a scalable arbiter for non-persistent signals. Systems and devices for signal arbitration are described. The plurality of asynchronous circuits may receive a plurality of non-persistent signals representing the plurality of requests and scrub the plurality of non-persistent signals to generate a plurality of persistent signals. The at least one logic circuit may arbitrate a plurality of persistent signals, wherein each logic circuit in the at least one logic circuit may include a mutual exclusion circuit configured to arbitrate two signals. Each logic circuit is one of a first logic circuit, a second logic circuit, and a third logic circuit that are different from each other. The plurality of copies of the first logic circuit may be implemented at an initial arbitration level, and the plurality of copies of the second and third logic circuits may be implemented at an additional arbitration level.

A processing method according to an embodiment of the present disclosure includes: causing a computer to perform first processing for identifying one or a plurality of flip-flop circuits each forming a self-feedback loop from among a plurality of flip-flop circuits in a synchronous circuit, deleting a feedback path in the self-feedback loop, identifying two or more flip-flop circuits forming strongly coupled components from among the one or plurality of flip-flop circuits, and replacing the two or more flip-flop circuits forming the strongly coupled components with one dummy flip-flop circuit; and causing the computer to perform second processing for identifying first one or more flip-flop circuits coupled to input side of a combinational circuit and second one or more flip-flop circuits coupled to output side of the combinational circuit.

Systems and devices for signal arbitration are described. A plurality of asynchronous circuits can receive a plurality of non-persistent signals representing a plurality of requests and sanitize the plurality of non-persistent signals to generate a plurality of persistent signals. At least one logic circuit can arbitrate the plurality of persistent signals, where each one of the at least one logic circuit can include a mutual exclusive circuit configured to arbitrate two signals. Each logic circuit is one of a first logic circuit, a second logic circuit and a third logic circuit different from one another. A number of copies of the first logic circuit can be implemented in an initial level of arbitration and a number of copies of the second logic circuit and the third logic circuit can be implemented in additional levels of arbitration.

The application discloses an AHB bus cross-clock domain data synchronization method based on a self-defined handshake protocol and particularly relates to the AHB technical field, which comprises the following steps: designing a self-defined handshake protocol, setting an AHB bus conversion bridge, setting an asynchronous FIFO synchronization circuit, setting a handshake protocol conversion bridge, and completing the cross-clock domain synchronization of a request path and a response path. Through the request and response full-handshake mechanism, the application can realize data synchronization between any clock domains in any frequency combination of a source clock domain and a target clock domain, avoid the timing conflict caused by the superposition of multiple requests, fix the READY signal of the response channel as a high level, and completely solve the deadlock problem of the existing pulse synchronization scheme. In addition, the application optimizes the depth required by the asynchronous FIFO circuit and the information between different clock domains by utilizing the characteristic that the in-transit request of the handshake protocol is less than or equal to 1, optimizes the timing of the AHB bus conversion bridge through scene conversion logic, realizes the request of any burst transmission type, and improves the synchronization and transmission efficiency.

An asynchronous circuit portion for sampling an input signal is provided. The asynchronous circuit portion comprises a sampling circuit portion arranged to receive the input signal and to generate first and second sample signals; a first storage element arranged to generate a first storage signal on a first storage output on reception of the first sample signal; and a second storage element arranged to generate a second storage signal on a second storage output on reception of the second sample signal. A control circuit portion is arranged to detect if either of said first and second storage signals has been generated, to fix the first and second storage outputs and to generate a sample ready signal. The circuit portion generates an output signal corresponding to the input signal using the first storage output when the sample ready signal is generated.

This invention discloses a method and apparatus for cracking asynchronous encryption circuits. By analyzing the encryption netlist structure of the asynchronous encryption circuit, the control path and data path are extracted. The asynchronous controller in the control path is structurally analyzed and divided into a first group of real paths and a group of potential forged paths. Based on the first group of real paths and the group of potential forged paths, the data path is resynchronized to obtain a simplified circuit. A Boolean satisfiability SAT solver is used to classify the potential forged paths in the simplified circuit, resulting in a second group of real paths and a group of forged paths. Based on the classification results of the first group of real paths, the second group of real paths, and the group of forged paths, the key is recovered. This invention combines the characteristics of asynchronous circuits and encryption methods, transforming the encryption circuit into a classification problem of forged and real paths. By extracting the correlation and distribution characteristics between keys, the circuit is simplified, and the SAT solving speed is accelerated.

The application relates to the chip technical field, in particular to a low-power-consumption asynchronous handshake circuit and an asynchronous circuit, the asynchronous handshake circuit comprising a first flip-flop, a second flip-flop and a third flip-flop; a clock port of the first flip-flop is used for receiving a single pulse signal generated based on a first clock, a data port of the first flip-flop is connected with vdd, and an output port of the first flip-flop is connected with a data port of the second flip-flop; an output port of the second flip-flop is connected with a data port of the third flip-flop, and a clock port of the second flip-flop and an output port of the third flip-flop are both connected with a second clock; if the first flip-flop is an asynchronous low-level effective reset port, the asynchronous handshake circuit further comprises an inverter, an output port of the third flip-flop is connected with a data port of the inverter, and an output port of the inverter is connected with a reset port of the first flip-flop. The application reduces the power consumption of the asynchronous handshake circuit and improves the timing convergence speed of the asynchronous handshake circuit.

The application discloses a high-concurrency processor architecture based on an instruction-level event structure and a scheduling method thereof, is based on RISC-V instructions, and defines the stagnation, successful termination, sequential execution, conditional branching and merging operation of a program through a process algebra (PA-ISA) oriented to an instruction set architecture (ISA). On the basis of the PA-ISA, the dependence relationship between instructions in program execution is described through an instruction-level event structure (IES). The instruction-level event structure model is adopted to describe the dependence relationship between instructions in the program, the instruction concurrency is improved, and good expansibility is achieved. The high-concurrency processor architecture based on the IES is combined with an asynchronous circuit, an event triggering is taken as a basic execution advancing mode, the frequency or energy efficiency is improved, the bypass control mechanism in the out-of-order execution is simplified, and the system reliability is improved. The instruction-level event structure is combined with a double-path instruction fetching mechanism, the instruction waste and performance loss are reduced, and the fault tolerance capability under a large-scale instruction fetching strategy is optimized.

The invention discloses an implementation asynchronous circuit and implementation method of an SM3 algorithm resisting side channel attacks, in the implementation circuit, a handshake protocol is adopted to drive data flow, reliable data transmission and parallel computing without clock synchronization are realized through an asynchronous component, an asynchronous message extension module decomposes a single control flow into multiple paths of concurrent threads by utilizing Splitter, and the multiple paths of concurrent threads are distributed in parallel. And independently updating the physical register block. A plurality of asynchronous dynamic topology prefix adders are arranged in the iterative compression calculation module, operation can be started immediately according to the data arrival sequence, and the problem of power consumption leakage is solved in computational logic through the adders and built-in mask operation. WaitMerge is used as a dynamic synchronization barrier, the completion time of a corresponding adder is accurately captured to trigger subsequent calculation, a periodic clock characteristic peak in electromagnetic radiation is eliminated by using a mutex Merge mutual exclusion mechanism and a clock-free design, the side channel attack resistance protection capability is improved, and the physical defense capability of a chip is enhanced.

The invention provides an asynchronous wake-up circuit system which is divided into an analog circuit part and a digital circuit part. The analog circuit part comprises an oscillator; the digital circuit part comprises a wake-up control module, a clock control module and a system state machine; the clock control module is realized by adopting an asynchronous circuit and is used for outputting a power failure control signal; the oscillator outputs the clock signal in response to the fact that the power-down control signal is at a low level; the oscillator outputs no signal in response to the condition that the power-down control signal is at a high level; the wake-up control module is used for receiving the wake-up signal and outputting a wake-up event; the system state machine is used for controlling mode switching of the system and comprises a sleep mode and a normal working mode. Therefore, the dual problems that the dynamic power consumption in the dormant state cannot be eliminated by the traditional clock gating and the wake-up delay of the power gating technology is long are effectively solved.

The application belongs to the field of asynchronous circuits, and discloses an asynchronous MouseTrap handshake unit with a matching delay and a system, the handshake unit comprising: a delay latch, a self-clock generator and an output inverter; an enabling output end of the self-clock generator is connected with an enabling input end of the delay latch, and output ends of the delay latch are respectively connected with an input end of the self-clock generator and an input end of the output inverter; the delay latch comprises: a Schmitt trigger unit, and a delay module is arranged on an input side of the Schmitt trigger unit, and the delay module is used for making the Schmitt trigger unit produce a delay. The circuit structure of the application is simple, the Schmitt trigger unit can increase the driving capacity of the delay latch, and dynamic power consumption is reduced.

The utility model relates to lithium cell technical field, concretely is a kind of constant-current constant-voltage heating pad control circuit based on PWM. Including asynchronous buck circuit, gate drive circuit, voltage control drive circuit, PWM control circuit, MCU chip, the LCSG_DriveA0 port of asynchronous buck circuit, LCSG_DriveB0 port are sequentially connected the LCSG_DriveA0 port of gate drive circuit, LCSG_DriveB0 port, the VSamp port of asynchronous buck circuit is connected the VSamp port of PWM control circuit, the CON_PWM port of gate drive circuit is connected the CON_PWM port of PWM control circuit, the REF_PWM port of voltage control drive circuit is connected the VRef port of PWM control circuit, the one PE pin of MCU chip is connected the HEAT_OFF port of gate drive circuit, another PE pin of MCU chip is connected the CL_PWM port of voltage control drive circuit. Compared with prior art, realize the dynamic regulation of heating pad current, ensure that constant-current constant-voltage output is to heating pad both ends, improve energy conversion efficiency.

Systems and devices for signal arbitration are described. A plurality of asynchronous circuits can receive a plurality of non-persistent signals representing a plurality of requests and sanitize the plurality of non-persistent signals to generate a plurality of persistent signals. At least one logic circuit can arbitrate the plurality of persistent signals, where each one of the at least one logic circuit can include a mutual exclusive circuit configured to arbitrate two signals. Each logic circuit is one of a first logic circuit, a second logic circuit and a third logic circuit different from one another. A number of copies of the first logic circuit can be implemented in an initial level of arbitration and a number of copies of the second logic circuit and the third logic circuit can be implemented in additional levels of arbitration.