47 results about "Asynchronous circuit" patented technology

The invention discloses an automatic integrated system from an asynchronous pipeline to an asynchronous circuit, which adopts a modular architecture, takes a high-level structure description file in a JSON / XML format as input, and gradually maps to generate a gate-level netlist and a standard delay format file so as to be in butt joint with a commercial back-end design process. According to the method, asynchronous design based on an asynchronous structure can be automatically mapped into an asynchronous circuit, the automatic mapping process can seamlessly process multi-level design representation, the mapping result is stable and cooperatively operated, asynchronous circuit time sequence detection and delay matching are automatically completed, the design efficiency is greatly improved, and the design cost is reduced. An automatic delay matching mechanism enables the circuit to have a good data ready detection and handshake mechanism, and the characteristics of low power consumption, high throughput and no global clock drift sensitivity are realized; in addition, automation of asynchronous design key links such as structure abstraction, time delay modeling and testability insertion is achieved while design readability, hierarchical consistency and time sequence controllability are guaranteed.

Systems and devices for signal arbitration are described. A first asynchronous circuit can receive and sanitize a first non-persistent signal representing a first request to generate a first persistent signal. A second asynchronous circuit can receive and sanitize a second non-persistent signal representing a second request to generate a second persistent signal. A mutual exclusive circuit can arbitrate between the first persistent signal and the second persistent signal and output a grant signal to issue a grant. A control circuit can control an operation mode of the first and second asynchronous circuits based on a control signal, a first grant signal indicating a grant status of the first request, a second grant signal indicating a grant status of the second request, the first persistent signal and the second persistent signal.

The invention discloses an asynchronous multi-granularity memory access control method in a microprocessor, an asynchronous circuit and a memory access module, the memory access control method adopts asynchronous clock-free control, introduces a multi-granularity memory access control mechanism, and divides the memory access granularity into two classes of multi-word memory access and non-multi-word memory access for processing. According to the method, the access path and the cache strategy can be flexibly adjusted according to different access granularities, redundant operation during access is reduced, and the access efficiency is greatly improved. The asynchronous circuit is a delay-limited asynchronous circuit and comprises an asynchronous controller and an asynchronous micro-pipeline structure based on a'sending-relay-receiving 'structure. The memory access module based on the asynchronous circuit comprises a memory access state management module, a data access updating module, an instruction / data cache and peripheral interaction interface, and a data interaction interface between the memory access module and the write-back module. According to the invention, lower dynamic power consumption and higher energy efficiency ratio are realized, and high efficiency and low delay are realized under large data volume operation.

The invention discloses an asynchronous parallel processing method and system for address correlation in a superscalar processor, after an instruction data packet enters a transmitting unit, instructions are sent to a corresponding transmitting queue according to the type of each instruction, the transmitting queue requests to transmit the instructions in a polling mode, and when the selected instruction meets a transmitting condition, the selected instruction is transmitted; in one round of instructions, the Load instructions are grouped by taking the Store instructions as boundaries, and the Load instructions in the groups are executed out of order; after the memory access instruction enters the memory access stage, when the Store instruction is executed, the Store instruction is temporarily stored in the buffer table, when the Load instruction is executed, whether address correlation exists between the current Load instruction and the Store instruction in the buffer table or not is detected, if the address correlation does not exist, the internal access number is accessed, and if the address correlation exists, the number is fetched from the buffer table. On the basis of the design of the asynchronous circuit, a memory access instruction part out-of-order execution and memory access instruction address correlation processing mechanism is introduced, the memory access instruction throughput efficiency of the superscalar processor is improved, and the instruction execution speed and processing efficiency are improved.

The invention discloses a parallel processing module and method for a compression instruction set and a non-compression instruction set and an asynchronous circuit, and the module comprises the steps: firstly, storing a mixed instruction into a buffer area Buffer 1 module, then separating a compression instruction and a non-compression instruction through a mixedInstrDivsion module, directly storing the separated non-compression instruction into a buffer area Buffer 2 module, and storing the compressed instruction and the non-compression instruction into the buffer area Buffer 2 module; the separated compression instructions are expanded through a mixInstrProcess module, four compression instructions are expanded in parallel in one round, and finally the expanded non-compression instructions are stored in a buffer area Buffer 2 module to be used by a decoding module. By adopting the parallelization processing method, more instructions are divided and expanded in the same time period, the instruction processing speed of the compression processing stage in the superscalar processor is improved, parallel execution of multiple instructions is achieved in the whole stage, and the performance of the processor is improved. The parallel processing module is realized by adopting a BBD asynchronous circuit, so that the clock problem is avoided, and the power consumption can be greatly reduced.

An apparatus may comprise a controller programmed to receive information about a synchronized digital circuit comprising a plurality of Boolean gates, determine a critical path through each synchronized, combination subcircuit block of the digital circuit, identify a first set of Boolean gates among the plurality of Boolean gates positioned in the critical path, determine a hybrid equivalent gate for each Boolean gate among the first set of Boolean gates, wherein the hybrid equivalent gate has a synchronous input, a dual-rail asynchronous input, and a dual-rail output, and generate a modified digital circuit by replacing each Boolean gate among the first set of Boolean gates with a corresponding hybrid equivalent gate.

The embodiment of the invention relates to a scalable arbiter for non-persistent signals. Systems and devices for signal arbitration are described. The plurality of asynchronous circuits may receive a plurality of non-persistent signals representing the plurality of requests and scrub the plurality of non-persistent signals to generate a plurality of persistent signals. The at least one logic circuit may arbitrate a plurality of persistent signals, wherein each logic circuit in the at least one logic circuit may include a mutual exclusion circuit configured to arbitrate two signals. Each logic circuit is one of a first logic circuit, a second logic circuit, and a third logic circuit that are different from each other. The plurality of copies of the first logic circuit may be implemented at an initial arbitration level, and the plurality of copies of the second and third logic circuits may be implemented at an additional arbitration level.

The invention relates to an asynchronous input signal function safety design method and device and a chip, and the method comprises the steps: inputting an asynchronous input signal into a first synchronization module and a second synchronization module at the same time, the first synchronization module being the same as the second synchronization module; and simultaneously inputting the output signal of the first synchronization module and the output signal of the second synchronization module into a detection module, wherein the detection module detects the difference of the output signal of the first synchronization module and the output signal of the second synchronization module in period. According to the asynchronous input signal function safety design method provided by the invention, a simple safety mechanism of an asynchronous circuit is realized through redundancy design of the two synchronous modules.

Systems and devices for signal arbitration are described. A first asynchronous circuit can receive and sanitize a first non-persistent signal representing a first request to generate a first persistent signal. A second asynchronous circuit can receive and sanitize a second non-persistent signal representing a second request to generate a second persistent signal. A mutual exclusive circuit can arbitrate between the first persistent signal and the second persistent signal and output a grant signal to issue a grant. A control circuit can control an operation mode of the first and second asynchronous circuits based on a control signal, a first grant signal indicating a grant status of the first request, a second grant signal indicating a grant status of the second request, the first persistent signal and the second persistent signal.

The invention discloses a double-phase lightweight asynchronous circuit based on time sequence borrowing and a control method thereof. The circuit comprises a control path and a data path. The control access comprises a double-phase lightweight asynchronous controller and a lightweight asynchronous controller; the data path comprises a storage unit and a combinational logic unit. The method comprises the following steps: carrying out asynchronization processing based on a register circuit to obtain an asynchronized register circuit; carrying out distinguishing processing on the asynchronized register circuit based on time sequence constraint to obtain a distinguished register circuit; a double-phase lightweight asynchronous controller and a lightweight asynchronous controller are introduced, margin sensing asynchronous control processing is carried out on the distinguished register circuits, and time sequence pulse control signals are generated. According to the embodiment of the invention, the control signals with different pulse widths can be matched with the requirements of the latch, so that the execution efficiency of the instruction is improved, and the optimization of the power consumption and the area of the asynchronous circuit is realized. The method can be widely applied to the technical field of integrated circuit design.

The invention discloses a clock management architecture for realizing low power consumption of a chip based on an asynchronous circuit, and belongs to the technical field of chip clock management. Comprising a wake-up detection circuit and an event processing circuit which are two branches and are respectively used for detecting a wake-up related signal and a chip mode, an output signal of the wake-up detection circuit is connected with a reset port of a gate control enabling generation module, and an output signal of the event processing circuit is connected with an input end of the gate control enabling generation module; the gating enabling generation module generates a gating enabling instruction, the gating enabling instruction is sent to the gating module through the second signal synchronization module, a gating clock signal is obtained, and the clock is opened or closed. According to the invention, clocks of different modules can be thoroughly closed under different conditions according to actual needs, and the asynchronous circuit can detect the wake-up signal to open the clock under the condition that the clock is closed.

A processing method according to an embodiment of the present disclosure includes: causing a computer to perform first processing for identifying one or a plurality of flip-flop circuits each forming a self-feedback loop from among a plurality of flip-flop circuits in a synchronous circuit, deleting a feedback path in the self-feedback loop, identifying two or more flip-flop circuits forming strongly coupled components from among the one or plurality of flip-flop circuits, and replacing the two or more flip-flop circuits forming the strongly coupled components with one dummy flip-flop circuit; and causing the computer to perform second processing for identifying first one or more flip-flop circuits coupled to input side of a combinational circuit and second one or more flip-flop circuits coupled to output side of the combinational circuit.

This control circuit for an asynchronous circuit comprises a clock generation circuit (220) that outputs a clock (clk) of an expandable / contractable pulse width. The clock generation circuit (220) comprises a delay adjustment circuit (101) that delays an inputted clock (clk) by a delay amount and outputs the result, and a logic circuit (205) that outputs, as a clock (clk), a signal expressing the result of a logical operation between the output of the delay adjustment circuit (101), a request signal (req), and an acknowledgement signal (ack). The clock (clk) is supplied to a register.

The invention relates to the field of chip design, in particular to a low-power-consumption MCU (Microprogrammed Control Unit) power management unit realized by using an asynchronous circuit. Isolation unit control, voltage-stabilized power supply control, HSI clock control and VCORE domain reset control are asynchronously realized through the trigger and a series of delay chains. Compared with a PMU realized based on a state machine, the PMU is designed in a fully asynchronous manner, a clock is not needed during working, the dynamic power consumption of the PMU is reduced, and the power consumption required for maintaining clock operation in a low-power-consumption mode is saved. Compared with a PMU which is realized by a state machine and needs to start to work after a clock is stable, the method provided by the invention starts to work after a wake-up mark is effective, so that the wake-up response time of the chip is effectively shortened.

Systems and devices for signal arbitration are described. A plurality of asynchronous circuits can receive a plurality of non-persistent signals representing a plurality of requests and sanitize the plurality of non-persistent signals to generate a plurality of persistent signals. At least one logic circuit can arbitrate the plurality of persistent signals, where each one of the at least one logic circuit can include a mutual exclusive circuit configured to arbitrate two signals. Each logic circuit is one of a first logic circuit, a second logic circuit and a third logic circuit different from one another. A number of copies of the first logic circuit can be implemented in an initial level of arbitration and a number of copies of the second logic circuit and the third logic circuit can be implemented in additional levels of arbitration.

The invention discloses a high-concurrency processor architecture based on an instruction level event structure and a scheduling method of the high-concurrency processor architecture, which are characterized in that on the basis of an RISC-V instruction, stagnation, successful termination, sequential execution, conditional branching and merging operations of a program are defined through a process algebra PA-ISA oriented to an instruction set architecture; on the basis of PA-ISA, a dependency relationship among instructions in program execution is described through an instruction level event structure IES. According to the method, an instruction-level event structure model is adopted to describe a dependency relationship among instructions in a program, so that the concurrency of the instructions is improved, and good expansibility is achieved; a high-concurrency processor architecture based on IES is combined with an asynchronous circuit, event triggering is used as a basic execution propulsion mode, and the frequency or energy efficiency is improved; by simplifying a bypass control mechanism in out-of-order execution, the system reliability is improved; through combination of an instruction-level event structure and a double-path fetch mechanism, instruction waste and performance loss are reduced, and the fault-tolerant capability under a large-scale fetch strategy is optimized.

This invention discloses a clockless asynchronous circuit, a method, device, and medium for synchronous data output. By adding several signal values ​​to the existing 0 and 1 signal values ​​and outputting these signal values ​​through a clockless asynchronous circuit, the effect of transmitting multiple signal values ​​on a single data line is achieved. Through the clockless asynchronous circuit, the input module converts the initial signal value and outputs a first operation signal for logical operations by the internal module. This enables the internal module to output a first operation result based on the first operation signal, and the output module to output a second operation result based on the first operation result, which is used by the asynchronous circuit to determine whether to output data. This achieves the effect of data clock synchronization while avoiding the power loss of the asynchronous circuit caused by clock signals or clock recovery circuits.

The invention discloses a circuit design method and a circuit design platform. Determining a time sequence margin threshold range corresponding to one or more time sequence paths in the first asynchronous circuit; searching an error time sequence path in the one or more time sequence paths through the time sequence analysis instruction; wherein the error time sequence path is a path in which the time sequence margin of the time sequence path exceeds a corresponding time sequence margin threshold range, the time sequence margin is the difference between a first time length and a second time length, the first time length is the time length from a transmitting clock of a first latch to a capturing clock of a second latch in the corresponding time sequence path, and the second time length is the time length from the transmitting clock of the second latch to the capturing clock of the second latch in the corresponding time sequence path. The second duration is a data calculation duration between the first latch and the second latch in the corresponding time sequence path; and adjusting a capture clock of a second latch of the error timing path to a clock position matched with the corresponding timing margin threshold range through the timing processing instruction. By adopting the embodiment of the invention, the problem of time sequence chaos in an asynchronous circuit realized based on a latch can be solved.

A control circuit of an asynchronous circuit disclosed herein includes a clock generation circuit (220) that outputs a clock (clk) having a flexible pulse width. The clock generation circuit (220) includes: a delay adjustment circuit (101) that delays an input clock (clk) by a delay amount and outputs the delayed clock; and a logic circuit (205) that outputs, as a clock (clk), a signal representing the result of a logical operation between the output of the delay adjustment circuit (101), a request signal (req), and an acknowledgement signal (ack). The clock (clk) is supplied to a register.

The application discloses an AHB bus cross-clock domain data synchronization method based on a self-defined handshake protocol and particularly relates to the AHB technical field, which comprises the following steps: designing a self-defined handshake protocol, setting an AHB bus conversion bridge, setting an asynchronous FIFO synchronization circuit, setting a handshake protocol conversion bridge, and completing the cross-clock domain synchronization of a request path and a response path. Through the request and response full-handshake mechanism, the application can realize data synchronization between any clock domains in any frequency combination of a source clock domain and a target clock domain, avoid the timing conflict caused by the superposition of multiple requests, fix the READY signal of the response channel as a high level, and completely solve the deadlock problem of the existing pulse synchronization scheme. In addition, the application optimizes the depth required by the asynchronous FIFO circuit and the information between different clock domains by utilizing the characteristic that the in-transit request of the handshake protocol is less than or equal to 1, optimizes the timing of the AHB bus conversion bridge through scene conversion logic, realizes the request of any burst transmission type, and improves the synchronization and transmission efficiency.

An asynchronous circuit portion for sampling an input signal is provided. The asynchronous circuit portion comprises a sampling circuit portion arranged to receive the input signal and to generate first and second sample signals; a first storage element arranged to generate a first storage signal on a first storage output on reception of the first sample signal; and a second storage element arranged to generate a second storage signal on a second storage output on reception of the second sample signal. A control circuit portion is arranged to detect if either of said first and second storage signals has been generated, to fix the first and second storage outputs and to generate a sample ready signal. The circuit portion generates an output signal corresponding to the input signal using the first storage output when the sample ready signal is generated.

The application relates to the field of chip design, in particular to a low-power MCU power management unit realized by using an asynchronous circuit. The application realizes isolated unit control, stabilized power supply control, HSI clock control and VCORE domain reset control asynchronously through a flip-flop and a series of delay chains. Compared with a PMU realized based on a state machine, the application is a full-asynchronous design, does not need a clock during work, reduces the dynamic power consumption of the PMU, and saves the power consumption required for maintaining clock operation in a low-power mode. Compared with a PMU realized based on a state machine which needs to wait for the clock to be stable before starting work, the application starts work as soon as the wake-up flag is valid, effectively shortening the wake-up response time of the chip.

The invention relates to an arbiter for non-persistent signals. Systems and devices for signal arbitration are described herein. The first asynchronous circuit may receive and scrub a first non-persistent signal representing the first request to generate a first persistent signal. The second asynchronous circuit may receive and scrub a second non-persistent signal representing the second request to generate a second persistent signal. A mutual exclusion circuit may arbitrate between the first persistent signal and the second persistent signal and output an authorization signal to issue an authorization. A control circuit may control operating modes of the first asynchronous circuit and the second asynchronous circuit based on a control signal, a first authorization signal indicative of an authorization state of the first request, a second authorization signal indicative of an authorization state of the second request, the first duration signal, and the second duration signal.

The invention discloses an AHB (Advanced High-performance Bus) cross-clock domain data synchronization method based on a user-defined handshake protocol, and particularly relates to the technical field of AHBs, which comprises the steps of designing the user-defined handshake protocol, setting an AHB conversion bridge, setting an asynchronous FIFO (First In First Out) synchronous circuit, setting a handshake protocol conversion bridge and finishing cross-clock domain synchronization of a request path and a response path. Through a request and response full handshake mechanism, any frequency combination of a source clock domain and a target clock domain, data synchronization is carried out between any clock domains, time sequence conflicts caused by superposition of multiple requests are avoided, a response channel READY signal is fixed to be high level, no response blocking scene exists, the deadlock problem of an existing pulse synchronization scheme is thoroughly solved, and the time sequence conflicts caused by superposition of multiple requests are avoided. The characteristic that the in-transit request of a handshake protocol is smaller than or equal to 1 is utilized, the depth needed by the asynchronous FIFO circuit and information between different clock domains are optimized, the AHB bus conversion bridge optimizes the time sequence through scene-based conversion logic, requests of any burst transmission type are achieved, and the synchronization and transmission efficiency is improved.

An apparatus, system, and method for voltage regulator (VR) control are provided. An apparatus can include first, second, and third comparators configured to determine whether a load voltage (VLOAD) drops below a lower non-linear control (NLC) threshold, drops below a lower linear control (LC) threshold, and exceeds an upper LC threshold, respectively. The apparatus can include power gates (PGs) configured to adjust an output voltage (VOUT) based on a provided power gate (PG) code. The apparatus can include voltage regulator (VR) controller circuitry comprising synchronous LC circuitry and asynchronous NLC circuitry, the LC circuitry configured to increment or decrement the PG code responsive to the VLOAD dropping below the LC threshold and exceeding the upper LC threshold, respectively, and the NLC circuitry configured to increase the PG code based on a number of consecutive NLC droop events and responsive to the VLOAD dropping below the lower NLC threshold.

The invention belongs to the field of asynchronous circuits, and discloses an asynchronous Mouse Trap handshake unit and system with matching delay, and the handshake unit comprises a delay latch, a self-clock generator and an output phase inverter; the enabling output end of the self-clock generator is connected with the enabling input end of the delay latch, and the output end of the delay latch is connected with the input end of the self-clock generator and the input end of the output phase inverter. The delay latch comprises a Schmidt trigger unit, a delay module is deployed on the input side of the Schmidt trigger unit, and the delay module is used for enabling the Schmidt trigger unit to generate delay. The circuit is simple in structure, the Schmidt trigger unit can increase the driving capacity of the delay latch, and dynamic power consumption is reduced.

This invention discloses a method and apparatus for cracking asynchronous encryption circuits. By analyzing the encryption netlist structure of the asynchronous encryption circuit, the control path and data path are extracted. The asynchronous controller in the control path is structurally analyzed and divided into a first group of real paths and a group of potential forged paths. Based on the first group of real paths and the group of potential forged paths, the data path is resynchronized to obtain a simplified circuit. A Boolean satisfiability SAT solver is used to classify the potential forged paths in the simplified circuit, resulting in a second group of real paths and a group of forged paths. Based on the classification results of the first group of real paths, the second group of real paths, and the group of forged paths, the key is recovered. This invention combines the characteristics of asynchronous circuits and encryption methods, transforming the encryption circuit into a classification problem of forged and real paths. By extracting the correlation and distribution characteristics between keys, the circuit is simplified, and the SAT solving speed is accelerated.

The application discloses an automatic synthesis system of an asynchronous pipeline to an asynchronous circuit, adopts a modular architecture, takes a high-level structure description file in a JSON / XML format as input, gradually maps to generate a gate-level netlist and a standard delay format file, and is connected to a commercial back-end design process.The application can automatically map asynchronous design based on an asynchronous structure to an asynchronous circuit, the automatic mapping process can seamlessly process multi-level design representation, the mapping result is stable and cooperatively operated, and timing detection and delay matching of the asynchronous circuit are automatically completed, so that the design efficiency is greatly improved, the automatic delay matching mechanism makes the circuit have good data ready detection and handshaking mechanism, low power consumption, high throughput and no global clock drift sensitivity are realized; in addition, while guaranteeing design readability, level consistency and timing controllability, structure abstraction, delay modeling, testability insertion and other key links of asynchronous design are realized.

The application relates to the chip technical field, in particular to a low-power-consumption asynchronous handshake circuit and an asynchronous circuit, the asynchronous handshake circuit comprising a first flip-flop, a second flip-flop and a third flip-flop; a clock port of the first flip-flop is used for receiving a single pulse signal generated based on a first clock, a data port of the first flip-flop is connected with vdd, and an output port of the first flip-flop is connected with a data port of the second flip-flop; an output port of the second flip-flop is connected with a data port of the third flip-flop, and a clock port of the second flip-flop and an output port of the third flip-flop are both connected with a second clock; if the first flip-flop is an asynchronous low-level effective reset port, the asynchronous handshake circuit further comprises an inverter, an output port of the third flip-flop is connected with a data port of the inverter, and an output port of the inverter is connected with a reset port of the first flip-flop. The application reduces the power consumption of the asynchronous handshake circuit and improves the timing convergence speed of the asynchronous handshake circuit.

The invention relates to the technical field of chips, in particular to a low-power-consumption asynchronous handshake circuit and an asynchronous circuit, and the asynchronous handshake circuit comprises a first trigger, a second trigger and a third trigger; a clock port of the first trigger is used for receiving a single pulse signal generated based on a first clock, a data port of the first trigger is connected with the vdd, and an output port of the first trigger is connected with a data port of the second trigger; an output port of the second trigger is connected with a data port of the third trigger, and a clock port of the second trigger and an output port of the third trigger are both connected with a second clock; if the first trigger is an asynchronous low-level effective reset port, the asynchronous handshake circuit further comprises a phase inverter, an output port of the third trigger is connected with a data port of the phase inverter, and an output port of the phase inverter is connected with a reset port of the first trigger. According to the invention, the power consumption of the asynchronous handshake circuit is reduced, and the time sequence convergence speed of the asynchronous handshake circuit is improved.