26 results about "Asynchronous circuit" patented technology

The invention discloses an automatic integrated system from an asynchronous pipeline to an asynchronous circuit, which adopts a modular architecture, takes a high-level structure description file in a JSON / XML format as input, and gradually maps to generate a gate-level netlist and a standard delay format file so as to be in butt joint with a commercial back-end design process. According to the method, asynchronous design based on an asynchronous structure can be automatically mapped into an asynchronous circuit, the automatic mapping process can seamlessly process multi-level design representation, the mapping result is stable and cooperatively operated, asynchronous circuit time sequence detection and delay matching are automatically completed, the design efficiency is greatly improved, and the design cost is reduced. An automatic delay matching mechanism enables the circuit to have a good data ready detection and handshake mechanism, and the characteristics of low power consumption, high throughput and no global clock drift sensitivity are realized; in addition, automation of asynchronous design key links such as structure abstraction, time delay modeling and testability insertion is achieved while design readability, hierarchical consistency and time sequence controllability are guaranteed.

The invention discloses an asynchronous multi-granularity memory access control method in a microprocessor, an asynchronous circuit and a memory access module, the memory access control method adopts asynchronous clock-free control, introduces a multi-granularity memory access control mechanism, and divides the memory access granularity into two classes of multi-word memory access and non-multi-word memory access for processing. According to the method, the access path and the cache strategy can be flexibly adjusted according to different access granularities, redundant operation during access is reduced, and the access efficiency is greatly improved. The asynchronous circuit is a delay-limited asynchronous circuit and comprises an asynchronous controller and an asynchronous micro-pipeline structure based on a'sending-relay-receiving 'structure. The memory access module based on the asynchronous circuit comprises a memory access state management module, a data access updating module, an instruction / data cache and peripheral interaction interface, and a data interaction interface between the memory access module and the write-back module. According to the invention, lower dynamic power consumption and higher energy efficiency ratio are realized, and high efficiency and low delay are realized under large data volume operation.

An apparatus may comprise a controller programmed to receive information about a synchronized digital circuit comprising a plurality of Boolean gates, determine a critical path through each synchronized, combination subcircuit block of the digital circuit, identify a first set of Boolean gates among the plurality of Boolean gates positioned in the critical path, determine a hybrid equivalent gate for each Boolean gate among the first set of Boolean gates, wherein the hybrid equivalent gate has a synchronous input, a dual-rail asynchronous input, and a dual-rail output, and generate a modified digital circuit by replacing each Boolean gate among the first set of Boolean gates with a corresponding hybrid equivalent gate.

The embodiment of the invention relates to a scalable arbiter for non-persistent signals. Systems and devices for signal arbitration are described. The plurality of asynchronous circuits may receive a plurality of non-persistent signals representing the plurality of requests and scrub the plurality of non-persistent signals to generate a plurality of persistent signals. The at least one logic circuit may arbitrate a plurality of persistent signals, wherein each logic circuit in the at least one logic circuit may include a mutual exclusion circuit configured to arbitrate two signals. Each logic circuit is one of a first logic circuit, a second logic circuit, and a third logic circuit that are different from each other. The plurality of copies of the first logic circuit may be implemented at an initial arbitration level, and the plurality of copies of the second and third logic circuits may be implemented at an additional arbitration level.

Systems and devices for signal arbitration are described. A first asynchronous circuit can receive and sanitize a first non-persistent signal representing a first request to generate a first persistent signal. A second asynchronous circuit can receive and sanitize a second non-persistent signal representing a second request to generate a second persistent signal. A mutual exclusive circuit can arbitrate between the first persistent signal and the second persistent signal and output a grant signal to issue a grant. A control circuit can control an operation mode of the first and second asynchronous circuits based on a control signal, a first grant signal indicating a grant status of the first request, a second grant signal indicating a grant status of the second request, the first persistent signal and the second persistent signal.

The invention discloses a clock management architecture for realizing low power consumption of a chip based on an asynchronous circuit, and belongs to the technical field of chip clock management. Comprising a wake-up detection circuit and an event processing circuit which are two branches and are respectively used for detecting a wake-up related signal and a chip mode, an output signal of the wake-up detection circuit is connected with a reset port of a gate control enabling generation module, and an output signal of the event processing circuit is connected with an input end of the gate control enabling generation module; the gating enabling generation module generates a gating enabling instruction, the gating enabling instruction is sent to the gating module through the second signal synchronization module, a gating clock signal is obtained, and the clock is opened or closed. According to the invention, clocks of different modules can be thoroughly closed under different conditions according to actual needs, and the asynchronous circuit can detect the wake-up signal to open the clock under the condition that the clock is closed.

A processing method according to an embodiment of the present disclosure includes: causing a computer to perform first processing for identifying one or a plurality of flip-flop circuits each forming a self-feedback loop from among a plurality of flip-flop circuits in a synchronous circuit, deleting a feedback path in the self-feedback loop, identifying two or more flip-flop circuits forming strongly coupled components from among the one or plurality of flip-flop circuits, and replacing the two or more flip-flop circuits forming the strongly coupled components with one dummy flip-flop circuit; and causing the computer to perform second processing for identifying first one or more flip-flop circuits coupled to input side of a combinational circuit and second one or more flip-flop circuits coupled to output side of the combinational circuit.

Systems and devices for signal arbitration are described. A plurality of asynchronous circuits can receive a plurality of non-persistent signals representing a plurality of requests and sanitize the plurality of non-persistent signals to generate a plurality of persistent signals. At least one logic circuit can arbitrate the plurality of persistent signals, where each one of the at least one logic circuit can include a mutual exclusive circuit configured to arbitrate two signals. Each logic circuit is one of a first logic circuit, a second logic circuit and a third logic circuit different from one another. A number of copies of the first logic circuit can be implemented in an initial level of arbitration and a number of copies of the second logic circuit and the third logic circuit can be implemented in additional levels of arbitration.

The invention discloses a high-concurrency processor architecture based on an instruction level event structure and a scheduling method of the high-concurrency processor architecture, which are characterized in that on the basis of an RISC-V instruction, stagnation, successful termination, sequential execution, conditional branching and merging operations of a program are defined through a process algebra PA-ISA oriented to an instruction set architecture; on the basis of PA-ISA, a dependency relationship among instructions in program execution is described through an instruction level event structure IES. According to the method, an instruction-level event structure model is adopted to describe a dependency relationship among instructions in a program, so that the concurrency of the instructions is improved, and good expansibility is achieved; a high-concurrency processor architecture based on IES is combined with an asynchronous circuit, event triggering is used as a basic execution propulsion mode, and the frequency or energy efficiency is improved; by simplifying a bypass control mechanism in out-of-order execution, the system reliability is improved; through combination of an instruction-level event structure and a double-path fetch mechanism, instruction waste and performance loss are reduced, and the fault-tolerant capability under a large-scale fetch strategy is optimized.

The application discloses an AHB bus cross-clock domain data synchronization method based on a self-defined handshake protocol and particularly relates to the AHB technical field, which comprises the following steps: designing a self-defined handshake protocol, setting an AHB bus conversion bridge, setting an asynchronous FIFO synchronization circuit, setting a handshake protocol conversion bridge, and completing the cross-clock domain synchronization of a request path and a response path. Through the request and response full-handshake mechanism, the application can realize data synchronization between any clock domains in any frequency combination of a source clock domain and a target clock domain, avoid the timing conflict caused by the superposition of multiple requests, fix the READY signal of the response channel as a high level, and completely solve the deadlock problem of the existing pulse synchronization scheme. In addition, the application optimizes the depth required by the asynchronous FIFO circuit and the information between different clock domains by utilizing the characteristic that the in-transit request of the handshake protocol is less than or equal to 1, optimizes the timing of the AHB bus conversion bridge through scene conversion logic, realizes the request of any burst transmission type, and improves the synchronization and transmission efficiency.

An asynchronous circuit portion for sampling an input signal is provided. The asynchronous circuit portion comprises a sampling circuit portion arranged to receive the input signal and to generate first and second sample signals; a first storage element arranged to generate a first storage signal on a first storage output on reception of the first sample signal; and a second storage element arranged to generate a second storage signal on a second storage output on reception of the second sample signal. A control circuit portion is arranged to detect if either of said first and second storage signals has been generated, to fix the first and second storage outputs and to generate a sample ready signal. The circuit portion generates an output signal corresponding to the input signal using the first storage output when the sample ready signal is generated.

The application relates to the field of chip design, in particular to a low-power MCU power management unit realized by using an asynchronous circuit. The application realizes isolated unit control, stabilized power supply control, HSI clock control and VCORE domain reset control asynchronously through a flip-flop and a series of delay chains. Compared with a PMU realized based on a state machine, the application is a full-asynchronous design, does not need a clock during work, reduces the dynamic power consumption of the PMU, and saves the power consumption required for maintaining clock operation in a low-power mode. Compared with a PMU realized based on a state machine which needs to wait for the clock to be stable before starting work, the application starts work as soon as the wake-up flag is valid, effectively shortening the wake-up response time of the chip.

The invention discloses an AHB (Advanced High-performance Bus) cross-clock domain data synchronization method based on a user-defined handshake protocol, and particularly relates to the technical field of AHBs, which comprises the steps of designing the user-defined handshake protocol, setting an AHB conversion bridge, setting an asynchronous FIFO (First In First Out) synchronous circuit, setting a handshake protocol conversion bridge and finishing cross-clock domain synchronization of a request path and a response path. Through a request and response full handshake mechanism, any frequency combination of a source clock domain and a target clock domain, data synchronization is carried out between any clock domains, time sequence conflicts caused by superposition of multiple requests are avoided, a response channel READY signal is fixed to be high level, no response blocking scene exists, the deadlock problem of an existing pulse synchronization scheme is thoroughly solved, and the time sequence conflicts caused by superposition of multiple requests are avoided. The characteristic that the in-transit request of a handshake protocol is smaller than or equal to 1 is utilized, the depth needed by the asynchronous FIFO circuit and information between different clock domains are optimized, the AHB bus conversion bridge optimizes the time sequence through scene-based conversion logic, requests of any burst transmission type are achieved, and the synchronization and transmission efficiency is improved.

This invention discloses a method and apparatus for cracking asynchronous encryption circuits. By analyzing the encryption netlist structure of the asynchronous encryption circuit, the control path and data path are extracted. The asynchronous controller in the control path is structurally analyzed and divided into a first group of real paths and a group of potential forged paths. Based on the first group of real paths and the group of potential forged paths, the data path is resynchronized to obtain a simplified circuit. A Boolean satisfiability SAT solver is used to classify the potential forged paths in the simplified circuit, resulting in a second group of real paths and a group of forged paths. Based on the classification results of the first group of real paths, the second group of real paths, and the group of forged paths, the key is recovered. This invention combines the characteristics of asynchronous circuits and encryption methods, transforming the encryption circuit into a classification problem of forged and real paths. By extracting the correlation and distribution characteristics between keys, the circuit is simplified, and the SAT solving speed is accelerated.

The application discloses an automatic synthesis system of an asynchronous pipeline to an asynchronous circuit, adopts a modular architecture, takes a high-level structure description file in a JSON / XML format as input, gradually maps to generate a gate-level netlist and a standard delay format file, and is connected to a commercial back-end design process.The application can automatically map asynchronous design based on an asynchronous structure to an asynchronous circuit, the automatic mapping process can seamlessly process multi-level design representation, the mapping result is stable and cooperatively operated, and timing detection and delay matching of the asynchronous circuit are automatically completed, so that the design efficiency is greatly improved, the automatic delay matching mechanism makes the circuit have good data ready detection and handshaking mechanism, low power consumption, high throughput and no global clock drift sensitivity are realized; in addition, while guaranteeing design readability, level consistency and timing controllability, structure abstraction, delay modeling, testability insertion and other key links of asynchronous design are realized.

The application relates to the chip technical field, in particular to a low-power-consumption asynchronous handshake circuit and an asynchronous circuit, the asynchronous handshake circuit comprising a first flip-flop, a second flip-flop and a third flip-flop; a clock port of the first flip-flop is used for receiving a single pulse signal generated based on a first clock, a data port of the first flip-flop is connected with vdd, and an output port of the first flip-flop is connected with a data port of the second flip-flop; an output port of the second flip-flop is connected with a data port of the third flip-flop, and a clock port of the second flip-flop and an output port of the third flip-flop are both connected with a second clock; if the first flip-flop is an asynchronous low-level effective reset port, the asynchronous handshake circuit further comprises an inverter, an output port of the third flip-flop is connected with a data port of the inverter, and an output port of the inverter is connected with a reset port of the first flip-flop. The application reduces the power consumption of the asynchronous handshake circuit and improves the timing convergence speed of the asynchronous handshake circuit.

The invention relates to the technical field of chips, in particular to a low-power-consumption asynchronous handshake circuit and an asynchronous circuit, and the asynchronous handshake circuit comprises a first trigger, a second trigger and a third trigger; a clock port of the first trigger is used for receiving a single pulse signal generated based on a first clock, a data port of the first trigger is connected with the vdd, and an output port of the first trigger is connected with a data port of the second trigger; an output port of the second trigger is connected with a data port of the third trigger, and a clock port of the second trigger and an output port of the third trigger are both connected with a second clock; if the first trigger is an asynchronous low-level effective reset port, the asynchronous handshake circuit further comprises a phase inverter, an output port of the third trigger is connected with a data port of the phase inverter, and an output port of the phase inverter is connected with a reset port of the first trigger. According to the invention, the power consumption of the asynchronous handshake circuit is reduced, and the time sequence convergence speed of the asynchronous handshake circuit is improved.

The application discloses a high-concurrency processor architecture based on an instruction-level event structure and a scheduling method thereof, is based on RISC-V instructions, and defines the stagnation, successful termination, sequential execution, conditional branching and merging operation of a program through a process algebra (PA-ISA) oriented to an instruction set architecture (ISA). On the basis of the PA-ISA, the dependence relationship between instructions in program execution is described through an instruction-level event structure (IES). The instruction-level event structure model is adopted to describe the dependence relationship between instructions in the program, the instruction concurrency is improved, and good expansibility is achieved. The high-concurrency processor architecture based on the IES is combined with an asynchronous circuit, an event triggering is taken as a basic execution advancing mode, the frequency or energy efficiency is improved, the bypass control mechanism in the out-of-order execution is simplified, and the system reliability is improved. The instruction-level event structure is combined with a double-path instruction fetching mechanism, the instruction waste and performance loss are reduced, and the fault tolerance capability under a large-scale instruction fetching strategy is optimized.

The invention discloses an implementation asynchronous circuit and implementation method of an SM3 algorithm resisting side channel attacks, in the implementation circuit, a handshake protocol is adopted to drive data flow, reliable data transmission and parallel computing without clock synchronization are realized through an asynchronous component, an asynchronous message extension module decomposes a single control flow into multiple paths of concurrent threads by utilizing Splitter, and the multiple paths of concurrent threads are distributed in parallel. And independently updating the physical register block. A plurality of asynchronous dynamic topology prefix adders are arranged in the iterative compression calculation module, operation can be started immediately according to the data arrival sequence, and the problem of power consumption leakage is solved in computational logic through the adders and built-in mask operation. WaitMerge is used as a dynamic synchronization barrier, the completion time of a corresponding adder is accurately captured to trigger subsequent calculation, a periodic clock characteristic peak in electromagnetic radiation is eliminated by using a mutex Merge mutual exclusion mechanism and a clock-free design, the side channel attack resistance protection capability is improved, and the physical defense capability of a chip is enhanced.

The invention provides an asynchronous wake-up circuit system which is divided into an analog circuit part and a digital circuit part. The analog circuit part comprises an oscillator; the digital circuit part comprises a wake-up control module, a clock control module and a system state machine; the clock control module is realized by adopting an asynchronous circuit and is used for outputting a power failure control signal; the oscillator outputs the clock signal in response to the fact that the power-down control signal is at a low level; the oscillator outputs no signal in response to the condition that the power-down control signal is at a high level; the wake-up control module is used for receiving the wake-up signal and outputting a wake-up event; the system state machine is used for controlling mode switching of the system and comprises a sleep mode and a normal working mode. Therefore, the dual problems that the dynamic power consumption in the dormant state cannot be eliminated by the traditional clock gating and the wake-up delay of the power gating technology is long are effectively solved.

The application belongs to the field of asynchronous circuits, and discloses an asynchronous MouseTrap handshake unit with a matching delay and a system, the handshake unit comprising: a delay latch, a self-clock generator and an output inverter; an enabling output end of the self-clock generator is connected with an enabling input end of the delay latch, and output ends of the delay latch are respectively connected with an input end of the self-clock generator and an input end of the output inverter; the delay latch comprises: a Schmitt trigger unit, and a delay module is arranged on an input side of the Schmitt trigger unit, and the delay module is used for making the Schmitt trigger unit produce a delay. The circuit structure of the application is simple, the Schmitt trigger unit can increase the driving capacity of the delay latch, and dynamic power consumption is reduced.

The application discloses a kind of asynchronous multi-granularity memory access control method in microprocessor, asynchronous circuit, memory access module, and memory access control method uses asynchronous clockless control, introduces multi-granularity memory access control mechanism, and memory access granularity is divided into two categories of multi-word memory access and non multi-word memory access to be handled, can flexibly adjust access path and cache strategy according to different memory access granularity, reduce the redundant operation in access time, and greatly improve memory access efficiency.Asynchronous circuit uses delay limited type asynchronous circuit, including asynchronous controller and the asynchronous micro pipeline structure based on "send-relay-receive" structure.Based on the data interaction interface between memory access module of asynchronous circuit and write-back module, memory access state management module, data access update module, instruction / data cache and peripheral interaction interface are included.The application realizes lower dynamic power consumption and higher energy efficiency ratio, with high efficiency and low delay under large data volume operation.

The application discloses a dual-phase lightweight asynchronous circuit based on timing borrowing and a control method thereof. The circuit comprises a control path and a data path. The control path comprises a dual-phase lightweight asynchronous controller and a lightweight asynchronous controller. The data path comprises a storage unit and a combination logic unit. The method comprises: performing asynchronous processing on a register circuit to obtain an asynchronous register circuit; performing division processing on the asynchronous register circuit based on timing constraints to obtain a divided register circuit; introducing the dual-phase lightweight asynchronous controller and the lightweight asynchronous controller to perform margin-aware asynchronous control processing on the divided register circuit to generate a timing pulse control signal. The embodiment of the application can match the control signal with different pulse widths with the requirement of a latch, thereby improving the execution efficiency of instructions and optimizing the power consumption and area of the asynchronous circuit. The application can be widely applied to the technical field of integrated circuit design.

The utility model relates to lithium cell technical field, concretely is a kind of constant-current constant-voltage heating pad control circuit based on PWM. Including asynchronous buck circuit, gate drive circuit, voltage control drive circuit, PWM control circuit, MCU chip, the LCSG_DriveA0 port of asynchronous buck circuit, LCSG_DriveB0 port are sequentially connected the LCSG_DriveA0 port of gate drive circuit, LCSG_DriveB0 port, the VSamp port of asynchronous buck circuit is connected the VSamp port of PWM control circuit, the CON_PWM port of gate drive circuit is connected the CON_PWM port of PWM control circuit, the REF_PWM port of voltage control drive circuit is connected the VRef port of PWM control circuit, the one PE pin of MCU chip is connected the HEAT_OFF port of gate drive circuit, another PE pin of MCU chip is connected the CL_PWM port of voltage control drive circuit. Compared with prior art, realize the dynamic regulation of heating pad current, ensure that constant-current constant-voltage output is to heating pad both ends, improve energy conversion efficiency.

The application discloses a kind of lightweight asynchronous controller circuit and timing control method, the circuit includes double-end asynchronous controller, source controller, receiving end controller, multi-channel handshake control multiplexer and demultiplexer, double-end asynchronous controller includes first double-end asynchronous controller, second double-end asynchronous controller, third double-end asynchronous controller and fourth double-end asynchronous controller;The control method includes: the cyclic transmission of the output request signal and response signal of each module in asynchronous controller circuit is carried out.The application can reduce the power consumption of asynchronous controller circuit and reduce the area of asynchronous controller circuit chip.The application can be widely applied to asynchronous circuit control technical field as a kind of lightweight asynchronous controller circuit and timing control method.

Systems and devices for signal arbitration are described. A plurality of asynchronous circuits can receive a plurality of non-persistent signals representing a plurality of requests and sanitize the plurality of non-persistent signals to generate a plurality of persistent signals. At least one logic circuit can arbitrate the plurality of persistent signals, where each one of the at least one logic circuit can include a mutual exclusive circuit configured to arbitrate two signals. Each logic circuit is one of a first logic circuit, a second logic circuit and a third logic circuit different from one another. A number of copies of the first logic circuit can be implemented in an initial level of arbitration and a number of copies of the second logic circuit and the third logic circuit can be implemented in additional levels of arbitration.