Reconfigurable convolutional neural network acceleration circuit based on asynchronous logic

A convolutional neural network and asynchronous logic technology, applied in the field of reconfigurable convolutional neural network acceleration circuits, to achieve standardized network interfaces, low energy consumption, and low system integration complexity

Inactive Publication Date: 2018-09-14
TSINGHUA UNIV
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Problems solved by technology

Due to the existence of the clock tree, the synchrotron circuit has certain limitations in energy efficiency
At the same time, with the advancement of technology and the i

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  • Reconfigurable convolutional neural network acceleration circuit based on asynchronous logic
  • Reconfigurable convolutional neural network acceleration circuit based on asynchronous logic
  • Reconfigurable convolutional neural network acceleration circuit based on asynchronous logic

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Embodiment Construction

[0031] The implementation of the present invention will be described in detail below in conjunction with the drawings and examples.

[0032] Such as figure 1 As shown, the input data is stored in the off-chip DRAM. Before each operation, the controller first writes the configuration information into the computing unit array. The configuration information determines the scheduling method of the computing unit array and the data multiplexing method. Due to the short time required for this configuration, dynamic configuration is possible, either according to different CNN models or according to different layers of the same model. The data to be processed is read into the input buffer and input register (Mesh architecture), then enters the computing unit array for processing, and finally obtains the output data through the output buffer.

[0033] The basic operation unit (PE) based on asynchronous logic such as figure 2 As shown, the control part of the PE is a three-stage asyn...

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Abstract

The present invention provides a reconfigurable convolutional neural network acceleration circuit based on asynchronous logic. The circuit comprises three portions consisting of basic processing elements (PE), a processing array formed by the PEs and a configurable pooling unit. The circuit employs the basic configuration of a reconfigurable circuit to perform reconfiguration of the pressing arrayfor different convolutional neural network models; the circuit is integrally based on the asynchronous logic to employ a lock clock generated by Click units in an asynchronous circuit to replace a global clock in a synchronous circuit and employ an asynchronous pipeline architecture formed by cascading the Click units; and finally, the circuit employs the asynchronous communicating Mesh network to achieve data reuse to reduce power dissipation through reduction of the number of times of accessing the memory. The circuit provided by the invention is flexible and high in degree of parallelism and data reuse rate, and has a power consumption advantage compared to an acceleration circuit implemented through synchronous logic so as to greatly improve the processing speed of the convolutional neural network in the low power consumption.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, in particular to a reconfigurable convolutional neural network acceleration circuit based on asynchronous logic. Background technique [0002] In recent years, Convolutional Neural Network (CNN) has become the most effective model in the field of image recognition. Due to a series of problems such as slow speed, high power consumption, and low energy efficiency in the operation of convolutional neural networks on traditional computing platforms (such as CPU and GPU), the design of convolutional neural network acceleration circuits is a current research hotspot. [0003] Because the convolutional neural network has the following characteristics: the number of layers of different models is different, the calculation parameters of different layers of the same model are different, and the convolutional layer has a large amount of calculation. If the traditional application-specific...

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Application Information

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IPC IPC(8): G06N3/063
CPCG06N3/063
Inventor 陈虹陈伟佳王登杰
Owner TSINGHUA UNIV
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