The invention provides a multiport register file circuit comprising a write address decoder circuit, a read address decoder circuit, a first memory array, a second memory array, a first input data buffer circuit, a third input data buffer circuit, a first sense amplifier array, a third sense amplifier array, a second input data buffer circuit, a fourth input data buffer circuit, a second sense amplifier array and a fourth sense amplifier array, wherein the first memory array and the second memory array are respectively connected with the write address decoder circuit and the read address decoder circuit, the first input data buffer circuit and the third input data buffer circuit are mutually reversed and are connected with the first memory array, the first sense amplifier array and the third sense amplifier array are connected with the first memory array, the second input data buffer circuit and the fourth input data buffer circuit are mutually reversed and are connected with the second memory array, and the second sense amplifier array and the fourth sense amplifier array are connected with the second memory array. The multiport register file circuit can supply 17 read data ports and 9 write data ports at the same time, and each port has 32-bit data signals, thereby the multiport register file circuit is capable of being applied into a digital signal processor of a very long instruction word structure.