Deep learning accelerator suitable for stacked hourglass network

Abstract

The invention discloses a deep learning accelerator suitable for a stacked hourglass network. A parallel computing layer computing unit improves the computing parallelism, and a data caching module improves the utilization rate of data loaded into the accelerator while accelerating the computing speed; and meanwhile, a data adjuster in the accelerator can carry out self-adaptive data arrangement sequence change according to different calculation layer operations, so that the integrity of acquired data can be improved, the data acquisition efficiency is improved, and the time delay of a memoryaccess process is reduced. Therefore, according to the accelerator, the memory bandwidth is effectively reduced by reducing the number of memory accesses and improving the memory access efficiency while the algorithm calculation speed is increased, so that the overall calculation acceleration performance of the accelerator is realized.

Description

technical field [0001] The invention belongs to the field of neural network training, and in particular relates to a deep learning accelerator suitable for a stacked hourglass network. Background technique [0002] Deep Neural Networks (Deep Neural Networks) is an algorithm model in deep learning. Due to its superior performance compared with traditional algorithms, it has been widely used in various fields such as image classification, target recognition, and gesture recognition. Deep neural networks require a large amount of data calculations. Traditional general-purpose processors have slow calculation speeds due to architectural limitations and cannot meet the needs of real-time applications. Therefore, it is necessary to design dedicated neural network accelerators to provide hardware support for real-time calculations of deep neural networks. . [0003] In the application of gesture recognition, a deep neural network structure called stacked hourglass network (Stacked...

AI Technical Summary

Problems solved by technology

[0004] The stacked hourglass network structure uses a large number of depth-separable convolution modules and multi-level residual structures. During the calculation process, these calculation layers require a large number of calculation units to access the memory to obtain the data required for calculation, and the delay generated during the memory access process It will take up most of the hardware running time. In the past, deep neural network accelerators did not provide optimized computing circuits for the memory access methods of the above-mentioned network structure, so they cannot provide effective acceleration for this structure.

At the same time, additional memory access due to unoptimized circuit design will also bring additional power consumption, which greatly reduces the battery life of devices with this type of accelerator unit.

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