32results about How to "Increase Computational Parallelism" patented technology

The invention belongs to the technical field of the digital video code, particularly to a n-level sub-pixel searching method based on the integer-pixel searching result and a device thereof, characterized by selecting the coordinate position of the top left corner pixel besting matching with the integer-pixel in the reference picture as the center, then performing the n-level sub-pixel searching with variable complexity, obtaining the block matching error function value of the corresponding sub-pixel position point and the integer-pixel position point, comparing the block matching error function value of the corresponding sub-pixel position point and the integer-pixel position point, obtaining the optimum coordinate position at the top left corner of the block corresponding with the blockmatching error function value, wherein n is not less than 2 in the n-level sub-pixel searching. According to the invention, the sub-pixel searching with high level is independent of the sub-pixel searching result of the lower level, thereby increasing the computing parallelism, saving the coding time, effectively advancing the computing parallelism between different sub-pixel levels when the hardware implement; while the device based on the method can make full use of the parallelism characteristic between the sub-pixels with different levels to increase the processing speed of the hardware.

The invention discloses a deep neural network model parallel fully connected layer data exchange method and system. The fully connected layer of the deep neural network is evenly divided into N training units according to the number of neurons to form a deep neural network. A network model in which the fully connected layer model is parallel; in the forward propagation process of the fully connected layer, the forward propagation method such as half-stop is used to process the input data of the front layer by partial arrival, partial calculation, overall output and overall propagation method; in the backward propagation process of the fully connected layer, the residual data of the rear layer is processed by using the backward propagation method such as stop and stop, and the processing methods of quantitative achievement, quantitative calculation and quantitative propagation are adopted; in a forward and backward propagation After completion, the weight data and threshold data of each layer are updated in parallel according to the obtained weight gradient and threshold gradient. It can overlap the data communication and data calculation of the fully connected layer, and accelerate the convergence of the model under the premise of ensuring the correct rate.

The invention brings forward a streamlined acceleration system of an FPGA-based depth convolution neural network. The streamlined acceleration system is mainly formed by an input data distribution control module, an output data distribution control module, a convolution calculating sequence serialization realizing module, a convolution calculating module, a pooling calculating sequence serialization realizing module, a pooling calculating module, and a convolution calculating result distribution control module. Moreover, the streamlined acceleration system comprises an internal system cascade interface. Through the streamlined acceleration system designed by the invention, highly efficient parallel streamlined realization can be conducted on an FPGA, problems of resource waste and effective calculation delays caused by filling operations during calculation are effectively solved, the power consumption of the system is effectively reduced, and the operation processing speed is greatly increased.

The invention discloses a low-updating-frequency satellite navigation software receiver carrier wave tracing method. The method includes that in a single processing period of a carrier wave tracing loop, a GPU completes multiple times of pre-detection accumulation at the same time and estimates carrier wave phase prediction and Doppler frequency error according to multiple related accumulated values; the CPU takes the error as observation quantity of a Kalman filter, corrects a prediction value, configures related accumulation parameters of the GPU of the next period after loop filtering and finally completes carrier wave loop tracing. Compared with conventional carrier wave tracing algorithms, the method has the advantage that stability and accuracy of carrier wave loop tracing can be ensured at low processing frequency.

The invention discloses a processing method and device for multiplication and accumulation operation, used for solving the problems of low data processing efficiency and high power consumption of a computer in the prior art. The method comprises the following steps of distributing a register identifier to each read multiplication and accumulation instruction, after processing each multiplication and accumulation instruction to obtain an add operand, taking the add operand and the register identifier distributed to the multiplication and accumulation instruction as binary groups to cache, reading one binary group as a reference binary group, taking the add operand included in the reference binary group as the first add operand, reading an associated binary group, taking the add operand included in the associated binary group as the second add operand, or, reading data in a register corresponding to the register identifier included in the reference binary group as the second add operand, generating an add calculation result based on the first add operand and the second add operand, and storing the add calculation result in the source of the second add operand. Thereby, the calculation parallelism, the data throughout and the data processing efficiency are increased; and the power consumption of the computer is reduced.

The present invention provides a dual-base forward-looking SAR image geometric correction method and device based on DSP and FPGA. The method includes: DSP sends parameter data to FPGA; FPGA arranges a two-dimensional virtual matrix on the ground plane, and FPGA has Calculation module for k oblique pixel point correspondences; take k unprocessed pixel points and coordinates from the two-dimensional virtual matrix; simultaneously input the acquired coordinates of the unprocessed pixel points into the oblique ground pixel point correspondence relationship Calculation module, each oblique pixel point correspondence calculation module processes the coordinates of an unprocessed pixel point; the calculation results of each oblique pixel point correspondence calculation module of the FPGA are combined into an oblique projection conversion matrix; DSP After the echo is processed in the range direction and the azimuth direction, and the image of the imaging oblique plane is obtained, the image of the imaging oblique plane is corrected into an image of the ground plane in combination with the oblique projection transformation matrix.

The invention relates to the communication field and discloses an authentication method, a network and a system of mobile ad hoc network, which ensures the realization of layer distribution type authentication scheme of cluster mobile ad hoc network; and the requirement on computer processed resources is rational, which can be realized in practical application environment. The invention adopts a group network structure of cluster mobile ad hoc network and advocates layer distribution identity authentication scheme; and the inter-cluster communication used an improved new threshold group signature protocol which improves the original threshold group signature method based on GQ and decreases power index calculation times, improves calculation parallelism and reduces the requirement on processed resources; at the time of initialization, a certificate and a sub key are issued by the system uniformly; cluster heads which have enough numbers of sub keys can jointly recover system keys, thereby carrying out the group signature to issue certificates to new added nodes and using multi-leap serial communication for realizing united group signature.

The present invention discloses a method for 4*4 sub-macroblock parallel intraframe prediction in H.264 / AVC, comprising the steps of: a unified intraframe prediction formula, a reference value array, a reference position table and a concrete implementation step of parallel intraframe prediction. The unified intraframe prediction formula is improved based on the feature of a CUDA and an intraframe prediction formula, by the corresponding prediction formulas of 9 prediction modes to be transformed into one formula to meet the requirements of the CUDA multi-thread single instruction multiple data stream, to achieve the fine-grained parallel in the intraframe prediction sub-macroblock. The reference value array and the reference position table are designed to cooperate with the unified intraframe prediction formula and to completely eliminate a large number of branch statements that affects the parallel algorithm performance. The present invention in the process of the intraframe prediction achieves the pixel level parallel, can effectively use multi-core resources in a GPU to accelerate the process of intraframe prediction, and shorts a coding time.

The invention discloses a data access method, device, hardware accelerator, computing equipment and storage medium. A data access method according to the present invention, comprising: when the input data is received and stored in units of feature vectors, storing the i-th input feature vector in the i%B-th cache in B cache blocks At this time, the storage address of the ith input feature vector is next to the previous storage address in the i%B cache block, where B and i are both natural numbers. Efficient data access in convolutional neural networks with relatively large convolution kernel sizes is achieved. In this way, hardware resources are saved, costs and power consumption are reduced, a higher degree of computing parallelism is supported, and system performance is improved.

This invention discloses one high speed crack sum MAC device, which comprises input and output and four function units, wherein, the unit one is data selection unit; function unit two is semi-bit wide sum up device; function unit three comprise two parts of circuit with one for two and half mode sum up output circuit and two for whole word mode multiplier or sum up pre-process circuit; the function unit four is for whole mode multiplier or sum up output circuit with one as bit in selection structure composed of selector and one bit sum device.

The invention discloses a deep learning accelerator suitable for a stacked hourglass network. The parallel calculation layer calculation unit improves the calculation parallelism, and the data cache module improves the utilization of data loaded into the accelerator internal cache while accelerating the calculation speed. At the same time, the data adjuster inside the accelerator can make adaptive changes in the order of data arrangement according to the operation of the computing layer, which can increase the integrity of the acquired data, improve the efficiency of data acquisition, and reduce the delay of the memory access process. Therefore, while improving the computing speed of the algorithm, the accelerator effectively reduces the memory bandwidth by reducing the number of memory accesses and improving memory access efficiency, thereby realizing the overall computing acceleration performance of the accelerator.

The invention discloses an FPGA hardware implementation method, device and target tracking method of particle filtering based on Bayesian resampling. The FPGA implementation method is as follows: the particle sampling unit reads old particles from the particle cache block, Receive random numbers, and sample and update the read old particles in parallel; the weight update unit reads the observed values, performs weight calculations on the updated particles in parallel, and stores the generated weights in the weight cache block; the Bayesian resampling unit uses Bayesian resampling method, resampling is performed in parallel according to all weight values ​​in the weight cache block, and the index output value is stored back to the corresponding index cache block; the pseudo-random permutation generator reads the address of new particles from the index cache block , randomly assign new particles to each particle cache block to realize the exchange of particles in parallel computing; execute the above steps in a loop until all time steps are iteratively completed to complete the state estimation of the system. The invention can improve the calculation speed of the particle filter system.