Neural network acceleration circuit and method

Abstract

The embodiment of the invention discloses a neural network acceleration circuit and method. The neural network acceleration circuit comprises a data storage module which is used for storing the inputdata needed by the calculation of a neural network, a data caching module which is used for caching the input data output by the data storage module, a calculation module which comprises a plurality of calculation units which are used for calculating the input data output by the data caching module to obtain output data, and a delay processing module which is used for carrying out delay processingon the output data and simultaneously outputting the output data after delay processing. According to the neural network acceleration circuit provided by the embodiment of the invention, the contradiction between the time sequence and the calculation parallelism degree in the neural network acceleration circuit is solved, so that the neural network acceleration circuit can have high calculation parallelism degree when working at a high clock frequency, and the calculation capability of the neural network acceleration circuit is improved.

Description

technical field [0001] Embodiments of the present invention relate to the field of neural networks, and in particular, to a neural network acceleration circuit and method. Background technique [0002] In recent years, neural networks have developed rapidly and are widely used in computer vision and natural language computing. Neural network accelerators are characterized by high energy efficiency and massively parallel computing, and have gradually become a hot research topic. [0003] The neural network acceleration circuit usually uses a high degree of parallelism to quickly complete the massive calculation tasks required by the neural network algorithm. Due to the regularity of the calculation form, the acceleration circuit will first design the basic calculation unit, and use this calculation unit to implement the algorithm. The basic operations, and then a large number of copies of this computing unit to achieve a high degree of computing parallelism. figure 1 It sho...

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Problems solved by technology

[0004] This kind of neural network acceleration circuit requires that the data output by the input data RAM and the weight RAM reach all computing modules at the same clock cycle. The weight RAM is far away, and it will take longer for the corresponding data to reach these computing modules. As a result, when the clock is high, these long traces will cause the signal setup time to be insufficient, thus limiting the highest circuit that can work. Clock frequency; and to enable the circuit to work at a higher clock frequency, timing requirements limit the computational parallelism of the circuit

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