High-speed split multiply accumulator MAC apparatus

A multiply-accumulator and multiply-accumulate technology, which is applied in the field of high-speed split multiply-accumulator MAC devices, can solve problems such as low calculation parallelism and inability to meet multimedia streams, and achieve high calculation parallelism, fast operating frequency, and pipeline no depth effect

CN100465877CInactive Publication Date: 2009-03-04ZHEJIANG UNIV
5 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Publication Date
2009-03-04
Estimated Expiration
Not applicable · inactive patent

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

This invention discloses one high speed crack sum MAC device, which comprises input and output and four function units, wherein, the unit one is data selection unit; function unit two is semi-bit wide sum up device; function unit three comprise two parts of circuit with one for two and half mode sum up output circuit and two for whole word mode multiplier or sum up pre-process circuit; the function unit four is for whole mode multiplier or sum up output circuit with one as bit in selection structure composed of selector and one bit sum device.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The invention relates to a high-speed split multiply-accumulator MAC device for solving multiple multiply-accumulate algorithms. Background technique

[0002] In digital signal processing applications, many operations, such as FIR, IIR, convolution algorithm, and FFT, etc., involve various modes of multiplication or multiply-accumulate operations, and the processing capability of the multiply-accumulate algorithm directly affects the performance of the processor. The multiplier and the multiplicand of the multiplication and accumulation operation are likely to be signed numbers in some cases, and unsigned numbers in other cases, and it is also possible that one is a signed number and the other is an unsigned number; In some occasions, not only multiply-accumulate operations are required, but also multiplication operations of operands with different bit widths, multiply-accumulate operations, and parallel multiply-accumulate operations are required. At...

Examples

Embodiment Construction

[0023] In conjunction with the accompanying drawings, the present invention will be described in detail below.

[0024] exist figure 1 In the example of the present invention, the high-speed split multiplier-accumulator MAC device is divided into four sequentially executed functional units, and each functional unit completes part of the functions of the MAC device.

[0025] I is a functional unit I, which is the data selection logic of the multiplier. It receives multi-bit multiplier and multiplicand data and granularity selection signal, and it selects appropriate data according to the granularity selection signal to output to four multipliers. Its specific logic is:

[0026] Set G_mul high: perform full word (32bit) operation.

[0027] The operands of multiplier 1 are: AH, BH

[0028] The operands of multiplier 2 are: AL, BL

[0029] The operands of multiplier 3 are: AH, BL

[0030] The operands of multiplier 4 are: AL, BH

[0031] G_mul set low: execute half word (16...