117results about "Multistate logic" patented technology

An IC solution utilizing mixed FPGA and MLC arrays is proposed. The process technology is based on the Schottky CMOS devices comprising of CMOS transistors, low barrier Schottky barrier diode (SBD), and multi-level cell (MLC) flash transistors. Circuit architectures are based on the pulsed Schottky CMOS Logic (SCL) gate arrays, wherein a variable threshold NMOS transistor may replace the regular switching transistor. During initialization windows, existing FPGA programming techniques can selectively adjust the VT of the switching transistor, re-configure the intra-connections of the simple SCL gates, complete all global interconnections of various units. Embedded hardware arrays, hardwired blocks, soft macro constructs in one chip, and protocols implementations are parsed. A wide range of circuit applications involving generic IO and logic function generation, ESD and latch up protections, and hot well biasing schemes are presented. The variable threshold transistors thus serve 3 distinctive functions. It acts as an analog device to store directly nonvolatile information in SCL gates. It couples the diode tree logic functions. Finally, it stores and operates large amount of information efficiently. The mixed SCL type FPGA and MLC storages shall emerge as the most compact logic and memory arrays in Si technology. Low power, high performance, and high capacity ICs are designed to mix and replace conventional CMOS-TTL circuits. The idea of multi-value logic composed of binary, ternary, and quaternary hardware and firmware is also introduced.

A new scheme of Schottky FPGA (SFPGA) IC solution is proposed. The chip is organized by embedded analog, memory, and logic units with on chip apparatus and software means to partitioning, altering selected portions of hardware. The process means is based on the combined Schottky CMOS (SCMOS, U.S. Pat. No. 6,590,800) and Flash technology. The circuit means is based on SCMOS-DTL gate arrays. Software means is based on the C++ procedures with levels of LUT. The SFPGA device supports GHz low power ASIC mixed signal product applications with embedded analog, logic, and memory array units. Several multiplexing schemes are disclosed, which accommodate tasks to vary the Vt and transmission line transmission of selected transistor or IO nets, and therefore their analog and digital device properties. A voltage doubler and supply booster and a Digital-Analog-Digital-Translator (DADT) apparatus are also disclosed in accordance with the present invention. Accordingly, the present invention includes control schemes to field program basic circuit element or any critical nets, and to alter the functionality of certain predetermined circuit units, and update array interconnections, accessing stored protocols, algorithms in all chips in the embodiment subsystem of a SFPGA chip sets.

An object of the present invention is to realize an example of configuration that approximately represents a state of quantum spin in a semiconductor device where components as a basic configuration unit are arrayed so as to search a ground state of Ising model. There is disclosed a semiconductor device provided with plural units each of which is equipped with a first memory cell that stores a value which represents one spin of the Ising model by three or more states, a second memory cell that stores an interaction coefficient showing interaction from another spin which exerts interaction on the one spin and a logical circuit that determines the next state of the one spin on the basis of a function having a value which represents a state of the other spin and the interaction coefficient as a constant or a variable.

A non-volatile Boolean logic operation circuit, including: two input ends; an output end; a first resistive switching element M₁, the first resistive switching element M including a positive electrode and a negative electrode; and a second resistive switching element M₂, the second resistive switching element M₂ including a positive electrode and a negative electrode. The negative electrode of the first resistive switching element M₁ operates as a first input end of the logic operation circuit. The negative electrode of the second resistive switching element M₂ operates as a second input end of the logic operation circuit. The positive electrode of the second resistive switching element M₂ is connected to the positive electrode of the first resistive switching element M₁, and a connected end thereof operates as the output end of the logic operation circuit.

A reduced power dissipation integrated circuit. Power dissipation within a CMOS circuit is reduced by substitution of multi-level buses with several thresholds for binary state buses with a single threshold. A significant portion of an IC's power dissipation is consumed by the act of charging and discharging data and address busses within the IC because theses busses possess the highest capacitances of any of the nodes within the part. The present invention uses a series of thresholds from a minimum voltage to a maximum voltage. Below the minimum threshold voltage Vref1, the logic state would be "0". Above the maximum threshold voltage Vrefn, the logic state would be "n". A series of defined thresholds, Vref1, Vref2, . . . Vrefn, between the minimum and maximum voltages define a series of logic states 0, 1, 2 . . . n+1 between 0 and n+1.

A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments to store configuration data for programmable logic devices, field programmable arrays, and many other applications.

A logic circuit comprising a quaternary logic switching circuit which includes a multilevel storage cell (MLSC), and the trinary or variable threshold logic means to yield an improved space, power, and time-efficient performance device is disclosed. The present invention is used for the implementation of a customized new logic design to further improve the cost-effectiveness of the application. Advanced circuit solutions are provided using asynchronous clock controlled functional units which are field programmable. A diode capacitor ladder chain is also used on an on-chip power supply multiplier to support internal high voltage operations. A digital-to-analog-to-digital translation (DADT) apparatus is also provided utilizing the above identified circuits. Finally, a printed circuit board (PCB) net driver with a trinary signal wire provides 50% bandwidth increase over conventional binary solutions.

A control circuit generates an output based on the first signal and the second signal by encoding the output to be a multi-state signal having at least three states. A magnitude of the multi-state signal generated by the controller varies depending on binary states of the first signal and the second signal. The controller utilizes the output (i.e., the multi-state signal) to control a switching circuit. A driver circuit receives the output generated by the control circuit. In one embodiment, the multi-state signal has more than two different logic states. The driver decodes the multi-state signal for generating signals to control switches in the switching circuit. One signal generated by the driver circuit is a pulse width modulation signal; another signal generated by the driver circuit is an enable/disable signal.

The disclosure provides an ICG (integrated clock gating) cell that utilizes a low area and a low power latch. The ICG cell includes a first logic gate that receives an enable signal and generates a latch input. A latch is coupled to the first logic gate and receives the latch input and a clock input. The latch includes a tri-state inverter and an inverting logic gate. The tri-state inverter is activated by a control signal generated by the inverting logic gate. A second logic gate receives the control signal and generates a gated clock.

A Tri-State circuit element (100) composed of Complementary Metal Oxide Semiconductor (CMOS)—devices is described. Said Tri-State circuit element (100) having a data signal input terminal (102) for receiving a data signal, an enable signal input terminal (104) for receiving an enable signal, and an output signal terminal (106) for providing an output signal. Furthermore a Tri-State-Multiplexer circuitry (300) composed of such Tri-State circuit elements (100) is described.

The invention discloses a memristor simulator circuit based on a digital potentiometer. According to a mathematical model of a TiO2 memristor of an HP (Hewlett-Packard) laboratory, discrete analysis is performed on the mathematical model, a discrete model of the mathematical model of the memristor is obtained, and according to the obtained discrete mathematical model, the memristor model of the HP laboratory is realized by using a control circuit and the digital potentiometer. The memristor simulator provided by the invention comprises the digital potentiometer, a high quality instrumentation differential amplifier and a singlechip. Under the condition that a single isolated memristor device of a nanoscale cannot be obtained, the memristor simulator provided by the invention can replace a practical TiO2 memristor to perform design and experiment of relevant circuits of the memristor, and can also be used for other fields in need of the memristor.

A PAM (Pulse Amplitude Modulation) modulator driver is configured to receive a PAM input signal having N input amplitude levels and provide a PAM output signal having N output amplitude levels, where N is an integer. The PAM modulator driver circuit configured to electrically adjust amplitude levels in the PAM output signal.

A multi-level transmitter circuit with substantially constant output impedance has a capacitive transducer connected between a voltage input and ground. A first voltage path connects the voltage input to a first positive voltage source. The first voltage path is controlled by a first control signal. A second voltage path connects the voltage input to a second positive voltage source, less than the first positive voltage source. The second voltage path passes through a diode and is controlled by a second control signal. A third voltage path connects the voltage input to a third voltage source, less than ground, and is controlled by the second control signal. The impedance at the voltage input during the first control signal is substantially the same as the impedance at the voltage input during the second control signal.

Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.