7results about "Multistate logic" patented technology

The invention provides a single-pin multifunctional multiplexing circuit and method and electronic equipment. The single-pin multifunctional multiplexing circuit comprises an upper computer and a charging management chip. And the charging management chip is used for outputting the configuration starting signal from the GPIO pin when the power supply signal received by the power supply input pin is valid. And the upper computer is used for outputting a plurality of parameter configuration signals to the GPIO pin according to a configuration starting signal, so that the charging management chip completes configuration of a plurality of parameters within a first preset time. The charging management chip enters a charging state indication mode after completing the configuration of the plurality of parameters and controls the light state of the LED through the GPIO pin, so that the charging management chip simultaneously realizes the configuration of the plurality of parameters and the light state of the LED only through the GPIO chip, and the packaging pins of the charging management chip are reduced; and the packaging cost of the chip is reduced.

The invention provides a pin expansion method and a pin expansion circuit, the pin expansion method is applied to a controller, the controller comprises N input pins and M output pins, any one of N and M is an integer greater than or equal to 2, and the other one is an integer greater than or equal to 3. The method comprises the following steps: acquiring N * M switch elements, wherein each switch element comprises a control electrode, a carrier input electrode and a carrier output electrode; a carrier input electrode of each switch element is connected with any one of the M output pins, a carrier output electrode of each switch element is connected with any one of the N input pins, and a control electrode of each switch element is connected with an external input pin, so that N * M external input pins are formed through expansion based on the N * M switch elements; the external input pin is an expanded input pin of the controller, and the controller is connected with external equipment through the external input pin.

The invention provides a pin multiplexing circuit, an electronic chip, a sealing chip and a pin multiplexing method, and the pin multiplexing circuit comprises a power-on timing module which is used for starting the timing of a first time after the chip is powered on and generating an input state control signal, an input state control signal is maintained or an output state control signal is generated based on the input detection result in the first time; the input detection module is used for working under the action of the input state control signal, detecting whether an external signal is input at an output pin of the electronic chip and generating an input detection result; the output module is used for working under the action of the output state control signal and transmitting a signal to be output to an output pin; wherein the output pin is a bidirectional pin. According to the invention, the problem that the cost is increased when the ASIC chip is trimmed by adding the enabling pin in the prior art is solved.

A semiconductor integrated circuit, comprising: an input pin; a switch having a drain terminal electrically connected to the input pin, and configured to be in an ON mode or an OFF mode, responsive to a state of the input pin; a first logic block electrically connected to a gate terminal of the switch and a source terminal of the switch; a second logic block electrically connected to the gate terminal of the switch; and a first node electrically connected to the first logic block, the second logic block, and the gate terminal of the switch.

In an embodiment a processing system includes a sub-circuit including a three-state driver circuit, wherein the three-state driver circuit has a combinational logic circuit configured to monitor logic levels of a first signal and a second signal, and selectively activate one of the following switching states as a function of the logic levels of the first signal and the second signal: in a first switching state, connect the transmission terminal to the positive supply terminal by closing the first electronic switch, in a second switching state, connect the transmission terminal to the negative supply terminal by closing the second electronic switch, and in a third switching state, put the transmission terminal in a high-impedance state by opening the first electronic switch and the second electronic switch.

The invention belongs to the technical field of chip manufacturing, and discloses a digital trimming system, which comprises an input signal processing module used for receiving an external input signal, demodulating the external input signal into a serial data signal and a clock signal, and outputting the serial data signal and the clock signal to a digital logic module; the first input end of the digital logic module is connected with the first output end of the input signal processing module to receive the serial data signal, and the second input end of the digital logic module is connected with the second output end of the input signal processing module to receive the clock signal; the control end of the output signal processing module is connected with the first group of output ends of the digital logic module, and the signal input end of the output signal processing module is connected with the M to-be-observed signals; and the control end of the fuse trimming module is connected with the second group of output ends of the digital logic module. By utilizing the system disclosed by the invention, a series of problems existing in a chip trimming scheme in the prior art can be solved.

A chip includes a first modulator configured to receive a first internal signal, and convert the first internal signal into a first output signal including a first pattern, and a second modulator configured to receive a second internal signal, and convert the second internal signal into a second output signal including a second pattern distinct from the first pattern. The chip also includes an observation pad, and a merge circuit coupled to the observation pad, wherein the merge circuit is configured to merge the first output signal and the second output signal into a merged output signal, and output the merged output signal to the observation pad, wherein the merged output signal includes the first pattern and the second pattern, and the first pattern and the second pattern are spaced apart in the merged output signal.