26results about "Multistate logic" patented technology

The invention provides a ternary logic gate circuit, a calculation circuit, a chip and electronic equipment. The ternary logic gate circuit provided by the invention can realize addition and subtraction of 1 to an input logic value. Based on the ternary logic gate circuit, 27 univariate functions of ternary logic are utilized, the ternary logic gate circuit is applied to the ternary logic circuit, the purpose of simplifying the structure of the ternary logic circuit can be achieved, the number of transistors in the ternary logic circuit can be reduced, the power consumption of the ternary logic circuit can be reduced, and the reliability of the ternary logic circuit is improved. And the calculation efficiency of the ternary logic circuit is improved.

An integrated circuit (IC) includes a tristatable output buffer having a control input. The IC includes an input buffer having a buffer output. The IC further includes a delay circuit having a delay circuit input, a first delay circuit output, and a second delay circuit output. The delay circuit input is coupled to the buffer output. The IC also includes a tristate circuit coupled to the first delay circuit output and to the second delay circuit output. The tristate circuit having a tristate circuit output coupled to the control input.

A coupled ring oscillator circuit includes a first ring oscillator, a second ring oscillator and a coupling circuit. The first ring oscillator includes a series of delay stages, each delay stage including an inverter gate. The second ring oscillator includes a series of delay stages, each delay stage including an inverter gate. The coupling circuit includes a coupling cell having a first modified tri-state inverter connected in parallel with one of the inverter gates of the first ring oscillator, and a second modified tri-state inverter connected in parallel with one of the inverter gates of the second ring oscillator.

The invention provides a single-pin multifunctional multiplexing circuit and method and electronic equipment. The single-pin multifunctional multiplexing circuit comprises an upper computer and a charging management chip. And the charging management chip is used for outputting the configuration starting signal from the GPIO pin when the power supply signal received by the power supply input pin is valid. And the upper computer is used for outputting a plurality of parameter configuration signals to the GPIO pin according to a configuration starting signal, so that the charging management chip completes configuration of a plurality of parameters within a first preset time. The charging management chip enters a charging state indication mode after completing the configuration of the plurality of parameters and controls the light state of the LED through the GPIO pin, so that the charging management chip simultaneously realizes the configuration of the plurality of parameters and the light state of the LED only through the GPIO chip, and the packaging pins of the charging management chip are reduced; and the packaging cost of the chip is reduced.

The invention discloses a signal preprocessing circuit, and relates to the technical field of electronic circuits. The circuit comprises a primary multiplexer, a secondary multiplexer, a signal processing module and an information source receiving end, the first-stage multiplexer is provided with a first-stage signal gating port and a first-stage signal output port; the second-stage multiplexer is provided with a second-stage signal gating port and a second-stage signal output port; the signal processing module is provided with a module input port and a module output port; the signal source receiving ends are connected with primary signal gating ports of the primary multiplexer in a one-to-one correspondence manner, primary signal output ports are connected with module input ports in a one-to-one correspondence manner, and module output ports are connected with secondary signal gating ports of the secondary multiplexer in a one-to-one correspondence manner; by setting the on or off state of the first-stage signal gating port and the second-stage signal gating port, a signal obtained by the signal source receiving end is processed by the signal processing module and then transmitted to the preset second-stage signal output port.

A signal sampling device includes an input circuit and a latch circuit. The input circuit is activated in a first period according to a first clock signal to generate a plurality of first output signals according to a plurality of input signals. The latch circuit is activated in a second period according to a second clock signal to generate a plurality of second output signals according to the plurality of first output signals,

The present invention discloses a multi-stage drive data transmission circuit and a data transmission method. The multi-stage drive data transmission circuit includes: a first drive module and a second drive module; wherein, the first drive module includes: a first signal generation unit and a first tri-state driver; the second drive module includes: a second tri-state driver; a first input end of the second tri-state driver is coupled to an output end of the first tri-state driver; the first signal generation unit includes: a first input end, a second input end and an output end; an output end of the first signal generation unit is coupled to a second input end of the first tri-state driver; the first signal generation unit is configured to receive a first signal through its first input end, receive a first feedback signal of the first signal from the second drive module through its second input end, generate a first control signal with an effective signal width wider than that of the first signal according to the first signal and the first feedback signal, and provide the first control signal to the first tri-state driver.

The invention provides a pin expansion method and a pin expansion circuit, the pin expansion method is applied to a controller, the controller comprises N input pins and M output pins, any one of N and M is an integer greater than or equal to 2, and the other one is an integer greater than or equal to 3. The method comprises the following steps: acquiring N * M switch elements, wherein each switch element comprises a control electrode, a carrier input electrode and a carrier output electrode; a carrier input electrode of each switch element is connected with any one of the M output pins, a carrier output electrode of each switch element is connected with any one of the N input pins, and a control electrode of each switch element is connected with an external input pin, so that N * M external input pins are formed through expansion based on the N * M switch elements; the external input pin is an expanded input pin of the controller, and the controller is connected with external equipment through the external input pin.

The invention relates to the technical field of integrated circuits, in particular to a single-port multi-control-mode interface circuit. And the port module comprises a port and a switch unit, the port is connected with the switch unit, the switch unit is respectively connected with the pull-up resistor and the pull-down resistor, and the switch unit has three working states. Each group of comparison units comprises two comparison modules, each comparison module comprises a transistor element, a first MOS (Metal Oxide Semiconductor) tube, a resistive element and a phase inverter, in one comparison module, the transistor element is connected with an input power supply, and the resistive element is grounded; in the other comparison module, a transistor element is grounded, and a resistive element is connected with the input power supply; and the signal control module is used for selecting an output mode according to the output signal of each comparison module in the comparison modules. In this way, the problem that in the prior art, multi-mode control achieved through a single port is complex is solved.

The application discloses a multi-level output driving circuit and method. The circuit comprises a signal selection module configured to select a to-be-transmitted signal of a corresponding channel according to an externally input signal; a weight generation module configured to generate weight data according to the weight of an output eye diagram; wherein the weight of the output eye diagram and the weight data are both multi-bit binary data; a coefficient transmission module configured to perform weight control on the to-be-transmitted signal according to the weight data to generate data containing weight information; and a weight adjustment and data output module configured to perform weight adjustment and pulse amplitude modulation calculation according to weight adjustment control data, the to-be-transmitted signal and the data containing weight information to generate four-level pulse amplitude modulation data PAM4. Compared with the prior art, the embodiment of the application enriches the mode of eye diagram adjustment and can be applied to eye diagram misadjustment caused by different transmission environments.

An integrated circuit (IC) includes a tristatable output buffer having a control input. The IC includes an input buffer having a buffer output. The IC further includes a delay circuit having a delay circuit input, a first delay circuit output, and a second delay circuit output. The delay circuit input is coupled to the buffer output. The IC also includes a tristate circuit coupled to the first delay circuit output and to the second delay circuit output. The tristate circuit having a tristate circuit output coupled to the control input.

The invention provides a pin multiplexing circuit, an electronic chip, a sealing chip and a pin multiplexing method, and the pin multiplexing circuit comprises a power-on timing module which is used for starting the timing of a first time after the chip is powered on and generating an input state control signal, an input state control signal is maintained or an output state control signal is generated based on the input detection result in the first time; the input detection module is used for working under the action of the input state control signal, detecting whether an external signal is input at an output pin of the electronic chip and generating an input detection result; the output module is used for working under the action of the output state control signal and transmitting a signal to be output to an output pin; wherein the output pin is a bidirectional pin. According to the invention, the problem that the cost is increased when the ASIC chip is trimmed by adding the enabling pin in the prior art is solved.

The present application relates to a photon emitter driver that implements logic using a cascaded differential transistor pair. A driver circuit includes a digital input, such as a first digital input and a second digital input. The digital input receives a voltage of a digital high voltage or a digital low voltage. The driver circuit has a clock input, an analog output, a first differential pair transistor connected to the analog output, a second differential pair transistor connected to the analog output, and a voltage limiter connected to the clock input and the second differential pair transistor. The voltage limiter provides different voltages to the second differential pair transistor, which causes the second differential pair transistor to provide analog signals to the analog output, and these analog signals are at different voltage steps at the digital high voltage, the digital low voltage, and between the digital high voltage and the digital low voltage.

Disclosed herein are aspects for configuring a port (120) in an integrated circuit using a configuration state machine. An example aspect begins by determining a current state of internal pull-up (125) and pull-down (127) resistors of the port. The aspect then modifies resistance characteristics of the resistors from the current state. These characteristics indicate a strap configuration (135) of a circuitry connected to the port. The aspect determines a state result based on the strap configuration and the current state. The aspect transitions to a next state based on the state result. The aspect continues by modifying resistance characteristics of the resistors from the next state, indicating a second strap configuration. A second state result is then determined based on the second strap configuration and the next state. The aspect then transitions to a resultant terminal state based on the next state and configures the port to operate in accordance with a port configuration.

A semiconductor integrated circuit, comprising: an input pin; a switch having a drain terminal electrically connected to the input pin, and configured to be in an ON mode or an OFF mode, responsive to a state of the input pin; a first logic block electrically connected to a gate terminal of the switch and a source terminal of the switch; a second logic block electrically connected to the gate terminal of the switch; and a first node electrically connected to the first logic block, the second logic block, and the gate terminal of the switch.

In an embodiment a processing system includes a sub-circuit including a three-state driver circuit, wherein the three-state driver circuit has a combinational logic circuit configured to monitor logic levels of a first signal and a second signal, and selectively activate one of the following switching states as a function of the logic levels of the first signal and the second signal: in a first switching state, connect the transmission terminal to the positive supply terminal by closing the first electronic switch, in a second switching state, connect the transmission terminal to the negative supply terminal by closing the second electronic switch, and in a third switching state, put the transmission terminal in a high-impedance state by opening the first electronic switch and the second electronic switch.

The invention belongs to the technical field of chip manufacturing, and discloses a digital trimming system, which comprises an input signal processing module used for receiving an external input signal, demodulating the external input signal into a serial data signal and a clock signal, and outputting the serial data signal and the clock signal to a digital logic module; the first input end of the digital logic module is connected with the first output end of the input signal processing module to receive the serial data signal, and the second input end of the digital logic module is connected with the second output end of the input signal processing module to receive the clock signal; the control end of the output signal processing module is connected with the first group of output ends of the digital logic module, and the signal input end of the output signal processing module is connected with the M to-be-observed signals; and the control end of the fuse trimming module is connected with the second group of output ends of the digital logic module. By utilizing the system disclosed by the invention, a series of problems existing in a chip trimming scheme in the prior art can be solved.

The present application provides a ternary logic gate circuit, a calculation circuit, a chip, and an electronic device. According to the ternary logic gate circuit provided by the present application, an input logic value can be increased by 1 or can be reduced by 1. On the basis of the ternary logic gate circuit, twenty-seven single-variable functions of three-valued logic are used to apply the ternary logic gate circuit to a ternary logic circuit, thereby achieving the purpose of simplifying the structure of the ternary logic circuit, reducing the number of transistors in the ternary logic circuit, reducing the power consumption of the ternary logic circuit, and improving the calculation efficiency of the ternary logic circuit.

A chip includes a first modulator configured to receive a first internal signal, and convert the first internal signal into a first output signal including a first pattern, and a second modulator configured to receive a second internal signal, and convert the second internal signal into a second output signal including a second pattern distinct from the first pattern. The chip also includes an observation pad, and a merge circuit coupled to the observation pad, wherein the merge circuit is configured to merge the first output signal and the second output signal into a merged output signal, and output the merged output signal to the observation pad, wherein the merged output signal includes the first pattern and the second pattern, and the first pattern and the second pattern are spaced apart in the merged output signal.

The invention relates to a household electrical appliance IO port multiplexing method, device and circuit and a household electrical appliance, the method is applied to an integrated chip circuit of the household electrical appliance, the integrated chip circuit comprises an IO port, the IO port is connected with a silicon controlled rectifier controller, the IO port is also connected with a functional unit, and the method comprises the following steps: detecting the phase of a rectified current; when the zero-point phase of the rectified current is detected, judging the type of the received last control command; if the type of the last control command is to start a silicon controlled rectifier controller, enabling the IO port to be in an output mode, and outputting a driving current from the IO port, the driving current being used for conducting the silicon controlled rectifier controller; after a preset duration, the IO ports are in an input mode, and the IO ports in the input mode are used for receiving input signals from the functional unit. According to the invention, the IO port can be reused, and the cost is reduced.

The invention relates to the technical field of computing equipment, in particular to computing equipment. A computing device includes a logic device, a controller, and a plurality of single boards. Wherein the logic device is connected with at least one single board, the controller is respectively connected with the plurality of single boards, and the controller is connected with the logic device. The logic device is used for configuring the address of the target device on at least one single board, and the addresses of the target devices on the multiple single boards are different. And the controller communicates with the target device on the corresponding single board based on the different addresses. Therefore, when the controller in the application communicates with the target devices on the plurality of single boards, the target devices can be identified, and addresses of the target devices on the plurality of single boards connected with the controller are prevented from conflicting. Moreover, the computing equipment provided by the embodiment of the invention can prevent the addresses of the target devices on the plurality of single boards from conflicting without additionally adding hardware, so that the hardware cost and the system complexity of the computing equipment can be reduced.

The present invention relates to the field of integrated circuit technology, and in particular, to a single-port multi-control mode interface circuit. Port module: comprising a port and a switch unit, wherein the port is connected to the switch unit, wherein the switch unit is respectively connected to a pull-up resistor and a pull-down resistor, and the switch unit has three working states. At least one group of comparison units, each group of comparison modules comprises two comparison modules, wherein the comparison modules comprise a transistor element, a first MOS tube, a resistive element and an inverter, wherein in one of the comparison modules, the transistor element is connected to an input power supply, and the resistive element is grounded; in another comparison module, the transistor element is grounded, and the resistive element is connected to an input power supply; signal control module: selecting an output mode according to the output signal of each comparison module in the comparison module. This solves the problem that it is relatively complicated to realize multi-mode control through a single port in the prior art.

A scan flip-flop circuit includes first and second I / O nodes, a flip-flop circuit, a selection circuit configured to receive a scan direction signal and including input terminals coupled to the first and second I / O nodes and an output terminal coupled to an input terminal of the flip-flop circuit, and first and second drivers configured to receive the scan direction signal and a scan enable signal, each including an input terminal coupled to an output terminal of the flip-flop circuit and an output terminal coupled to a respective first or second input terminal of the selection circuit. Responsive to the scan direction and scan enable signals, one of the first driver is configured to output a first signal responsive to a second signal received at the second input terminal or the second driver is configured to output a third signal responsive to a fourth signal received at the first input terminal.

A scan flip-flop circuit includes first and second I / O nodes, a selection circuit coupled to the first and second I / O nodes and including first through third PMOS transistors arranged in parallel and first through third NMOS transistors arranged in parallel, each including a gate configured to receive a corresponding first through third signal, and an output terminal configured to output one of the first through third signals as a selected signal based on scan direction and scan enable signals, a flip-flop circuit including an input terminal coupled to the output terminal of the selection circuit and an output terminal configured to output an output signal based on the selected signal, first and second drivers coupled to the output terminal and configured to output the first signal to the first I / O node and the second signal to the second I / O node responsive to the selected signal and the scan direction signal.

The invention discloses a channel selection circuit, a driving chip, a display device and electronic equipment, the channel selection circuit is formed by cascading at least one two-channel selection module, and the two-channel selection module comprises a decoding unit for receiving a closing signal and a selection signal and generating a first control signal to a third control signal; and the selection unit is connected with the decoding unit and is used for selectively outputting one of the first input signal and the second input signal received by the selection unit according to the first control signal, the second control signal and the third control signal. According to the channel selection circuit provided by the invention, under the condition that only one-bit control register resource (N + 1 bits) is added, the problem that a 2N channel selection circuit cannot be closed during application is solved, the register resource overhead is saved, and the layout wiring density is reduced.

The present application discloses a signal preprocessing circuit, which relates to the technical field of electronic circuits. The circuit includes: a first-level multiplexer, a second-level multiplexer, a signal processing module, and a signal source receiving end; the first-level multiplexer has: a first-level signal selection port and a first-level signal output port; the second-level multiplexer has: a second-level signal selection port and a second-level signal output port; the signal processing module has: a module input port and a module output port; the signal source receiving end is correspondingly connected to the first-level signal selection port of the first-level multiplexer one by one, the first-level signal output port is correspondingly connected to the module input port one by one, and the module output port is correspondingly connected to the second-level signal selection port of the second-level multiplexer one by one; by setting the conduction or cut-off state of the first-level signal selection port and the second-level signal selection port, the signal obtained by the signal source receiving end is transmitted to a preset second-level signal output port after being processed by the signal processing module.