Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit

Abstract

A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source / drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments to store configuration data for programmable logic devices, field programmable arrays, and many other applications.

Description

RELATED APPLICATION DATA[0001]The present application is a continuation of U.S. Pat. No. 12 / 650,238, filed on Dec. 30, 2009, which claims the benefit of the filing date of U.S. Provisional Application No. 61 / 141,618, filed on Dec. 30, 2008, the disclosures of which is hereby incorporated herein by reference. The application is further related to U.S. application Ser. Nos. 12 / 264,029, 12 / 264,060, and 12 / 264,076, all filed on Nov. 3, 2008 which are hereby incorporated herein by reference.FIELD OF THE INVENTION[0002]The present invention relates to non-volatile configuration circuits which can be programmed one time, or multiple times in some instances. The invention has particular applicability to applications where is it desirable to customize electronic circuits, including programmable logic devices, field programmable gate arrays, etc.BACKGROUND[0003]Field Programmable Gate Arrays (FPGAs) are well-known circuits used in a variety of electronic devices / computing systems. FPGAs offer...

AI Technical Summary

Benefits of technology

This solution allows for efficient and flexible programming of memory cells with reduced energy consumption and minimal additional processing costs, enabling seamless integration into CMOS logic processes and potential for multi-level architectures.

Problems solved by technology

These devices, however, are not optimal, however, as they require additional processing step to embed them within a logic circuit.

Incorporating OTP and MTP memories nonetheless also typically comes at the expense of some additional processing steps.

In addition, since an NMOS device's programming mechanism with channel hot electrons injection is self-limiting, unlike that case of a PMOS with channel hot electron programming, the amount of energy consumption during programming is self-limited for this invention.

However, it is unclear whether the device actually works in the way the inventors claim.

That is, it is not apparent that the channel current will be initiated to induce hot-hole-injection since the state of the floating gate is unknown and there is no available means to couple a voltage unto the floating gate.

This is not a very optimal behavior for a memory device.

The drawbacks of this cell, however, include the fact that the cell and channel 412 must be asymmetric, and the coupling is only controlled using the length dimension of the active regions.

Because of these limitations, it also does not appear to be extendable to a multi-level architecture.

Moreover, it apparently is only implemented as a p-channel device.

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