460 results about "Variable number" patented technology

A computer data signal embodied in a propagation medium is provided. The signal enables a variable number of data transfers and includes an initial connection source code segment and a data transfer source code segment. The initial connection source code segment establishes a connection between at least two devices via predetermined listening ports, with at least one predetermined listening port residing within each device. The initial connection source code segment also dynamically assigns a first data port within a first device, and transmits the address of the first data port to a remaining device via the predetermined listening ports. The data transfer source code segment is for each of the variable number of data transfer operations. The data transfer source code segment dynamically assigns a corresponding second data port within the remaining device and transfers data between the connected devices via the data ports so that the data is substantially simultaneously transferred between a variable number of devices via the data ports. Each pair of first and second data ports is established in response to each listening port connection.

Disclosed is a system that permits a variable number of disparate streams of data to be packaged together as content into a single distinct program referred to as an omnimedia package. A framework definition may be specified and created for the omnimedia package to allow a client set top box to decode the information and provide access to streams comprising video, audio and metadata information. The framework definition may be employed by a broadcast system to create a broadcast stream. A mechanism is described that permits a content provider to define a framework for delivering a package of related content. The framework definition encapsulates information necessary to build, format, transmit and display the disparate content streams. Data may be downloaded to a receiver prior to the broadcast of an associated program. The present invention may be implemented on terrestrial, cable, satellite, VDSL and other transport systems, including those that support upstream communication.

A harmonic suppression mixer for down converting an RF signal to a complex I and Q baseband signal that uses a plurality of switching mixers each with a gain stage to produce a sinusoidal weighted sum of the mixer outputs. Odd harmonics output by each switching mixer is suppressed in the composite signal. A low skew local oscillator (LO) clock generator creates multiple LO phases and drives the mixers. The mixer can be used in low noise direct conversion RF tuners. The mixer is configurable by programming gain stage coefficient values to achieve a variable number of effective mixers used in combination. At low tuning frequencies, all available mixers are programmed with unique coefficients and driven by different LO clock phases to achieve maximum harmonic suppression. At high tuning frequencies, some mixers are paralleled and duplicate coefficients are programmed or mixers are disabled to reduce the number of effective mixers.

A novel interpolating phase detector for use in a multiphase PLL is described comprising an array of individual phase comparators, all operating at essentially the same operating point which permits the circuits to be designed simultaneously for high speed and for low power consumption. Two adjacent phase outputs of a multi-phase VCO may be selected and interpolated in between, by selectively attaching a variable number of phase comparators to each phase output and summing their phase error outputs. By varying the number of phase comparators attached to each phase output, interpolation can be achieved with high linearity.

A method and computer graphics system capable of super-sampling and performing programmable real-time filtering or convolution are disclosed. In one embodiment, the computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples. The sample buffer, which is coupled to the graphics processor, is configured to store the samples and may be configured to double-buffer at least part of the stored samples. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the sample buffer to filter into an output pixel. The sample-to-pixel calculation unit performs the filter process in real-time, and may be programmable to use a number of different filter types in.a single frame. The sample buffer may be super-sampled, and the samples may be positioned according to a regular grid, a perturbed regular grid, or a stochastic grid.

The invention relates to a computer device comprising a memory 108 for storing audio signals 114, in part pre-recorded, each corresponding to a defined source, by means of spatial position data 116, and a processing module 110 for processing these audio signals in real time as a function of the spatial position data. The processing module 110 allows for the instantaneous power level parameters to be calculated on the basis of audio signals 114, the corresponding sources being defined by instantaneous power level parameters. The processing module 110 comprises a selection module 120 for regrouping certain of the audio signals into a variable number of audio signal groups, and the processing module 110 is capable of calculating spatial position data which is representative of a group of audio signals as a function of the spatial position data 116 and instantaneous power level parameters for each corresponding source.

A method and computer graphics system for rendering images using programmable sample positions is disclosed. In one embodiment, the computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples using a sample positioning algorithm selected from a programmable memory or generated by programmable hardware. The sample buffer, which is coupled to the graphics processor, may be configured to store the samples. The sample buffer may be super-sampled and double buffered. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the sample buffer to filter into an output pixel. The sample-to-pixel calculation unit performs the filter process in real-time, and may use a number of different filter types. The algorithms used to position the samples may position the samples according to a regular grid, a perturbed regular grid, or a stochastic grid.

An architecture and method for dynamically allocating and deallocating memory for variable length packets with a variable number of virtual lanes in an Infiniband subnetwork. This architecture uses linked lists and tags to handle the variable number of Virtual Lanes and the variable packet sizes. The memory allocation scheme is independent of Virtual Lane allocation and the maximum Virtual Lane depth. The disclosed architecture is also able to process Infiniband packet data comprising variable packet lengths, a fixed memory allocation size, and deallocation of memory when packets are either multicast or unicast. The memory allocation scheme uses linked lists to perform memory allocation and deallocation, while tags are used to track Infiniband subnetwork and switch-specific issues. Memory allocation and deallocation is performed using several data and pointer tables. These tables store packet data information, packet buffer address information, and pointer data and point addresses. The tags allow the memory allocation and deallocation process to correctly handle good and bad packets, as well as successive blocks within a data packet.

An apparatus and method for automatically controlling voltages used to drive LED loads. A battery voltage can be boosted to a selected drive voltage level connected to current sources for driving the LED loads. The drive voltage level is selected by a controller using a headroom detect component to measure a headroom voltage across the current source. The controller adjusts the drive voltage level to maintain the headroom voltage within a predetermined operating range. The drive voltage may be used to drive a variable number of LEDs or a plurality of different LED loads connected in parallel without manual readjustment of drive voltage.

A device and method of providing a versatile illuminated panel for walls, product displays, and other surfaces is described. Panels are constructed from a variable number of rectangular illuminated tiles, where the tiles mate edge-to-edge so as to create a nearly seamless visual panel effect. Illumination within each tile is uniform to also create a nearly seamless visual panel effect. End-users may create panels of varying sizes and shapes by using different quantities of a standard tile. The software within the invention automatically determines the number and arrangement of tiles within each assembled panel. Each tile comprises a plurality of illuminators, an optical means to distribute light from the illuminators uniformly across the tile, and at least one communication interface. In one embodiment the tiles are linked into a communications tree-structure; and the location of each tile within the tree constitutes its logical address.

In a microprocessor that has an instruction set architecture in which the instructions may include a variable number of prefix bytes, an apparatus for efficiently extracting instructions from a stream of undifferentiated instruction bytes. Decode logic determines which byte is an opcode byte for each instruction of a plurality of instructions within the stream of undifferentiated instruction bytes. The opcode byte is the first non-prefix byte of the instruction. The decode logic accumulates prefix information onto the opcode byte of the instruction for each instruction of the plurality of instructions. A queue holds the stream of undifferentiated instruction bytes and the accumulated prefix information. Extraction logic extracts the plurality of instructions from the queue in one clock cycle independent of the number of prefix bytes included in each of the plurality of instructions.

Systems and methods that adapt to the weather and clutter in a weather radar signal and apply a frequency domain approach that uses a Gaussian clutter model to remove ground clutter over a variable number of spectral components that is dependent on the assumed clutter width, signal power, Nyquist interval and number of samples. A Gaussian weather model is used to iteratively interpolate over the components that have been removed, if any, thus restoring any overlapped weather spectrum with minimal bias caused by the clutter filter. The system uses a DFT approach. In one embodiment, the process is first performed with a Hamming window and then, based on the outcome, the Hamming results are kept or a portion of the process is repeated with a different window. Thus, proper windows are utilized to minimize the negative impact of more aggressive windows.

Systems and methods to provide a channelized Optical channel Data Unit flexible (ODUflex) include receiving a signal; multiplexing the signal into a Tributary Slot (TS) of the channelized ODUflex, wherein the channelized ODUflex supports a variable number of TSs and a variable size; and mapping the channelized ODUflex into an Optical channel Transport Unit k/Cn (OTUk/Cn) (k=1, 2, 3, 4), (n=1, 2, 3, . . . ). A network element configured to operate in an OTN network includes one or more ports coupled to switching circuitry, wherein a first port is configured to receive a signal, wherein the switching circuitry is configured to multiplex the signal into a TS of a channelized ODUflex, wherein the channelized ODUflex supports a variable number of TSs and a variable size (rate), and wherein a second port is configured to map the channelized ODUflex into an OTUk/Cn.

A method and apparatus is disclosed herein for a bus controller that supports a flexible bus protocol that handles pipelined, variable latency bus transactions while maintaining point-to-point (P2P) FIFO ordering of transactions in a non-blocking manner. In one embodiment, the apparatus includes a bus controller to receive a plurality of bus transactions at a first incoming port from a bus. The bus controller is configured to process the plurality of bus transactions in a pipelined manner, maintaining P2P FIFO ordering of the plurality of bus transactions even when the plurality of bus transactions take a variable number of cycles to complete.

The invention provides a human-machine interaction technology for the hand gesture recognition based on variable number of cameras by adopting an infrared light source. In the method, a user does not need to wear any assistive device, and the method has the outstanding characteristics of wide application range, comprehensive motion sensing capabilities, low production cost, low computation complexity and the like. In the invention, the gesture and location of a hand are modeled by using a virtual reality method, and a template database is generated. In practical use, background-removed input images of a plurality of cameras are compared with items in the template database, and an item with the minimum contrast difference in the database is regarded as an initial recognition result of the gesture of the hand. In order to obtain a more stable recognition result, a smoothing filter method is adopted to correct the initial recognition result so as to provide more stable recognition data for the user. In addition, sequences of hand motions in a continuous period can be recognized by the human-machine interaction technology, and rich options are provided for the human-machine interaction.