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A semiconductor memory aging test system and method

The invention belongs to the technical field of semiconductor memory test and discloses a semiconductor memory aging test system and a method. The system comprises a test core board and a test board.The test core board generates a t signal and a power signal according to that instruction of the upper computer, and after the test signal and the power signal are adjusted, the test signal is provided to a DUT, and the DUT output signal is compared with a preset value to obtain a preliminary test result which is partitioned and stored, and is uploaded to the upper computer; the test board is usedfor carrying DUT, providing clock signal and chip selection signal for DUT. A single test board is provided with a plurality of t bits, and DUT aging test can be carried out by a single DUT or by multiple DUTs at the same time. By outputting various types of test signals on the test core board, and adjusting the delay time of the test signal, strengthening the processing of driving, waveform control, and compensating the power signal, and storing the test results in the partitioned storage area respectively, the functions of management of single DUT test process control and failure analysis in aging test are realized, and the same test number of DUT is increased, which reduces the test resource overhead.
Owner:武汉精鸿电子技术有限公司
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