The invention discloses a weight adjustment circuit for variable-resistance synapses, which relates to the fields of integrated circuits and neural networks, and is used for carrying out weight adjustment on variable-resistance synapses. The circuit is composed of a weight enhancement adjustment subcircuit A (LTP (long term potentiation) adjustment) and a weight inhibition adjustment subcircuit B (LTD (long term depression) adjustment), wherein the two subcircuits respectively contain a charging pole, a discharging pole, a charge storage pole and an output pole. The core of the circuit is implemented by using an analog circuit mode, therefore, the number of transistors required by the circuit is greatly reduced; and meanwhile, through the setting of the bias voltage on a discharge tube in the discharge pole, the size of a weight adjustment time window can be adjusted conveniently. The circuit disclosed by the invention follows an STDP (spike timing dependent plasticity) learning rule, and LTP and LTD pulse outputs are generated according to the activities of nerve units at the two ends of the variable-resistance synapses so as to carry out corresponding weight adjustment on the variable-resistance synapses. The circuit disclosed by the invention is simple in structure, convenient in parameter adjustment, and suitable for applications, such as weight adjustment on electronic synapses of a large-scale neural network, and the like.