3 results about "Pipeline scheduling" patented technology

This disclosure provides interleaved pipeline scheduling methods, apparatus, devices, and storage media, particularly relating to the computer technology field, and more particularly to the artificial intelligence technology field, including deep learning, neural networks, and parallel computing. [Solution] A specific solution includes obtaining micro-batch scheduling parameters based on the pipeline splitting dimension, interleave dimension, and cumulative count; determining the transmission interval of a micro-batch requiring cache scheduling based on the micro-batch scheduling parameters; and performing cache scheduling on the computation results of the micro-batch requiring delayed transmission based on the transmission interval and cache units. According to this disclosure, a cache unit, for example, a cache queue, can be created, the computation results of some computation units can be cached in the cache unit, and the computation results can be transmitted with a delay. This allows for delayed transmission of the computation results of some micro-batches, improving the applicability of interleaved pipeline scheduling.

The application provides a data transmission module, a control method and an optoelectronic hybrid computing system. The data transmission module is applied to a runtime subsystem of the optoelectronic hybrid computing system, and the data transmission module is used for providing a data transmission management interface for the runtime subsystem. The data transmission module comprises a data transmission interface unit, a memory management unit, a direct memory access control unit and a pipeline scheduling unit. The data transmission interface unit is used for receiving a transmission call of the runtime subsystem. The memory management unit is used for managing allocation and release of on-board memory of a field programmable gate array. The direct memory access control unit is used for controlling access transmission between a graphics processor and the field programmable gate array. The pipeline scheduling unit is used for pipeline execution of data transmission and optoelectronic computing. In this way, the data transmission between the GPU and the FPGA can be managed by the data transmission module, and a complete transmission process of GPU-FPGA-GPU can be supported.

The application relates to a general-purpose GPU-oriented JPEG decoding batch processing and double-buffer pipeline scheduling method, belongs to the field of heterogeneous computing and image processing, and comprises the following steps: obtaining code stream data of a to-be-decoded JPEG image; performing entropy decoding and inverse quantization on the code stream data by a CPU to obtain a plurality of DCT coefficient blocks; if the size of the to-be-decoded JPEG image is not smaller than a preset size threshold, the DCT coefficient blocks are cached in a ring buffer located in a host memory; the state of the ring buffer is continuously monitored; when a preset batch triggering condition is met and a GPU is detected to be available, the DCT coefficient blocks in the ring buffer are batch copied to GPU display memory; based on the DCT coefficient blocks in the GPU display memory, integer IDCT transformation and color space conversion calculation are performed by the GPU to obtain an original image corresponding to the to-be-decoded JPEG image, and the original image is read back to the host memory; wherein the double-buffer pipeline is adopted to perform batch copying of the DCT coefficient blocks, integer IDCT transformation, color space conversion calculation and reading back of the original image. Efficient real-time decoding is realized.