31 results about "Reservation station" patented technology

Enabling high-performance Scalable Matrix Extension (SME) instruction issue in processor devices is disclosed herein. In some aspects, a processor device comprises a reservation station circuit configured to perform, during a first phase, a reduced-precision vector accumulator (ZA) tracking operation on micro-ops for which corresponding vector (Z) registers and corresponding predicate (P) registers are ready. Based on the reduced-precision ZA tracking operation, the reservation station circuit selects a first micro-op and a second micro-op having no Read-After-Write (RAW) hazard with respect to the ZA registers. During a subsequent second phase, the reservation station circuit performs a full-precision ZA tracking operation on the first micro-op and the second micro-op, and selects one as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the ZA registers. The reservation station circuit then issues the selected micro-op for execution.

The invention discloses a two-order loading value prediction design system based on path history information. The two-order loading value prediction design system comprises a path history register, a loading instruction address prediction table, a loading address reservation station, a value prediction table and a speculation conflict detection table, the invention also discloses a two-order loading value prediction design method based on path historical information. The method comprises the following steps: S1, predicting a memory address possibly accessed by a loading instruction through a loading instruction address prediction table; s2, storing the predicted memory address into a loading address reservation station; s3, when the load assembly line is idle, entering the load assembly line in advance, and accessing the data cache by using the memory address in the loading address reservation station; and S4, when the memory access instruction reaches a renaming stage, checking whether a predicted value exists in the value prediction table or not. The value of the loading instruction is predicted through the path information, and the prediction process can be more accurate.

Disclosed in the present application are an accelerator instruction processing method and apparatus, and an electronic device. The method is executed by a processor, and comprises: dispatching an accelerator instruction to a shared reservation station of an execution unit of an accelerator and an execution unit of a processor; determining whether there is a free entry in an accelerator instruction data transmission unit in the processor, and in response to there being a free entry in the accelerator instruction data transmission unit, issuing the accelerator instruction from the shared reservation station to the execution unit; monitoring a write-back port of the execution unit, and determining configuration information of the execution unit; on the basis of the configuration information of the execution unit, writing the accelerator instruction back to a re-order buffer area; and controlling the accelerator instruction data transmission unit to sequentially send instruction information of the accelerator instruction to the execution unit of the accelerator.

The invention discloses a speculative fusion design structure supporting discontinuous microcodes. The speculative fusion design structure is composed of a fusion predictor, a microcode queue, a reservation station and a fusion historical queue. The invention further discloses a speculation fusion optimization method supporting the discontinuous microcodes, which comprises the following steps of: S1, accessing the fusion predictor, acquiring fusion information of the corresponding microcodes, and storing the hit corresponding microcodes and the fusion information carried by the microcodes into a microcode queue; s2, after the microcodes and fusion information carried by the microcodes are stored in a microcode queue, internal correlation check and deadlock check of the microcodes are carried out; and S3, checking the correctness of microcode fusion in a submission stage after microcode fusion. According to the method, effective detection can be carried out during non-continuous microcode fusion, the problem of execution conflicts generated after non-continuous microcode fusion is avoided, the confidence degree of the prediction path is dynamically monitored, and the prefetching range and the prefetching accuracy are both considered.

An apparatus and method for efficient matrix processing in a clustered processor core. For example, one embodiment of a processor comprises: a front end to fetch and decode a plurality of instruction strands to generate a corresponding plurality of microoperations, including matrix processing microoperations; a reservation station to schedule the microoperations for execution in accordance with a first scheduling mode; out-of-order execution circuitry to execute the microoperations; and a detector to determine a density of the matrix processing microoperations within an interval and to signal to the reservation station to implement a second scheduling mode when the density of matrix processing microoperations reaches or exceeds a first threshold.

The invention provides a memory access instruction re-execution method and device, equipment and a storage medium, and the method applied to a processor comprises the steps: determining a re-execution event of a memory access instruction, and determining a target feedback port from at least one preset feedback port based on the re-execution event or a target pipeline level where the memory access instruction is located; and sending a retransmission request to the reservation station through the target feedback port, so that the reservation station retransmits the memory access instruction based on the retransmission request. According to the technical scheme, the memory access instruction re-execution efficiency can be improved, and the execution efficiency of the processor is further improved.

The application discloses a method, device and storage medium for selecting instructions, and belongs to the computer field. The method comprises the following steps: sorting queue ready information in a reservation station according to priorities, obtaining a ready queue and a mask of a queue pointer of the reservation station, and the all-1 part of the mask being a highest priority area; performing an AND operation on the ready queue and the mask, and performing an AND operation on the ready queue and the inverse code of the mask, obtaining and acquiring queue bits corresponding to ready instructions in the AND operation result through a priority encoder; when the acquired queue bits exist in the mask AND operation result, selecting the ready instructions in the mask AND operation result; otherwise, selecting the ready instructions in the inverse code AND operation result. The application aims at solving the problems of high energy consumption and high calculation cost of a processor in selecting currently highest priority ready instructions.

A reservation station that includes a storage circuit with multiple full and partial entries is disclosed. A given store-data entry of the multiple partial entries may store less data than a given full entry of the multiple full entries. A control circuit may receive a load / store operation and, in response to a determination that the load / store operation includes only a single source, store the load / store operation in a particular partial entry of the multiple partial entries.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for bypassing in out of order processing. One of the methods includes storing, in a reservation station, a bypass value that indicates a stage of an execution pipeline used to execute a producer instruction; selecting, using the bypass value, output data from the stage of the execution pipeline from data generated by at least two execution pipelines used to execute the producer instruction; and executing a consumer instruction stored in the reservation station associated with the bypass value using the selected output.

Enabling high-performance Scalable Matrix Extension (SME) instruction issue in processor devices is disclosed herein. In some aspects, a processor device comprises a reservation station circuit configured to perform, during a first phase, a reduced-precision vector accumulator (ZA) tracking operation on micro-ops for which corresponding vector (Z) registers and corresponding predicate (P) registers are ready. Based on the reduced-precision ZA tracking operation, the reservation station circuit selects a first micro-op and a second micro-op having no Read-After-Write (RAW) hazard with respect to the ZA registers. During a subsequent second phase, the reservation station circuit performs a full-precision ZA tracking operation on the first micro-op and the second micro-op, and selects one as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the ZA registers. The reservation station circuit then issues the selected micro-op for execution.

Enabling high-performance Scalable Matrix Extension (SME) instruction issue in processor devices is disclosed herein. In some aspects, a processor device comprises a reservation station circuit configured to perform, during a first phase, a reduced-precision vector accumulator (ZA) tracking operation on micro-ops for which corresponding vector (Z) registers and corresponding predicate (P) registers are ready. Based on the reduced-precision ZA tracking operation, the reservation station circuit selects a first micro-op and a second micro-op having no Read-After-Write (RAW) hazard with respect to the ZA registers. During a subsequent second phase, the reservation station circuit performs a full-precision ZA tracking operation on the first micro-op and the second micro-op, and selects one as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the ZA registers. The reservation station circuit then issues the selected micro-op for execution.

Systems and methods related to a processor with opportunistic bypass of dispatch buffer and reservation station are disclosed herein. The microarchitecture of the processor can determine when conditions exist for the dispatch buffers, reservation station, or other components of an instruction pipeline, to be bypassed by an instruction. One or more components may be bypassed after at least a portion of the instruction pipeline is flushed or ignored. Instructions may bypass one or more components if the source operands of the instruction are ready, there is sufficient space at the destination bypass path, and if the bypassed component is empty. Systems and methods as disclosed herein may improve the efficiency of processing instructions and reduce penalties for branch interpretations and other errors.

A reservation station design method for vector execution units includes: S1, receiving an instruction by a reservation station, decoding the number of ticks for executing the instruction, and extracting an address of each source operand; S2, determining whether each source operand is ready; selecting a specific instruction slot to store the instruction, monitoring a bypass path, and pulling up a status bit of each not-ready source operand; S3, sorting non-transmitted instructions, determining a specific instruction according to a sorting result, and transmitting the specific instruction to a vector execution unit, and sending out a prewrite-back signal; and S4, setting hold signals, and blocking an instruction to be blocked; and when the address of each source operand corresponding to any one non-transmitted instruction is identical with an address in the prewrite-back signal, counting ticks, and in the last tick, transmitting a corresponding non-transmitted instruction to the vector execution unit for execution.

A reservation station that includes primary and secondary storage circuits is disclosed. The primary storage circuit may include multiple full entries, while the secondary storage circuit includes multiple store-data entries. A given store-data entry of the multiple store-data entries stores a subset of the information stored in a given full entry of the multiple full entries. In response to a determination that a store address associated with a particular store operation, stored in particular full entry of the multiple full entries, has been available for use for a threshold number of cycles without store data associated with the particular store operation being available for use, a control circuit may transfer the particular store operation to a particular store-data entry of the multiple store-data entries.

Systems and methods related to a processor with opportunistic bypass of dispatch buffer and reservation station are disclosed herein. The microarchitecture of the processor can determine when conditions exist for the dispatch buffers, reservation station, or other components of an instruction pipeline, to be bypassed by an instruction. One or more components may be bypassed after at least a portion of the instruction pipeline is flushed or ignored. Instructions may bypass one or more components if the source operands of the instruction are ready, there is sufficient space at the destination bypass path, and if the bypassed component is empty. Systems and methods as disclosed herein may improve the efficiency of processing instructions and reduce penalties for branch interpretations and other errors.

The invention discloses a prediction and instruction fetching system based on a recovery path. The system comprises a main preceding-stage assembly line, a recovery path preceding-stage assembly line, a rear-end assembly line and a multi-path branch system, the invention also discloses a prediction and instruction fetching method based on the recovery path, and the method comprises the following steps: S1, the main preceding stage pipeline carries out instruction fetching and decoding according to the branch prediction path, and the recovery path preceding stage pipeline carries out instruction fetching and decoding according to the reverse direction of the branch prediction path; s2, if the result of the branch prediction path is correct, data in the cache of the recovery path is emptied, and branch information in the multipath branch reservation station is removed; and S3, if the result of the branch prediction path is wrong, clearing the instruction stream in the main preceding stage assembly line and the branch information in the multipath branch reservation station. According to the method, by widening the predicted instruction fetching width and predicting the main path and the recovery path of instruction fetching in parallel, when the main path is predicted to be wrong, the recovery path is used for filling a rear-end assembly line, so that the penalty is reduced.

A reservation station that includes a storage circuit with multiple full and partial entries is disclosed. A given store-data entry of the multiple partial entries may store less data than a given full entry of the multiple full entries. A control circuit may receive a load / store operation and, in response to a determination that the load / store operation includes only a single source, store the load / store operation in a particular partial entry of the multiple partial entries.

A reservation station that includes primary and secondary storage circuits is disclosed. The primary storage circuit may include multiple full entries, while the secondary storage circuit includes multiple store-data entries. A given store-data entry of the multiple store-data entries stores a subset of the information stored in a given full entry of the multiple full entries. In response to a determination that a store address associated with a particular store operation, stored in particular full entry of the multiple full entries, has been available for use for a threshold number of cycles without store data associated with the particular store operation being available for use, a control circuit may transfer the particular store operation to a particular store-data entry of the multiple store-data entries.

The invention discloses a processor chip defense method for ghost attack based on control flow misprediction, and belongs to the field of computer system structure security. The method comprises the following steps of: performing key security control in a register renaming stage, an instruction transmitting stage and an execution finishing stage of a processor: firstly, dynamically allocating an NSESL level for each instruction, and judging whether to label a target register according to the NSESL level; secondly, in an instruction transmitting stage, whether the transmission instruction is allowed to be transmitted is judged based on the NSESL and the label state; finally, after the branch instruction is analyzed, the NSESL of the instruction in the reservation station is decreased progressively, and label clearing operation is executed. The method is suitable for a processor architecture supporting out-of-order execution and branch prediction, and on the premise that the performance is not obviously influenced, speculation execution security threats caused by ghost attacks based on control flow misprediction are effectively resisted.

Systems and methods related to a processor with opportunistic bypass of dispatch buffer and reservation station are disclosed herein. The microarchitecture of the processor can determine when conditions exist for the dispatch buffers, reservation station, or other components of an instruction pipeline, to be bypassed by an instruction. One or more components may be bypassed after at least a portion of the instruction pipeline is flushed or ignored. Instructions may bypass one or more components if the source operands of the instruction are ready, there is sufficient space at the destination bypass path, and if the bypassed component is empty. Systems and methods as disclosed herein may improve the efficiency of processing instructions and reduce penalties for branch interpretations and other errors.

The present application relates to the technical field of microprocessor, and particularly relates to a RISC-V instruction set remainder instruction implementation method and system, the present application is to CPU out-of-order execution, instruction from the instruction fetch unit enters the instruction decoding unit, and instruction decoding is carried out; the instruction after decoding is carried out in the renaming unit and the renaming of the destination register is carried out, and the remainder instruction is optimized; if the remainder instruction does not satisfy the optimization condition, the instruction after renaming enters the reservation station, and then enters the execution unit for execution; the instruction after execution is submitted through the reordering cache, and the division instruction code cache resource allocated in the renaming stage is released. The present application realizes the function of the remainder instruction by increasing the remainder instruction acceleration unit in the renaming stage, when the division and remainder instruction pairing appears, the destination register of the remainder instruction is mapped to the physical register of the division instruction write remainder, the remainder generated by the division instruction is taken, and the remainder instruction execution efficiency is high.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for issue pipe sharing. One of the methods includes concurrently issuing a plurality of instructions to different execution units using selection logic to select which source data elements to obtain from the N read ports into the PRF by a process that includes a physical register file (PRF), a plurality of execution units, and a reservation station (RSV) that includes a plurality of issue pipes.

Controlling instruction issue rate using credit-based mechanisms in processor devices is disclosed herein. In some aspects, a processor device comprises a credit logic circuit that is communicatively coupled to a reservation station (RS) circuit, and that comprises a credit counter. The credit logic circuit receives an instruction issue indication for an instruction from the RS circuit during a time interval. The credit logic circuit decrements a value of a credit counter. The credit logic circuit also determines whether the value of the credit counter equals or is less than a blocking threshold, and, if so, asserts a block signal to the RS circuit. The RS circuit is configured to receive the block signal, and, responsive to receiving the block signal, block further instruction issuance during the time interval.

Controlling instruction issue rate using credit-based mechanisms in processor devices is disclosed herein. In some aspects, a processor device comprises a credit logic circuit that is communicatively coupled to a reservation station (RS) circuit, and that comprises a credit counter. The credit logic circuit receives an instruction issue indication for an instruction from the RS circuit during a time interval. The credit logic circuit decrements a value of a credit counter. The credit logic circuit also determines whether the value of the credit counter equals or is less than a blocking threshold, and, if so, asserts a block signal to the RS circuit. The RS circuit is configured to receive the block signal, and, responsive to receiving the block signal, block further instruction issuance during the time interval.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for sharing tag comparators. One of the methods includes obtaining, by a shared comparator, a broadcast destination tag, wherein the shared comparator operates for an instruction stored in the RSV; selecting, by a selection logic module, a source tag from among tags that include a tag of a first source and a tag of a second source, wherein the first source and the second source are used by the instruction; and comparing, by the shared comparator, the selected tag and the broadcast destination tag.

The invention relates to a reservation station port allocation method and device, an electronic device, a storage medium and a program product. The method comprises the following steps: setting an effective condition of each allocation port of each reservation station; arranging the distribution ports of each reservation station according to a rule that the reservation stations are ranked and all the distribution ports of all the reservation stations are ranked according to effective conditions; calculating an allocation identifier of each allocation port of each reservation station according to an arrangement result; which allocation port of which reservation station to which an instruction is to be allocated is determined based on a request identification of the instruction transmitted to the reservation station and an allocation identification of each allocation port. Therefore, not only can the distribution port of the reservation station be efficiently distributed to the instruction transmitted to the reservation station, but also load balancing of the reservation station can be realized, so that instruction transmission blockage caused by full load of a single reservation station can be avoided.

A method, system, and apparatus for a computing device includes a plurality of processing cores and a reservation station including circuitry configured to coordinate selection of instructions for out-of-order execution on the plurality of processing cores, the reservation station including a wait buffer and a plurality of clusters, wherein when the reservation station predicts that a load instruction will result in a cache miss, the reservation station is configured to execute the load instruction using one of the plurality of clusters and store one or more dependent instructions of the load instruction in the wait buffer, and when execution of the load instruction is completed, the reservation station is configured to retrieve the dependent instructions from the wait buffer and execute the dependent instructions using the plurality of clusters.

An apparatus and method for efficient reservation station dependency tracking. For example, one example of a processor comprises: a decoder to decode a plurality of instructions into a plurality of microoperations; and a reservation station to track dependencies associated with the plurality of microoperations, each dependency to be tracked by indicating a link between a result of each producer microoperation and a corresponding source of each consumer microoperation, wherein the reservation station is to dynamically allocate resources of a tracking data structure based on the link indicated for each dependency.

Systems and methods related to a processor with opportunistic bypass of dispatch buffer and reservation station are disclosed herein. The microarchitecture of the processor can determine when conditions exist for the dispatch buffers, reservation station, or other components of an instruction pipeline, to be bypassed by an instruction. One or more components may be bypassed after at least a portion of the instruction pipeline is flushed or ignored. Instructions may bypass one or more components if the source operands of the instruction are ready, there is sufficient space at the destination bypass path, and if the bypassed component is empty. Systems and methods as disclosed herein may improve the efficiency of processing instructions and reduce penalties for branch interpretations and other errors.

Providing physical register (PR) swap memory renaming in a processor-based device is disclosed herein. In some exemplary aspects, a processor provides an instruction processing circuit that includes a scheduling stage circuit and an execution stage circuit. The scheduling stage circuitry includes a reservation station circuitry, and the execution stage circuitry includes a PR swap table storing a plurality of PR swap table entries. The scheduling stage circuitry issues a first instruction associated with a store dependency ID. The execution stage circuitry: identifies a PR swap table entry corresponding to a storage dependency ID among the plurality of PR swap table entries in response to issuing of the first instruction; retrieving a loading dependency ID of the PR swap table entry; and broadcast the load dependency ID to the reserved station circuit to wake up a second instruction associated with the load dependency ID.