15 results about "Reservation station" patented technology

Disclosed in the present application are an accelerator instruction processing method and apparatus, and an electronic device. The method is executed by a processor, and comprises: dispatching an accelerator instruction to a shared reservation station of an execution unit of an accelerator and an execution unit of a processor; determining whether there is a free entry in an accelerator instruction data transmission unit in the processor, and in response to there being a free entry in the accelerator instruction data transmission unit, issuing the accelerator instruction from the shared reservation station to the execution unit; monitoring a write-back port of the execution unit, and determining configuration information of the execution unit; on the basis of the configuration information of the execution unit, writing the accelerator instruction back to a re-order buffer area; and controlling the accelerator instruction data transmission unit to sequentially send instruction information of the accelerator instruction to the execution unit of the accelerator.

The invention discloses a speculative fusion design structure supporting discontinuous microcodes. The speculative fusion design structure is composed of a fusion predictor, a microcode queue, a reservation station and a fusion historical queue. The invention further discloses a speculation fusion optimization method supporting the discontinuous microcodes, which comprises the following steps of: S1, accessing the fusion predictor, acquiring fusion information of the corresponding microcodes, and storing the hit corresponding microcodes and the fusion information carried by the microcodes into a microcode queue; s2, after the microcodes and fusion information carried by the microcodes are stored in a microcode queue, internal correlation check and deadlock check of the microcodes are carried out; and S3, checking the correctness of microcode fusion in a submission stage after microcode fusion. According to the method, effective detection can be carried out during non-continuous microcode fusion, the problem of execution conflicts generated after non-continuous microcode fusion is avoided, the confidence degree of the prediction path is dynamically monitored, and the prefetching range and the prefetching accuracy are both considered.

An apparatus and method for efficient matrix processing in a clustered processor core. For example, one embodiment of a processor comprises: a front end to fetch and decode a plurality of instruction strands to generate a corresponding plurality of microoperations, including matrix processing microoperations; a reservation station to schedule the microoperations for execution in accordance with a first scheduling mode; out-of-order execution circuitry to execute the microoperations; and a detector to determine a density of the matrix processing microoperations within an interval and to signal to the reservation station to implement a second scheduling mode when the density of matrix processing microoperations reaches or exceeds a first threshold.

The invention provides a memory access instruction re-execution method and device, equipment and a storage medium, and the method applied to a processor comprises the steps: determining a re-execution event of a memory access instruction, and determining a target feedback port from at least one preset feedback port based on the re-execution event or a target pipeline level where the memory access instruction is located; and sending a retransmission request to the reservation station through the target feedback port, so that the reservation station retransmits the memory access instruction based on the retransmission request. According to the technical scheme, the memory access instruction re-execution efficiency can be improved, and the execution efficiency of the processor is further improved.

A reservation station that includes a storage circuit with multiple full and partial entries is disclosed. A given store-data entry of the multiple partial entries may store less data than a given full entry of the multiple full entries. A control circuit may receive a load / store operation and, in response to a determination that the load / store operation includes only a single source, store the load / store operation in a particular partial entry of the multiple partial entries.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for bypassing in out of order processing. One of the methods includes storing, in a reservation station, a bypass value that indicates a stage of an execution pipeline used to execute a producer instruction; selecting, using the bypass value, output data from the stage of the execution pipeline from data generated by at least two execution pipelines used to execute the producer instruction; and executing a consumer instruction stored in the reservation station associated with the bypass value using the selected output.

Enabling high-performance Scalable Matrix Extension (SME) instruction issue in processor devices is disclosed herein. In some aspects, a processor device comprises a reservation station circuit configured to perform, during a first phase, a reduced-precision vector accumulator (ZA) tracking operation on micro-ops for which corresponding vector (Z) registers and corresponding predicate (P) registers are ready. Based on the reduced-precision ZA tracking operation, the reservation station circuit selects a first micro-op and a second micro-op having no Read-After-Write (RAW) hazard with respect to the ZA registers. During a subsequent second phase, the reservation station circuit performs a full-precision ZA tracking operation on the first micro-op and the second micro-op, and selects one as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the ZA registers. The reservation station circuit then issues the selected micro-op for execution.

Enabling high-performance Scalable Matrix Extension (SME) instruction issue in processor devices is disclosed herein. In some aspects, a processor device comprises a reservation station circuit configured to perform, during a first phase, a reduced-precision vector accumulator (ZA) tracking operation on micro-ops for which corresponding vector (Z) registers and corresponding predicate (P) registers are ready. Based on the reduced-precision ZA tracking operation, the reservation station circuit selects a first micro-op and a second micro-op having no Read-After-Write (RAW) hazard with respect to the ZA registers. During a subsequent second phase, the reservation station circuit performs a full-precision ZA tracking operation on the first micro-op and the second micro-op, and selects one as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the ZA registers. The reservation station circuit then issues the selected micro-op for execution.

Systems and methods related to a processor with opportunistic bypass of dispatch buffer and reservation station are disclosed herein. The microarchitecture of the processor can determine when conditions exist for the dispatch buffers, reservation station, or other components of an instruction pipeline, to be bypassed by an instruction. One or more components may be bypassed after at least a portion of the instruction pipeline is flushed or ignored. Instructions may bypass one or more components if the source operands of the instruction are ready, there is sufficient space at the destination bypass path, and if the bypassed component is empty. Systems and methods as disclosed herein may improve the efficiency of processing instructions and reduce penalties for branch interpretations and other errors.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for issue pipe sharing. One of the methods includes concurrently issuing a plurality of instructions to different execution units using selection logic to select which source data elements to obtain from the N read ports into the PRF by a process that includes a physical register file (PRF), a plurality of execution units, and a reservation station (RSV) that includes a plurality of issue pipes.

Controlling instruction issue rate using credit-based mechanisms in processor devices is disclosed herein. In some aspects, a processor device comprises a credit logic circuit that is communicatively coupled to a reservation station (RS) circuit, and that comprises a credit counter. The credit logic circuit receives an instruction issue indication for an instruction from the RS circuit during a time interval. The credit logic circuit decrements a value of a credit counter. The credit logic circuit also determines whether the value of the credit counter equals or is less than a blocking threshold, and, if so, asserts a block signal to the RS circuit. The RS circuit is configured to receive the block signal, and, responsive to receiving the block signal, block further instruction issuance during the time interval.

Controlling instruction issue rate using credit-based mechanisms in processor devices is disclosed herein. In some aspects, a processor device comprises a credit logic circuit that is communicatively coupled to a reservation station (RS) circuit, and that comprises a credit counter. The credit logic circuit receives an instruction issue indication for an instruction from the RS circuit during a time interval. The credit logic circuit decrements a value of a credit counter. The credit logic circuit also determines whether the value of the credit counter equals or is less than a blocking threshold, and, if so, asserts a block signal to the RS circuit. The RS circuit is configured to receive the block signal, and, responsive to receiving the block signal, block further instruction issuance during the time interval.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for sharing tag comparators. One of the methods includes obtaining, by a shared comparator, a broadcast destination tag, wherein the shared comparator operates for an instruction stored in the RSV; selecting, by a selection logic module, a source tag from among tags that include a tag of a first source and a tag of a second source, wherein the first source and the second source are used by the instruction; and comparing, by the shared comparator, the selected tag and the broadcast destination tag.

Providing physical register (PR) swap memory renaming in a processor-based device is disclosed herein. In some exemplary aspects, a processor provides an instruction processing circuit that includes a scheduling stage circuit and an execution stage circuit. The scheduling stage circuitry includes a reservation station circuitry, and the execution stage circuitry includes a PR swap table storing a plurality of PR swap table entries. The scheduling stage circuitry issues a first instruction associated with a store dependency ID. The execution stage circuitry: identifies a PR swap table entry corresponding to a storage dependency ID among the plurality of PR swap table entries in response to issuing of the first instruction; retrieving a loading dependency ID of the PR swap table entry; and broadcast the load dependency ID to the reserved station circuit to wake up a second instruction associated with the load dependency ID.

This invention discloses a fine-grained, lock-step-tolerant, superscalar out-of-order processor design method and system. The method includes: reading the current instruction address and performing branch prediction to obtain the fetch address of the next instruction; decoding the instruction fetch to extract the opcode, source operand register number, and destination operand register number; renaming the instruction decoding result; processing the renamed instruction decoding result through a reservation station module; performing arithmetic and logical operations on the arbitrated instruction decoding result; comparing and checking the results of executed instructions and writing them into the system; reordering and buffering the written results of executed instructions before committing them to construct the superscalar out-of-order processor. This invention improves the fault detection and recovery capabilities of superscalar out-of-order processors. As a fine-grained, lock-step-tolerant, superscalar out-of-order processor design method and system, this invention can be applied to the field of fault-tolerant processor design technology.