Task-level out-of-order multi-issue scheduler and scheduling method thereof

A multi-launcher and scheduler technology, applied in multi-program devices, resource allocation, etc., can solve the problems of low efficiency of correlation acquisition, instruction-level scheduler can not meet the design requirements of task-level coarse-grained scheduler, etc., and achieve parallel extraction Execution efficiency, high computing resource utilization efficiency, and the effect of efficient dynamic scheduling

Active Publication Date: 2015-09-23
HEFEI UNIV OF TECH
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AI Technical Summary

Problems solved by technology

The basic idea of ​​the dynamic scheduler is the application of the Tomasulo algorithm, which is very mature in the traditional instruction-level scheduler, but the design of the traditional instruction-level scheduler can no longer meet the design requirements of the task-level coarse-grained scheduler

Method used

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  • Task-level out-of-order multi-issue scheduler and scheduling method thereof
  • Task-level out-of-order multi-issue scheduler and scheduling method thereof
  • Task-level out-of-order multi-issue scheduler and scheduling method thereof

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Embodiment Construction

[0046] In this example, if figure 1 As shown, a task-level out-of-order multi-issue scheduler is arranged in a processor and is used to schedule M task instructions. The processor includes: an instruction fetch unit, a register state table and a processing unit array; the scheduler includes: Reserved station, selective wake-up unit and computing resource management unit; reserved station includes write address management unit, storage space and reserved station state table; selected wake-up unit includes age table, ready query unit and ready counter; computing resource management unit includes Calculation resource table, allocation unit and recycling unit;

[0047] Usually, a processor that supports dynamic scheduling includes a controller and a processing unit array. The controller includes an instruction fetching and decoding unit, a register renaming unit, a scheduler, a submission unit, physical registers, a register status table, etc.; The decoding unit obtains task inst...

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Abstract

The invention discloses a task-level out-of-order multi-issue scheduler and a scheduling method thereof. The scheduler is characterized by comprising a reservation station, an option awakening unit and a calculation resource management unit, wherein the reservation station comprises a write address management unit, a storage space and a reservation station state table; the option awakening unit comprises a chronological table, a ready inquiry unit and a ready counter; and the calculation resource management unit comprises a calculation resource table, an allocation unit and a recovery unit. The throughput and resource utilization efficiency of the scheduler can be increased, so that the task instruction issue efficiency is increased, and the system performance is improved.

Description

technical field [0001] The invention relates to a task-level out-of-order multi-issue scheduler and a scheduling method thereof, belonging to the field of out-of-order multi-issue processors. Background technique [0002] With the development of integrated circuit technology, the requirements for processor performance are getting higher and higher. The improvement of processor performance, on the one hand, depends on the development of integrated circuit technology; on the other hand, it also depends on the progress of processor design technology. Theme of. For a large part of the past, many efforts have been made to mine instruction-level parallelism. Technologies such as super-pipeline structure, superscalar structure, instruction out-of-order multiple issue, and very long instruction word VLIW have been applied in many processors. With the development of multi-core processors, the current multi-core technology has become the main technical method to improve processor pe...

Claims

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Application Information

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IPC IPC(8): G06F9/50
Inventor 张多利张扬宋宇鲲杜高明
Owner HEFEI UNIV OF TECH
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