85 results about "Processor design" patented technology

The invention discloses an instruction scheduling method, device and system, a product and a medium, and relates to the technical field of processor design. The invention provides an instruction scheduling method aiming at the problem that the dynamic change in the instruction transmitting time cannot be accurately scheduled by the existing out-of-order scheduling strategy. The historical delay information of each instruction is stored through the delay cache, and when the instruction execution delay corresponding to the instruction is dynamic delay, the dynamic delay is predicted through the historical delay information stored in the delay cache, so that instruction scheduling is performed. According to the method, the dynamic delay of which the delay time cannot be predetermined is included in the consideration range of instruction scheduling based on the dynamic delay prediction mechanism. On the basis of the method, for dynamic change scenes in instruction transmission time such as memory access delay and cache miss, the optimal instruction transmission opportunity can be accurately predicted, so that the effect of instruction scheduling on performance improvement of a processor is further improved.

The invention provides a multi-core GPU cache division method, architecture and data access method, relates to the technical field of graphics processor design, and aims to realize cross-core access performance system-level optimization and improve the performance of processing large-scale image data by introducing a cache allocation mechanism based on topology awareness. The method comprises the steps that a multi-core-grain GPU topological structure comprising a target computing core grain and at least one associated computing core grain is obtained, a to-be-divided far-end data cache of the target computing core grain is used for caching image data from a far-end video memory, and the to-be-divided far-end data cache is connected with the associated computing core grain through an inter-core-grain interconnection network; if the number of the calculation core particles contained in the multi-core-particle GPU does not exceed a first preset threshold value, the inter-core-particle hop count between each associated calculation core particle and a target calculation core particle is determined based on the topological structure, and then the corresponding capacity of the associated calculation core particles in the to-be-divided cache of the target calculation core particle is determined; and dividing the to-be-divided cache according to the capacity corresponding to each associated calculation core particle.

The invention belongs to the field of many-core processor design, and particularly relates to a many-core processor system based on a data flow framework and a task scheduling method.The system comprises a system control node, computing nodes and storage nodes which are connected through an on-chip internet, and each storage node and at least one computing node form a computing cluster; the system control node sends an instruction and data to the storage node through the on-chip internet, and the storage node distributes the data to the computing nodes in the computing cluster; an initialization unit of the computing node monitors a data buffer area of the on-chip internet through a state register, data are moved to a buffer unit, and initialization of a computing core is completed; the scheduling unit is responsible for scheduling a task queue, and transferring data required by a next task to the cache unit in advance through the DMA unit to realize parallel calculation and data transferring; the computing unit executes the computing task, and the data directly flows among different computing nodes, so that the memory access requirement is reduced, and the computing resource utilization rate is improved.

The invention discloses an automatic verification excitation generation method based on a backtracking thinking tree, and the method comprises the steps: constructing a backtracking thinking tree frame based on a self-feedback mechanism based on a thinking tree for a to-be-verified processor function; under the backtracking thinking tree framework, decoupling a to-be-verified function from top to bottom through a large language model, and recursively decomposing the whole to-be-verified function into function points capable of being independently verified layer by layer through a tree structure; according to each function point, determining a normal function and a boundary of each function point, and for each function point, generating verification excitation layer by layer in a tree structure; after the verification excitation is generated, self-verification and self-backtracking are carried out layer by layer through a tree structure, and finally, the generated verification excitation is executed on the processor design to verify the correctness of the processor function. According to the method and the system, the function verification efficiency and the verification coverage rate of the processor are remarkably improved.

The disclosed system includes a memory and a processor designed to execute operations for generating non-fungible tokens for training data utilized in training machine learning models. The memory is configured to store both data records of the training data and their corresponding metadata. The processor performs operations to identify a set of fields within each data record and to annotate each field. Such annotation process involves creating field metadata, including information that identifies each field in the data record and assigning a label to each field. Additionally, for each field, the processor is further configured to generate a non-fungible token and create a non-fungible token attribute record, incorporating details from both the data record metadata and the field metadata. Also, the processor is configured to store the non-fungible token attribute record in the memory, thereby facilitating comprehensive and secure authentication of data records.

The invention discloses a hybrid branch predictor capable of dynamically selecting different prediction methods and application, and relates to the technical field of high-performance processor design, the hybrid branch predictor mainly comprises a branch direction predictor and a branch target predictor; the branch direction predictor is used for predicting whether a branch instruction jumps or not; and the branch target predictor is used for predicting a specific jump target address when the branch direction is predicted to be jump. By implementing the hybrid branch predictor capable of dynamically selecting different prediction methods and the application provided by the invention, the branch prediction accuracy can be improved, and the hardware resource overhead can be reduced.

The present invention relates to a processor designed to optimize memory bandwidth utilization for tensor transpositions in machine learning. An example processor includes an input tensor shift buffer, a staging buffer, and an output tensor shift buffer. The input tensor shift buffer reads an input tensor from input memory and performs multiple cycles of input tensor shifting. The shifted tensor data is then written into the staging buffer. The output tensor shift buffer reads the shifted tensor data from the staging buffer and performs multiple cycles of output tensor shifting. Finally, the result is written to the output memory. This configuration facilitates efficient handling and transformation of tensor data, optimizing the computational processes required in machine learning tasks.

The invention discloses a PPA prediction method for designing a few-sample processor based on RAG. According to the technical scheme, an RAG-based few-sample processor design PPA prediction system composed of a processor design normal form, an EDA tool module, an RAG module, a to-be-tested processor design input module and a PPA prediction module is constructed. The RAG module samples a design space of a processor design normal form, obtains a processor design sample, encodes feature vectors of the sample, obtains a PPA value of the design sample by using the EDA tool module, and constructs a knowledge base required by PPA prediction; and the RAG module detects knowledge matched with the processor design code of the PPA value to be predicted in the knowledge base, and generates a cue word based on the matched knowledge. And the PPA prediction module interacts with the cue word to obtain a PPA prediction value designed by the PPA value processor to be predicted. Accurate PPA prediction can be carried out based on a small number of samples, and the design period is shortened.

The invention is suitable for the technical field of computer processor design, and provides an instruction processing method and device, terminal equipment and a program product, and the method comprises the steps: obtaining instruction information of a to-be-processed instruction set in a processor; generating an index vector corresponding to the to-be-processed instruction set based on the original effective vector; each index value in the index vector is subjected to one-hot code conversion, a one-hot code matrix corresponding to the instruction set to be processed is generated, and each row of one-hot code vector in the one-hot code matrix corresponds to each path of input instruction; and according to the original effective vector and the one-hot code matrix, sorting operation codes of each path of input instruction to obtain processed operation code information, so that a processor executes corresponding operation based on the processed operation code information. The method can meet the requirement that the high-performance processor completes instruction processing in a single cycle, the processing delay is low, and therefore the instruction execution efficiency of the processor is improved.

The invention discloses a processor circuit, a server, a data access method, an authentication method and a medium, and relates to the technical field of processor design, the processor circuit comprises a substrate, a processor integrated on the substrate, a protection module and an interface module, the protection module and the interface module are packaged in a packaging piece of the processor, and the protection module is arranged between the processor and the interface module. The external access signal passing the security authentication accesses the processor through the interface module, so that the design of a server system security circuit is simplified, the occupied area is small, and the security protection is more comprehensive; the technical problems of large size, low integration level, insufficient security, incomplete protection range and the like of platform firmware protection schemes in related technologies are solved, and the technical effects of effectively reducing the risk that the server is cracked by hardware, reducing the size of the server and the like are achieved.

The application discloses a kind of based on RAG's few-sample processor design PPA prediction method.The technical scheme is: the processor design paradigm, EDA tool module, RAG module, the input module of processor design to be measured and PPA prediction module are formed based on RAG's few-sample processor design PPA prediction system.RAG module carries out sampling to the design space of processor design paradigm, obtains processor design sample, the feature vector coding of sample, utilizes EDA tool module to obtain the PPA value of design sample, constructs the knowledge base required for PPA prediction;RAG module detects the knowledge matched with the processor design code of the PPA value to be predicted in knowledge base, generates prompt word based on the matched knowledge.PPA prediction module and prompt word interaction, obtain the PPA prediction value of the PPA value processor design to be predicted.The application can be based on a few samples to carry out accurate PPA prediction, shortens design cycle.

This invention provides a motor controller and engineering machinery. The motor controller includes: a driver connected to a motor; and an MPU (Multi-Core Processor), the MPU including a multi-core processor. Each core of the multi-core processor communicates with each other via a communication link for data exchange. The multi-core processor is connected to the driver and is used to detect motor operating status information and control the motor based on the operating status information. This invention adopts a single-chip MPU multi-core processor design, which can realize the motor controller function with a single MPU, meeting the requirements of small size and compact design of the controller, reducing equipment cost, and conforming to the ISO 13849 functional safety PLD / CAT2 class architecture.

The present application relates to a kind of reconfigurable baseband processing SoC architecture based on RISC-V extension instruction set and its instruction control method, belong to communication chip and processor design technical field.For the instruction set flexibility insufficient, data handling inefficiency and dynamic reconfiguration and high energy efficiency difficult to consider of existing 5G / 6G baseband processor, the present application proposes a kind of heterogeneous computing architecture, including the RISC-V processor core cluster of supporting RV64IMAFDCV instruction set, extension instruction execution unit, vector coprocessor and reconfigurable hardware acceleration module group.By adding special instructions such as complex matrix multiplication, optimizing data path design, using double buffering mechanism and hierarchical reconfigurable technology, efficient execution of baseband processing is realized.At the same time, dynamic voltage frequency regulation system can adjust power supply parameters in real time according to work load.The scheme significantly improves the performance and energy efficiency of baseband processing, and is suitable for physical layer signal processing of 5G / 6G communication system.

The invention provides a processor core co-verification debugging method, which comprises the following steps of: in a co-simulation running process of a processor core to be tested, capturing an output verification event, performing standardized storage, and generating a trace file and an interface specification file; automatically generating an independent verification framework compatible with the to-be-tested processor core interface according to the interface specification file; and loading the trace file to drive the verification framework to run, and separating from the processor core to be tested to carry out independent debugging and iteration. According to the invention, the efficiency and reliability of large-scale processor design verification are improved, and the resource overhead is reduced.

According to various embodiments, a data processing device is described, comprising: a processor designed to execute a computer program, and persistent memory, wherein the computer program includes instructions that effect an update of a signature of the program execution at predetermined signature update phases of the program execution, wherein at least one of the instructions effects an update of the signature depending on a configuration value stored in the persistent memory of the data processing device, wherein the configuration value specifies one or more operating settings of the data processing device, and wherein the processor is designed, for each of one or more predetermined integrity check phases of the program execution, to perform further processing after the predetermined integrity check phase of the program execution depending on thatwhether the signature matches one or more predetermined reference signatures.

This application relates to the technical field of processor design, and particularly to a matrix-vector processor and a matrix-vector collaborative computing method. The matrix-vector processor includes a main processor core, a matrix coprocessor core and a vector coprocessor core connected thereto, and an L2 cache connected to the main processor core, the matrix coprocessor core and the vector coprocessor core. The matrix-vector collaborative computing method includes the L1 cache obtaining instructions and data from the L2 cache and initially distinguishing the instruction types. For conventional computing instructions, matrix computing instructions and vector computing instructions, the main processor core, the matrix coprocessor core and the vector coprocessor core respectively execute the computations to obtain computation results. The computation results are written back to the L2 cache to update the resource status of the scoreboard module. This application can reduce resource redundancy, improve communication efficiency, break the closed restrictions, and achieve efficient elastic computing by combining hybrid scheduling and modular expansion.

A device may include: a memory and a processor designed to: determine a utilization state of a wireless communication link designed to communicate within a radio frequency channel; determine an operating frequency of a radio frequency interference generating device; and instruct the radio frequency interference (RFI) generating device to adjust the operating frequency based on the utilization state of the wireless communication link.

The embodiment of the invention discloses an instruction processing method and system, electronic equipment and a storage medium, relates to the technical field of computer processor design, and can save write port resources of a register file. The method comprises the following steps of: analyzing a read-write dependency relationship of each instruction in a current instruction group on a flag bit register so as to establish a flag bit data stream dependency chain; according to the read-write dependency relationship and a preset elimination rule, judging whether each instruction indicating to be written into the flag bit register in the current instruction group needs to be written into the flag bit register or not; and if the judgment result shows that the instructions indicating to be written into the flag bit register in the current instruction group do not need to be written into the flag bit register, canceling the operation of writing the instructions indicating not to be written into the flag bit register back to the flag bit register. The method and the device are suitable for eliminating invalid flag bit registers.

According to various embodiments, a data processing device is described which includes a Boolean masked addition processor designed to perform Boolean masked addition and a fault protection circuit designed to generate a checksum for a first part, generate a second checksum part, compare the first checksum part with the second checksum part, and trigger a safety action in response to a mismatch between the first checksum part and the second checksum part.

The present invention discloses an instruction scheduling method, apparatus, system, product and medium, relating to the technical field of processor design. Aiming at the problem that the current out-of-order scheduling strategy cannot accurately schedule the dynamic changes in the instruction issue time, an instruction scheduling method is provided. The historical delay information of each instruction is stored in a delay cache. When the instruction execution delay corresponding to an instruction is a dynamic delay, the dynamic delay is predicted through the historical delay information stored in the delay cache, so as to perform instruction scheduling. Based on the above dynamic delay prediction mechanism, this method incorporates dynamic delays with undetermined delay times into the consideration of instruction scheduling. In scenarios of dynamic changes in instruction issue time such as memory access delay and cache miss based on this method, the optimal issue time of instructions can be accurately predicted, thereby further improving the effect of instruction scheduling on processor performance improvement.

A digital processor simulates a quantum computing system by implementing a QPU model including a set of representation models and a device connectivity representation to simulate a quantum processor design or a physical quantum processor. The digital processor receives an analog waveform and generates a digital waveform representation comprising a set of waveform values that correspond to biases applied to programmable devices in a quantum processor. The digital processor selects a subset of waveform values based on channels in the device connectivity representation. The digital processor implements a representation model to compute a response based on the waveform values and a plurality of physical parameter values, the physical parameters characterizing a programmable device in a quantum processor. The device connectivity representation can be generated from a design implementation, validated against a set of rules, and adjusted to change the device connectivity representation until all of the rules are passed.

The invention provides a synchronous verification method for an asynchronous interrupt event, which comprises the following steps of: establishing a system-level verification platform designed by an instruction-level synchronous general processor based on UVM (Universal Verification Methodology), and loading an excitation binary file to enable the excitation binary file to work normally so as to realize instruction-level synchronous verification; creating an asynchronous interrupt event excitation, wherein the asynchronous interrupt event excitation comprises asynchronous interrupt event triggering time; in the normal working process of the system-level verification platform, an asynchronous interrupt event is injected into a to-be-tested product through the UVM environment framework, and the asynchronous interrupt event is injected into the reference model when the asynchronous interrupt event is detected to occur, so that the reference model synchronously triggers the same asynchronous interrupt event, and the system-level verification platform is verified. And instruction-level synchronous verification when an asynchronous interrupt event occurs is realized. According to the synchronous verification method for the asynchronous interrupt event, the synchronization relation of instruction submission is established between the to-be-tested product and the reference model, and synchronous verification can be carried out for the asynchronous interrupt event.

The present invention relates to a processor designed to optimize memory bandwidth utilization for tensor transpositions in machine learning. It features an instruction decoder that decodes tensor transpose instructions for an input tensor, distinguishing between transposing and stationary axes. An inner transpose engine, equipped with multiple tensor buffer units of varying sizes, transposes the tensor by reading data by rows and writing by columns, efficiently managing memory when the buffer is full. Additionally, an address scheduler determines the target memory addresses in the output tensor memory for the tensor data, improving the handling and transformation of tensors in machine learning environments. This processor significantly enhances the efficiency and speed of tensor operations critical to advanced machine learning applications.

Vehicle control device, which includes: a processor; and a memory (46) wherein the memory (46) stores relationship-defining data to define a relationship between a state of a vehicle and an action variable, which is a variable relating to operations of a transmission installed in the vehicle, the processor is designed to execute: an investigative processing method to determine the condition of the vehicle based on a sensor reading, an operational processing to control the transmission based on a value of the action variable determined by the state of the vehicle as determined in the investigation processing and the relationship-defining data, a reward calculation process to give a larger reward when the vehicle's characteristics meet a reference, instead of failing to meet the reference, based on the vehicle's state determined in the discovery processing, an update processing to update the relationship-defining data with the state of the vehicle determined in the discovery processing, the value of the action variables used in the operation of the transmission, and the reward corresponding to the operation, as inputs into a pre-set update map, a counting process for counting an update counter by the update processor, and a bounding process to limit downwards a range used by the operation processing, in which a value other than a value that maximizes an expected utility with respect to the reward, of values ​​of the action variable that specify the relationship-defining data, when the update counter is relatively large, and The processor is designed to output updated relationship-defining data, thus increasing the expected benefit when the gearbox is operated according to the relationship-defining data, based on an update map.

The invention relates to the technical field of processor design, discloses a multi-thread processor pipeline architecture system, a scheduling method and equipment, and designs an instruction prefetching scheduling algorithm based on mixed priorities, and the algorithm realizes load balancing of thread instruction queues through a static level decision mechanism and a dynamic level decision mechanism. The static level preferentially processes an empty queue thread to avoid starvation, and the dynamic level dynamically adjusts instruction fetching priority according to each queue depth, thread validity and a branch risk state to ensure that an instruction stream is continuously and stably supplied to a subsequent stage; a coupled polling emission scheduling algorithm is provided, so that high complexity of full-permutation search is avoided, and structural conflicts and data conflicts are effectively reduced; a special hardware architecture is designed around the algorithm, a multi-program counter and an instruction queue are integrated at the front end, a double-transmitting channel, a multifunctional unit and a thread private register file are configured at the rear end, and the performance of the single-core CPU is improved by optimizing the hardware architecture.

The invention discloses a fuzzy testing and model detection combined hardware verification method and system, and belongs to the technical field of hardware testing. The method comprises the steps that multiple rounds of fuzzy testing guided by the coverage rate are executed on a processor based on an initial seed set, snapshots generated in the fuzzy testing process are recorded, value scoring is conducted on the snapshots to construct a snapshot pool, and the processor is designed and generated based on a processor to be verified; selecting an optimal snapshot from the snapshot pool, and initializing a processor design based on the optimal snapshot; under the condition that points which are not covered exist in the processor design, a new test seed is generated through bounding model detection; performing fuzzy testing on the processor design based on the new test seed to obtain a verification result of the optimal snapshot; and synthesizing verification results of a plurality of optimal snapshots in the optimal snapshot set to obtain a hardware verification result of the to-be-verified processor design. According to the method, the efficiency and the applicability of the BMC can be remarkably improved on the premise of not sacrificing the verification precision.

The present invention relates to a control device (1) for semiconductor switches (4a, 5a, 4b, 5b, 4c, 5c) of an inverter output stage (2), the control device having a processor (12) and having drive circuits (6a, 7a, 6b, 7b, 6c, 7c) respectively provided for each semiconductor switch (4a, 5a, 4b, 5b, 4c, 5c) of the inverter output stage (2), wherein the processor (12) is designed to communicate via a communication interface (1 4.15) The phase current parameters during the switching process of one of the semiconductor switches (4a, 5a, 4b, 5b, 4c, 5c) in the inverter output stage (2) are transmitted to the corresponding drive circuits (6a, 7a, 6b, 7b, 6c, 7c) of the semiconductor switch (4a, 5a, 4b, 5b, 4c, 5c). c) has a computing unit (23) designed to calculate, based on parameters transmitted by the processor (12), the current sinusoidal phase current curves of the phase currents for the switching process of the semiconductor switches (4a, 5a, 4b, 5b, 4c, 5c), and wherein the driving circuits (6a, 7a, 6b, 7b, 6c, 7c) of the semiconductor switches (4a, 5a, 4b, 5b, 4c, 5c) have current curve storage devices (25) designed to calculate, based on parameters transmitted by the processor (12), the current curves of the phase currents for the switching process of the semiconductor switches (4a, 5a, 4b, 5b, 4c, 5c ... The calculation unit (23) of the driving circuit (6a, 7a, 6b, 7b, 6c, 7c) calculates the sinusoidal phase current curve and / or selects the current curve stored therein according to the voltage and / or according to the temperature, and provides it to the driving circuit (6a, 7a, 6b, 7b, 6c, 7c) of the semiconductor switch (4a, 5a, 4b, 5b, 4c, 5c) for performing the switching process in the semiconductor switch (4a, 5a, 4b, 5b, 4c, 5c).

The invention discloses a high-performance real-time range migration correction processor FPGA (Field Programmable Gate Array) design system and method, and solves the problem that in the prior art, when a range migration correction engineering implementation scheme based on a CPU (Central Processing Unit), a GPU (Graphic Processing Unit) and a DSP (Digital Signal Processor) is used for processing high-resolution and large-scale data; the problems of performance bottleneck, data transmission limitation, high power consumption, insufficient computing power and flexibility limitation generally exist; the system comprises a control state machine used for reading preset parameters in a data packet header and inputting the preset parameters to a Keystone parameter configuration module; the Keystone parameter configuration module is used for calculating four groups of effective values according to preset parameters and storing the four groups of effective values; the correction module is used for performing calculation according to the input ISAR echo data and the four groups of effective values to obtain echo data after migration correction; according to the system, high-parallelization acceleration of the migration correction module is realized, and the processing speed and efficiency are remarkably improved.

The invention relates to a multi-thread parallel redundancy fault-tolerant method based on a compilation layer. The invention relates to the technical field of embedded processor design. The method comprises the following steps: determining thread division and an SoR region core; packaging an SoR region related fault-tolerant function library, packaging a core fault-tolerant function into a header file, and ensuring that a library file contains a tool function strongly associated with the SoR region; matching the compiler with the tool chain; marking and automatically identifying the source program; automatically identifying and supplementing the ROSE compiler; compiling the SoR region and generating a dual-thread code; performing double-thread parallel execution and check point interaction; and redundant fault-tolerant processing and flow continuation are carried out. The method does not depend on a specific hardware platform, and the problem of poor portability of a traditional hardware redundancy technology or a fault-tolerant technology depending on a specific hardware architecture is effectively avoided.

The invention relates to a method for designing a processor, which comprises the following steps of: acquiring performance data after running by utilizing an analog processor, and enabling initial hardware simulated by the analog processor to have a design improvement multiple relative to reference hardware, when the performance improvement of the performance data relative to the reference performance data of the reference hardware does not reach the design improvement multiple, adjusting initial software of the analog processor, and updating the analog processor according to the adjusted initial software; and repeating the steps until the performance improvement of the performance data relative to the reference performance data reaches the design improvement multiple. According to the method for designing the processor, resource waste caused by the fact that a hardware entity processor is adopted for design can be avoided, specification parameters or implementation strategies of hardware can be adjusted more conveniently, and the design efficiency of the processor is improved.