260 results about "Transient storage" patented technology

The invention provides a data writing and backup method for cloud host block storage and corresponding equipment. According to the scheme, during data writing, a newly-created temporary storage volume and a corresponding temporary IO bitmap are utilized, and when data overwriting occurs to an IO data block for the first time, the data overwriting time is shortened; and if not, copying the original data in the IO data block to a second IO data block on the temporary storage volume, and then writing new data to be written into the first IO data block on the source disk volume. Therefore, during backup, new data can be written into the IO data block without waiting for backup completion, and original data required by backup can be found in the temporary storage volume even if CBW operation is not triggered, so that backup can be correctly completed under the condition of not influencing IO performance, the influence of a backup task on the IO performance of a cloud host service in a push mode is avoided, and the backup efficiency of the cloud host service is improved. And meanwhile, the support for other storage formats in a pull mode is made up, and the problem that the service IO performance jitters violently is greatly relieved.

A method for obtaining boot logs is provided. The method includes: determining an operating state of a target device, where the operating state includes: a normal operation state and an abnormal operation state; and in response to the operating state being the normal operation state, obtaining boot logs from a first target memory device in a BMC system of the target device, where the first target memory device is a transitory memory device, and the boot log is all logs of the target device in a boot process; or in response to the operating state being the abnormal operation state, obtaining the boot logs from a second target memory device in the target device, where the second target memory device is a memory device in the target device. An apparatus for obtaining boot logs and a method for transferring boot logs are further provided.

The invention provides a firmware management method and system, a storage medium and a program product. The method comprises the following steps: marking a firmware exclusive analysis class in advance through a (at) Firmware Type custom annotation, and defining a multi-product line verification rule by adopting a configuration file in advance; receiving a firmware uploading request, creating a corresponding asynchronous processing task, and temporarily storing a corresponding firmware file to the temporary storage path; obtaining a matched firmware analysis rule in the central rule base, and instantiating a corresponding (at) Firmware Type firmware exclusive analysis class to obtain analyzed firmware data; sequentially executing version preprocessing, dynamic rule matching and version verification on the analyzed firmware data according to a multi-product-line version verification rule; the firmware passing the version verification is intelligently stored; and cleaning the temporary file, and executing physical deletion on the firmware file with the reference return to zero stored in the formal storage path. By means of the technical scheme, the problems that an existing analysis rule is rigid, rule modification is tedious, and the storage utilization rate is low are solved.

A storage device includes one or more ports that form an electrical connection with an external device, one or more physical functions including physical resources, and exposed through the one or more ports to communicate with the external device, a storage controller that controls an operation of the storage device, and communicates with the external device through the one or more ports and the one or more physical functions, nonvolatile memories controlled by the storage controller, and a first buffer memory controlled by the storage controller. When the storage device is accessed by the external device, the first buffer memory is used by the one or more ports and the one or more physical functions to temporarily store data for the external device.

Methods, systems, and devices for data management are described. A data management system (DMS) may provide backup and recovery services for customer computing systems or databases. The DMS may implement an active / passive partition scheme to enable reception of log files in a push manner and avoid frequent building and teardown of the stack to back up the database. The DMS may implement two storage partitions which alternate between an active and passive state. Received log files may be stored temporarily in a first storage partition in the active state. Once the first storage partition is transitioned to the passive state, the DMS may capture a snapshot of the storage partition and may store the snapshot. When the first storage partition is transitioned to the passive state, the second storage partition may be transitioned to the active state so that the DMS may continue to receive log files.

An improved flushing technique controls a draining speed of data from a temporary storage tier to a backend storage tier of a node so that draining logic does not overwhelm an input / output (I / O) workload that is serviced by the storage tiers. Illustratively, the temporary storage tier is a persistent write buffer embodied as an operations log (oplog) and the backend storage tier is persistent physical disk storage embodied as an extent store. The technique improves an oplog flushing algorithm by enabling control of the oplog draining speed (rate) to provide consistent performance when the I / O workload (e.g., a primary ingest I / O stream) is serviced by the extent store and / or oplog during one or more states (e.g., static inertia state, idle state and rebuild state) of the oplog.

Disclosed herein are methods, systems, and computer-readable media for interacting with a language model using custom instructions. In one embodiment a method includes receiving, through an interface, custom instructions, the custom instructions comprising at least one of personal information or a response type preference, storing the custom instructions temporarily within a session specific cache, in response to a trigger event, adding the custom instructions to a system message associated with the language model, the system message being a prompt modifier to the language model, in response to receiving a prompt, retrieving the custom instructions from the session specific cache, determining whether the custom instructions are relevant to the prompt, and in response to determining the custom instructions are relevant to the prompt, generating a response to the prompt based on the custom instructions.

This invention relates to a service fault location system and method based on a BMC (Browser Control Center). The system includes: establishing a communication link between the BMC and the server under test (DUT) using a customized IPMI protocol; configuring test parameters and controlling the DUT to power on and start a restart test program; the BMC collecting current hardware-level data; the BMC performing temporary storage and determining whether an anomaly occurred during the current test round; when an anomaly occurs during the current test round, the BMC receives the current customized IPMI message, obtains the anomaly level information, and controls the CPLD (Content Management Logic Controller) to perform a hard restart or not perform a hard restart based on the anomaly level information, and persistently stores the on-site data. No additional test equipment or server hardware / software modifications are required, resulting in lower testing costs and broad applicability; in the event of an abnormal downtime, the BMC can directly operate the CPLD to perform a hard restart, greatly improving testing efficiency and continuity.

The invention provides a system for secure encryption of CPU boot firmware and a working method thereof. The system comprises a CPU unit, an MCU unit, a FLASH unit and an electronic switch unit. By introducing an MCU unit, conventional CPU boot firmware is firstly subjected to data encryption processing and then stored in a first FLASH chip to complete initial configuration, in the system starting process, the MCU firstly reads, decrypts and restores the securely encrypted boot firmware in the first FLASH chip into conventional boot firmware, and writes the conventional boot firmware into a second FLASH chip, so that the boot firmware in the second FLASH chip is subjected to data encryption processing; and then the CPU loads a conventional boot firmware starting system from the second FLASH chip, and after the CPU is started, the MCU erases the boot firmware in the second FLASH chip. Only the first FLASH chip stores the securely encrypted boot firmware, and the second FLASH chip only temporarily stores the boot firmware in the starting stage, so that the risk of physical leakage and cracking of the boot firmware is effectively prevented.

A data storage apparatus may include a storage device; a buffer memory device configured to temporarily store write data and a mapping table; and a memory controller configured to control the storage device to program the write data. The memory controller is configured to when externally receiving write commands including a logical addresses, store the logical addresses by mapping the logical addresses to physical addresses sequentially stored in the mapping table in a sequence in which the write commands are received, and when a program operation corresponding to a first write command fails, invalidate first mapping information corresponding to the first write command and update the first mapping information by allocating a new physical address to a logical addresses including the first write command in response to a reprogram command generated with respect to the first write command.

This application provides a method and apparatus for managing cached files, enabling flexible storage of cached files and improving system performance. The method includes: acquiring characteristic information of the cached file, the characteristic information including at least one of read / write information, size information, or active time information of the cached file; determining the file type of the cached file based on the characteristic information, the file type including at least two of a deletable type, a temporary storage type, or a long-term storage type; and managing the cached file according to the file type.

The invention provides a video storage method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a video collected by a network camera in a monitoring storage system, and storing the video in a temporary storage space in the monitoring storage system under the condition that a storage resource of the monitoring storage system is abnormal; storing the video of the temporary storage space to a target storage space in the storage resources under the condition that the storage resources are completely recovered to be normal; the temporary storage space is determined based on the to-be-covered basic storage block in the storage resource and / or the basic storage block in the storage hard disk in the first state, and the to-be-covered basic storage block is determined based on the configuration information of the network camera and the data specification of the storage resource, so that the problem that the video is easy to lose under the abnormal condition of the storage resource is solved; on the premise that the system cost is not increased and normal storage and coverage strategies of a storage system are not influenced, videos under the condition that rear-end storage resources are abnormal can be completely stored, and the integrity of monitoring data is ensured.

The disclosure configures a multi-port memory sub-system controller to store data in one or more host memory buffers. The disclosure associates, with a first port of a memory sub-system, a first host memory buffer (HMB) of a first temporary storage device that has been allocated to the memory sub-system by a first host system of a plurality of host systems and associates, with a second port of the memory sub-system, a second HMB of a second temporary storage device that has been allocated to the memory sub-system by a second host system of the plurality of host systems. The disclosure performs one or more memory operations on user data using the first HMB and the second HMB and a set of memory components.

The invention provides a Nor flash chip erasure frequency recording method, device and equipment and a storage medium, and is applied to the technical field of semiconductor integrated circuits. When an erasure instruction is received, current erasure frequency information of a target minimum erasure unit is read to a temporary storage unit to be temporarily stored; then, executing erasing operation on the target minimum erasing unit, clearing internal data of the target minimum erasing unit and counting old erasing frequency information in the storage area; generating updated erasure frequency information according to the temporarily stored current erasure frequency information; and finally, writing the updated erasure frequency information into a counting storage area of the target minimum erasure unit which is erased. According to the internal recording mode, the integrity and the accuracy of the data can be ensured even under the condition of power failure, so that the reliability and the accuracy of recording the erasing times of the Nor flash chip are remarkably improved, and the service life of the Nor flash chip is effectively prolonged.

This invention relates to the field of blockchain technology and discloses a Merkle tree hardware acceleration system for blockchain data verification. The system includes a control module for coordinating and controlling various modules; an address generator for generating addresses of sibling and parent nodes in the Merkle tree based on the indices of the input leaf nodes; a storage unit for storing the leaf, internal, and root node data of the Merkle tree; a computation module for performing data concatenation, hashing, and comparison on the Merkle tree nodes based on the addresses provided by the address generator, and generating intermediate and verification results; and a buffer for temporarily storing node data read from the storage unit and intermediate results output by the computation module. This invention designs a hardware acceleration architecture tailored to the structural characteristics of Merkle trees, improving the computational efficiency of blockchain data verification, achieving low-power operation, and is suitable for the performance requirements of various blockchain application scenarios.

A direct memory access (DMA) device includes a controller, a read request issuing circuit, a read buffer temporarily storing read data and an arrival time of the read data, and a read buffer managing circuit that calculates an average bus latency and an average buffer residence time. The read request issuing circuit adjusts the issuing capability based on the average bus latency and the average buffer residence time. The DMA device operates by issuing a read request based on an issuing capability, storing an issuing time of the read request, receiving read data corresponding to the read request, temporarily storing the read data and an arrival time of the read data in a read buffer, calculating an average bus latency based on the issuing time of the read request, calculating an average buffer residence time, adjusting the issuing capability, and issuing the read request based on the adjusted issuing capability.

A database system operates by: receiving a set of records for storage; applying a replication factor dictated by the required fault tolerance level to generate a set of replicas of the set of records; temporarily storing the set of replicas in a temporary ingress storage system during a first temporal period in accordance with the required fault tolerance level; generating a plurality of redundancy-coded segments that encodes the set of record utilizing a redundancy storage coding scheme dictated by the required fault tolerance level; and migrating the set of records from the temporary ingress storage system to a long-term storage system by storing the set of segments in the long-term storage system and by removing the set of replicas from the temporary ingress storage system.

An in-memory bitwise operation circuit and method thereof are provided. The circuit includes a memory array, storing page data each having strings; a page buffer, storing the strings and selecting a portion of the strings as operands; a pop-count counter, receiving the operands and an operator flag, counting the number of bit 1 at corresponding bit positions of the operands, and generating a bitwise operation result corresponding to the operator; a bitwise operation processing unit, receiving and temporally storing the bitwise operation result, and outputting a final bitwise operation result when receiving a final result flag. In case that the operator is a last operator, the bitwise operation result is output as the final bitwise operation result. The circuit and method are suitable for 3D NAND flash memory that has high capacity and high performance.

The invention discloses a Falcon signature loop structure parallel acceleration method based on a GPU (Graphics Processing Unit) shared memory. The method comprises the following steps: S1, distributing the shared memory and sharing data in a thread block; s2, performing parallel circulation; s3, performing thread synchronization; and S4, result combination and output. And S5, a Falcon signature result is obtained. According to the method, a large temporary storage space originally distributed on a function stack is optimized into GPU shared memory distribution, and a serial loop structure related to large-scale polynomial operation is transformed into a parallel execution mode of a fixed thread count (such as 128 threads), so that the execution efficiency of Falcon signature operation is greatly improved on the premise of ensuring the calculation correctness, and the execution efficiency of the Falcon signature operation is improved. The memory occupation is reduced, and the expandability and practicability of the algorithm in a high-dimension and large-scale application scene are enhanced.

This application provides a trigger circuit, chip, and electronic device. The circuit includes: a temporary storage module and an inverting module; the input terminal of the inverting module is electrically connected to the output terminal of the temporary storage module, and the output terminal of the inverting module is electrically connected to the input terminal of the temporary storage module; the inverting module is used to invert the signal output from the output terminal of the temporary storage module to obtain a first target signal, and transmit the first target signal to the input terminal of the temporary storage module; the control terminal of the temporary storage module is used to receive a trigger signal; the temporary storage module is used to update its latched control signal according to the first target signal received at the input terminal when the trigger signal received at the control terminal is valid, and output a control signal through the output terminal, or, when the trigger signal received at the control terminal is invalid, output the latched control signal through the output terminal. This is used to reduce the trigger switching operation time of the temporary storage module.

Provided are methods for nodes used for wireless communications, and an apparatus. A first node used for wireless communications comprises: a first receiver, which receives first information, wherein the first information is used for determining X ROs, and the X ROs are mapped to Q ROGs, X being a positive integer greater than 1, and Q being a positive integer; and a second receiver, which receives second information, wherein the second information is used for determining a plurality of candidate numerical values, the number of ROs comprised in any one of the Q ROGs is one of the plurality of candidate numerical values, the plurality of candidate numerical values include a first candidate numerical value and a second candidate numerical value, the larger value among the first candidate numerical value and the second candidate numerical value is preferentially used for the mapping from the X ROs to the Q ROGs, and / or the mapping from the X ROs to the Q ROGs is related to the numbers of ROGs respectively corresponding to the plurality of candidate numerical values.

Technologies for stacked memory devices with error recovery support are described. One stacked memory device includes a base layer and a plurality of memory layers. The base layer includes a primary interface for regular data, a secondary interface for checkpoint data, and a buffer for temporarily storing the checkpoint data. The buffer is accessible by the plurality of memory layers and the secondary interface. The base layer, in response to a first command, initiates a first transfer of a first block of bits from a memory layer of the plurality of memory layers into the buffer. The base layer, in response to a second command, initiates a second transfer of a second block of bits from the buffer out of the stacked memory device via the secondary interface. The second transfer occurs concurrently with a third transfer of data over the primary interface.

The invention provides a multi-dimensional construction data storage system and method, relates to the technical field of data storage, and realizes significant improvement of construction data storage efficiency and breakthrough of intelligent management capability by introducing multi-dimensional feature extraction, resolution factor calculation and a dimension perceptual hash algorithm. Firstly, original feature values of four dimensions are extracted from each construction data unit, standardized coding processing is carried out, a unified dimension code is generated, the precision degree and the association strength of data are quantitatively evaluated by calculating a time resolution factor, a space resolution factor and a coding similarity factor, and therefore a storage strategy is dynamically adjusted, and the storage efficiency is improved. According to the dimension perceptual hash algorithm, logic storage coordinates are intelligently generated through the factors, data with similar characteristics are naturally gathered on physical storage, data items are temporarily stored by maintaining an ordered structure on the memory management level, sorting is conducted according to the logic coordinates, disk random write-in operation is effectively reduced, and write-in performance is improved.

The invention relates to a system and a method for processing and packaging value documents, in particular banknotes. The system has a processing device which is designed to process value documents, in particular to check, classify and / or destroy the value documents; at least one binding device configured to bind the processed value documents into packs and / or to bind the processed value documents bound into one or more packs into respective bundles; a packaging device configured to package one or more packets and / or bundles; and a conveying device configured to convey the one or more packets and / or bundles to a packaging apparatus. Furthermore, there is at least one storage device configured to receive one or more packets and / or bundles; and a control device configured to control the at least one storage device such that one or more packets and / or bundles can be temporarily stored in the storage device when the conveying device and / or the packaging apparatus cannot receive any other packets and / or bundles.

The present disclosure relates to apparatuses and methods of capturing register state. Some aspects of the present disclosure relate to an apparatus comprising a register circuit implementing a plurality of registers, and a processing circuit to perform data processing operations on data stored in the registers. The apparatus comprises a store buffer circuit to temporarily store given data prior to providing the given data to a memory in response to a store instruction on the given data. In response to receiving a request at the processing circuit to perform a state save trigger operation, the register circuit is configured to capture a state of a subset of registers of the plurality of registers in shadow registers of the register circuit, and to provide the captured state from the shadow registers to the memory.

A processing apparatus for accelerating convolution operations according to one embodiment includes a plurality of elementary processing unit arranged in an array structure, a line buffer in which data is temporarily stored, and a controller configured to control operations of the line buffer and the elementary processing unitelementary processing units to perform convolution operations. The controller stores a portion of feature-map data in the line buffer for the convolution operation, performs convolution operations on the portion of feature-map data stored in the line buffer and kernel data stored in the elementary processing unit, and divides a feature map to be processed during the convolution operation into a plurality of partitions in consideration of a storage capacity of the line buffer and a size of the feature map, and stores, in the line buffer, data among the divided feature-map data to be operated with the kernel data.

A host device and a method of operating a host device are provided. The host device includes a cache configured to temporarily store data copied from a main memory, and a processor configured to process data read from the cache. The cache includes a plurality of ways, wherein each of the plurality of ways has an area distinguished by a plurality of indexes, the data includes first data, and the plurality of indexes includes a first index. The processor includes a cache management circuit configured to generate the first index by using a first adaptive matrix and a first vector, wherein the first adaptive matrix is based on upper bits of a first address corresponding to the first data, and the first vector is based on lower bits of the first address, and manage the first data to be temporarily stored in an empty area among areas corresponding to the first index in the plurality of ways.

The invention discloses an astronomical observation data key value storage optimization method and system based on a persistent memory. Comprising the following steps: receiving an original data stream of astronomical observation equipment, analyzing observation attribute information carried in the original data stream, generating a hierarchically coded key based on the observation attribute information, and packaging the key and a corresponding observation data value into a write-in request; accumulating the write request as batch data, distributing a continuous storage space for the batch data in a data area of a persistent memory, and writing the batch data into the distributed storage space by using a non-temporary storage instruction; updating the index structure based on the key and the storage address of the observation data value in the persistent memory; and according to the type and condition of the query request, positioning the address of the target data in the persistent memory through the index structure, and reading the data. According to the method, the nanosecond access delay and byte addressing characteristics of the persistent memory are utilized, and real-time reliable storage and rapid multi-dimensional retrieval of new-generation astronomical observation data are achieved.

The invention provides an improved apparatus and method for delaying high-speed constant bitrate signals in a programmable manner. For this purpose, a signal is demultiplexed into individual data units, and the data units are temporarily stored in a high bandwidth memory by writing and reading via multi-channel first data transfer. In this way, the temporary storage of data can be achieved without noticeable decrease of memory throughput and without interruption between writing and reading requests.

A portable network router system for communicating with a remote sensor is provided. The system comprises a transceiver configured to transmit and receive radio signals, and comprises a storage device configured to store program instructions and downloaded data. The system comprises a random access memory configured to temporarily store program instructions. The system comprises one or more processors operably coupled to the random access memory, the storage device and the transceiver.