533 results about "Voltage droop" patented technology

A system and method provides virtual ripple signal generation for use in voltage regulation applications. Some switch-mode power converters or voltage regulators use output signal ripple to effect voltage regulation. A virtual ripple generator provides this type of voltage regulator with a virtual ripple signal comprising an offset component responsive to actual load voltage, but with a generated AC ripple component of arbitrary magnitude that is independent of actual output signal ripple. Unlike the actual output ripple signal, the generated AC ripple component is not dependent on implementation specifics, such as circuit board layout or output capacitor ESR, and may have its gain set independent of the offset component. The generated AC ripple component is synchronized to the inductor switching actions of the voltage regulator and thus reflects actual inductor phase switching in single and multi-phase regulation applications. Virtual ripple signal generation can include output (load) voltage droop compensation.

A system and method for providing a digital real-time voltage droop detection and subsequent voltage droop reduction. A scheduler within a reservation station may store a weight value for each instruction corresponding to node capacitance switching activity for the instruction derived from pre-silicon power modeling analysis. For instructions picked with available source data, the corresponding weight values are summed together to produce a local current consumption value and this value is summed with any existing global current consumption values from corresponding schedulers of other processor cores yielding an activity event. The activity event is stored. Hashing functions within the scheduler are used to determine both a recent and an old activity average using the calculated activity event and stored older activity events. Instruction issue throttling occurs if either a difference between the old activity average and the recent activity average exceed a first threshold or the recent activity average exceeds a second threshold.

A frequency control circuit including a controlled oscillator and an amplifier circuit is disclosed for providing a clock signal to a switched capacitor circuit which divides an input voltage to provide an output voltage. The controlled oscillator has a frequency control input receiving a frequency control signal and an output for providing the clock signal at a frequency based on the frequency control signal. The amplifier circuit has an input for receiving the output voltage and an output providing the frequency control signal based on droop of the output voltage. In one embodiment, the amplifier circuit adjusts the frequency control signal to optimize efficiency of the switched capacitor circuit over a voltage range of the output voltage, which changes based on load level.

Provision is made in the housing of a host to provide a socket, or sockets, to which a peripheral piece of equipment can be connected for receiving directly from the host the low voltage DC power it requires. The socket(s) are connected electrically to the outputs of a power supply (or regulator) of a host for providing the low voltage needed to power the peripheral. The power supply may be mounted on the rear face of a computer. The principal feature of the invention resides in the use of a connector for connecting the host DC power to the peripheral DC power usage device. The connector comprises pins connected to a selected resistor in the power supply. The resistor value (i.e., resistance) is selected to produce a pre-determined control voltage which is fed back to a DC to DC converter in the host's internal power supply. The converter comprises a pulse width modulation control device. The control voltage determines the duty cycle (i.e., pulse width) of the modulation to reduce the output from a maximum voltage to an appropriate voltage suitable for the particular peripheral power usage device. Thus, by simply selecting the appropriate connector (or cable) having the proper pins correlated to a selected resistor previously installed in the power supply, the voltage level for the corresponding peripheral device is automatically selected. In an alternative embodiment, the DC power distribution apparatus of the present invention comprises a stand-alone unit having one or more universal ports for receiving a cable with a connector containing the appropriate pins for a selected DC power usage device.

Disclosed is a dead-time compensation method of a 3-phase inverter using an SVPWM scheme. The dead-time compensation method includes generating a switching signal having dead-time with respect to the power semiconductor switches of the upper and lower arms in order to obtain a predetermined output through the SVPWM scheme, detecting medium phase current from each phase current output through the switching signal, determining polarity of the medium phase current, and generating a switching signal by calculating switching time in order to compensate for time to apply effective voltage according to the polarity of the medium phase current. Through the dead-time compensation method, the distortion of the output voltage and the reduction of voltage having a fundamental wave in the output voltage, which are caused by the dead-time, are minimized through the switching of compensating for the time to apply effective voltage based on the polarity of the load current.

Method and apparatus for providing a peak detection circuit comprising a diode including an input terminal and an output terminal the input terminal of the diode configured to receive an input signal, a capacitor operatively coupled to the output terminal of the diode, an output terminal operatively coupled to the capacitor and the output terminal of the diode for outputting an output signal is provided. Other equivalent switching configuration is further provided to effectively detect and compensate for a voltage droop from a power supply signal, as well as to electrically isolate the voltage droop from the system circuitry.

Parallel stage power output rectifiers for radio-frequency identification (RFID) devices and related components and methods are disclosed. An RFID tag receives a radio-frequency (RF) signal comprising RF input energy through an input such as an antenna. The RF input energy provided to a rectifier splits the RF input energy into two or more stages having parallel electrical outputs. The parallel electrical outputs allow for a more efficient use of the input energy in terms of current draw and improves voltage droop, thus improving the range and operation of the RFID tag.

The invention discloses an inverter system based on the improved power distribution policy of a virtual synchronous generator. The inverter system comprises a grid-connected inverter system which is controlled by a virtual synchronous generator and is composed of a direct current voltage source, a three-phase bridge inverter circuit, an LCL filter, a public power grid, a load and a control drive circuit. The inverter system consists of an active regulator, an excitation regulator, a VSG algorithm module, and a voltage and current double closed-loop control module. The introduction of the control of the synchronous generator overcomes the problems of fast response and low inertia of a traditional grid-connected inverter. The permeability of renewable energy in a micro grid can be effectively improved. The dynamic characteristic of a synchronous generator rotor is introduced into a second-order transient model, which eliminates the influence of a traditional constant damping coefficienton droop control. In addition, by improving the reactive-voltage droop control, the influence of the inverter output filter impedance and the line impedance on reactive power distribution is reduced,and reasonable distribution of the inverter output power is ensured.

Circuits, systems, and methods for monitoring a power supply voltage and determining if the power supply voltage has drooped are disclosed. In one embodiment, a voltage monitoring circuit is provided and configured to determine if the power supply voltage supplied to a functional circuit has drooped. When no droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a first mode. When droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a second mode. In this manner, operating margin in the power supply may be reduced since the functional circuit may be configured to properly operate when a voltage droop of the power supply voltage occurs.

The invention discloses a high-voltage ESD protective device with dual latch-up resistance and of an annular LDMOS-SCR structure. The high-voltage ESD protective device with the dual latch-up resistance and of the annular LDMOS-SCR structure can be applied to an on-chip IC. The high-voltage ESD protective device with the dual latch-up resistance and of the annular LDMOS-SCR structure comprises a P type substrate, an N type buried layer, a first P trap, a first N trap, a second P trap, a P adulterant, a second N trap, a third P trap, an isolation area, a first P+, a first N+, a second N+, a second P+, a third N+, a third P+, a fourth N+, a fourth P+, a fifth N+, a sixth N+, a fifth P+, a metal anode and a metal cathode, wherein a Zener breakdown ESD current discharging path is formed by the second N+, the second P+, the first N+ and the first P+ or by the fourth P+, the fifth N+, the sixth N+ and the fifth P+. According to the high-voltage ESD protective device with the dual latch-up resistance and of an annular LDMOS-SCR structure, the ESD robustness of the device can be improved, the maintaining voltage can be improved, and the trigger voltage can be reduced; due to the design of the annular layout of the LDMOS-SCR structure, the on resistance can be reduced, and the maintaining current can be improved; the ESD protective capacity of the dual latch-up resistance is achieved.

A voltage droop detector captures the very high-frequency noise on the power grid of a load, such as a microprocessor. The droop detector includes twin circuits, one of which receives the voltage from the power grid of the load, the other of which receives a filtered voltage. A 0^th droop, as well as 1^st droops, 2^nd droops, and so on, are captured and stored for subsequent analysis. The circuits sample the voltages frequently enough to ensure that all droop events are captured. Other embodiments are described and claimed.

A voltage droop monitoring and correcting circuit for a microprocessor includes: a monitor circuit configured to monitor voltage droops of the microprocessor and perform a temporary clock-skipping technique to compensate for the voltage droops. A method for monitoring and correcting voltage droops of a microprocessor includes: monitoring voltage droops of the microprocessor; and performing a temporary clock-skipping technique to compensate for the voltage droops. A computer system includes memory; a processor operatively connected to the memory; and computer-readable instructions stored in the memory for causing the processor to: monitor voltage droops of the microprocessor; and perform a temporary clock-skipping technique to compensate for the voltage droops.

Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.

According to one aspect, embodiments of the invention provide a UPS system comprising an input, an output, a converter, an inverter configured to convert DC power into output AC power, and a controller configured to operate the inverter to introduce a voltage droop to the output AC power, wherein the controller includes an active power droop controller including a first moving average filter configured to sample instantaneous active power of the inverter to obtain instantaneous active power samples and calculate a first DC component of the instantaneous active power samples, and a first Min-Max filter configured to receive the first DC component of the instantaneous active power samples and output a second DC component of the instantaneous active power samples having a convergence time less than the first DC component, wherein the active power droop controller is configured to calculate the voltage droop based on the second DC component.

Supply voltage droop management circuits for reducing or avoiding supply voltage droops are disclosed. A supply voltage droop management circuit includes interrupt circuit configured to receive event signals generated by a functional circuit. Event signals correspond to an operational event that occurs in the functional circuit and increases load current demand to a power supply powering the functional circuit, causing supply voltage droop. The interrupt circuit is configured to generate an interrupt signal in response to the received event signal. Memory includes an operational event-frequency table having entries with a target frequency corresponding to an operational event. Operating the functional circuit at target frequency reduces the load current demand on the power supply, and supply voltage droop. A clock control circuit is configured to receive interrupt signal, access memory to determine the target frequency, and generate clock frequency adjustment signal to cause clock generator to adjust to the target frequency.