Tri-level dynamic element matcher allowing reduced reference loading and dac element reduction

Abstract

Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements.

Description

BACKGROUND OF THE INVENTION[0001](1) Field of the Invention[0002]This invention relates generally to digital-to-analog converters (DAC) and relates more specifically to three-level DACs applying dynamic element matching (DEM) techniques.[0003](2) Description of the Prior Art[0004]A digital-to analog converter (DAC) is a device for converting a digital (usually binary) code to an analog signal (current, voltage or electric charge). The DAC fundamentally converts finite-precision numbers (usually fixed-point binary numbers) into a continuously varying physical quantity, usually an analogue electrical voltage.[0005]In an ideal DAC, the numbers are output as a sequence of impulses, that are then filtered by a reconstruction filter. The DAC fundamentally converts finite-precision numbers (usually fixed-point binary numbers) into a continuously varying physical quantity, usually an analogue electrical voltage.[0006]In an ideal DAC, the numbers are output as a sequence of impulses, that ar...

AI Technical Summary

Benefits of technology

[0038]A principal object of the present invention is to achieve methods and systems to achieve a multi-bit delta-sigma DAC having a reduced power consumption.

[0041]A further object of the present invention is to achieve a multi-bit delta-sigma DAC having a reduced peak reference current and a reduced reference loading.

[0042]A further object of the present invention is to reduce power consumption and voltage droop of a delta-sigma DAC.

[0043]Another object of the present invention is reduce circuit complexity required to implement a N-bit delta-sigma DAC.

[0044]Moreover an important objective of the invention is to achieve low distortion in spite of variations of circuit elements

Problems solved by technology

This would, in principle, reproduce a sampled signal precisely up to the Nyquist frequency, although a perfect reconstruction filter cannot be practically constructed as it has infinite phase delay; and there are errors due to quantization.

However, this filter means that there is an inherent effect of the zero-order hold on the effective frequency response of the DAC resulting in a mild roll-off of gain at the higher frequencies (often a 3.9224 dB loss at the Nyquist frequency) and depending on the filter, phase distortion.

However, mismatches (such as random manufacturing variations) between the unit elements used to build a multi-bit DAC can cause non-linearity in the DAC transfer function, which causes signal distortion when converting a distortion-free digital signal to an analog signal.

A further known issue with most switched capacitor DACs implementations is signal-dependent loading of the DAC reference voltages, which can lead to signal distortion.

One way to remove signal dependency is to always draw the maximum reference current, but this maximizes reference power, which is undesirable in low-power systems.

It is a challenge for the designers of DACs to reduce therefore the peak reference current significantly compared to prior art.

Adding a discharge phase in the clocking arrangement removes all traces of signal from the DAC capacitors before they are switched to the reference, This achieves signal independence but makes the clock generation more complicated and results in maximum reference loading for all digital input codes.

A well known problem with dependency of the reference charge on the DAC input code is that providing this charge requires a current to flow from or to the reference voltage source, and this current flow can modify the reference voltage through interaction with the reference sources output impedances (e.g. ohmic drop).

Any signal-dependent variation of the reference voltages with changing DAC input causes non-linearity of the DAC analog output versus digital input code transfer function, and subsequent distortion of any signals being converted to analog.

A further well-known serious problem with multi-bit S / C (and current steering) DACs is that the individual DAC unit elements, C1-CN, cannot be manufactured to be exactly equal, but will have unavoidable random variations from ideal (“mismatches”) due to manufacturing variations.

These mismatches can cause nonlinearity of the DAC transfer function and hence distortion of any digital signals being converted to analog.

It is a challenge for the designers of DACs to reduce therefore the peak reference current significantly compared to prior art.

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