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Prioritising instructions according to category of instruction

An instruction and priority technology, applied in instruction analysis, address formation of the next instruction, multi-programming device, etc., can solve problems such as inability to ensure processor performance

Active Publication Date: 2015-02-11
MIPS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this strategy alone does not ensure optimal processor performance

Method used

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  • Prioritising instructions according to category of instruction
  • Prioritising instructions according to category of instruction
  • Prioritising instructions according to category of instruction

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Embodiment Construction

[0024] The embodiments of the present invention are described below by way of example only. These examples represent the best mode currently known to the applicants for practicing the invention, but these examples are not the only ways in which the invention may be practiced. The description sets forth the function of the example and the sequence of steps for constructing and operating the example. However, the same or equivalent functions and sequences can be implemented by different examples.

[0025] It has been demonstrated that executing some types of instructions (eg, control transfer instructions, flag-setting instructions, and address generation instructions) as quickly as possible, even if they are younger than other ready instructions, can significantly increase processor performance. This is because, once these types of instructions have been issued, they free up other resources that can be used by other instructions.

[0026] Accordingly, embodiments described he...

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Abstract

A method of selecting instructions to issue to a functional unit of an out-of-order superscalar processor single-threaded or multi-threaded. A reservation station classifies each instruction into one of a number of categories based on the type of instruction. Once classified, an instruction is stored in one of several instruction queues corresponding to the category in which it was classified. Instructions are then selected from one or more of the instruction queues (up to a maximum number of instructions for each particular queue) to issue to the functional unit based on a relative priority of the plurality of types of instructions. This allows certain types of instructions (eg. control transfer instructions, flag setting instructions and / or address generation instructions) to be prioritised over other types of instructions even if they are younger. A functional unit may contain a plurality of pipelines, and there may be several such functional units in a processor.

Description

Background technique [0001] Superscalar processors are designed to issue more than one instruction per clock cycle. Typically, these processors include one or more reservation stations that receive and store instructions until they are ready to issue to the out-of-order pipeline for execution. An instruction is considered ready to issue when all of its input operands are available. [0002] Each clock cycle, the reservation station selects a number of ready instructions (eg, one for each out-of-order pipeline) and issues them to the out-of-order pipeline for execution. However, in any given clock cycle, there will be multiple instructions ready to issue. Therefore, there must be some mechanism for selecting ready instructions for issue to the out-of-order pipeline. [0003] Typically, the oldest ready instruction is given the highest priority and the youngest ready instruction is given the lowest priority. Issuing the oldest instructions as quickly as possible ensures that...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/48
CPCG06F9/3855G06F9/3851G06F9/3836G06F9/3888G06F9/3856G06F9/3016G06F9/32G06F9/384
Inventor A·霍特H·杰克逊
Owner MIPS TECH INC
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