163results about "Next instruction address formation" patented technology

The invention discloses an IP event counting device and method, equipment and a storage medium. Comprising an IP function module and a power management module. The IP function module comprises a counting register; the power management module comprises a counting mirror image register and a cardinal number register; the counting register is connected with the counting mirror image register through a hardware connection line; when the IP function module is powered off, the IP function module reads the first count value from the count register and reads the third count value from the cardinal number register, the first count value and the third count value are accumulated, and an accumulation result is written into the cardinal number register to serve as a new third count value; and when the IP function module is in a power-on state, the power management module reads the second count value from the counting mirror image register every set duration, accumulates the read second count value and the third count value through the adder, and determines an accumulation result as a target count value of the preset IP event. And occupation of software and hardware resources of the power management system is reduced.

The invention provides a multi-discontinuous register reading method for improving Modbus protocol communication rate and a function code. The multi-discontinuous register reading method comprises the following steps: defining a function code 43H in a Modbus protocol; the method comprises the following steps: determining the type, address list and number of discontinuous registers to be read through a master device, assembling a request frame, and sending the request frame to a slave device; after the slave device receives the request frame, address matching and verification are carried out on the request frame, and if the address is not matched or verification fails, the frame is discarded; if the address is matched and the verification is passed, analyzing, judging whether abnormity exists or not, and executing related operation based on a judgment result; the master device receives the response frame returned by the slave device, verifies the response frame, and analyzes a data list in the response frame to obtain data of each register if the response frame passes the verification and is a normal response frame; if verification fails or the frame is responded abnormally, error processing is carried out, and the multi-discontinuous register reading method which can improve the communication rate, reduce the communication overhead and enhance the real-time performance and is high in compatibility is provided.

The invention belongs to the technical field of integrated circuit simulation verification, particularly relates to an RISC-V simulation resource dynamic generation method and system, and solves the problems of instruction consistency and variable-length instruction truncation through a metadata double-table structure and a cross-boundary instruction splicing mechanism. Virtualized two-stage translation support and abnormal injection are realized through a recursive multiple hit detection and dynamic attribute bit modification mechanism. According to the method, complete storage is replaced with lightweight metadata, memory occupation is remarkably reduced, the problem that memory occupation is linearly increased along with time is solved, simulation efficiency and consistency are improved, and the method is suitable for full-system verification of a high-performance RISC-V processor.

A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), a fusion engine. An ME holds MOPs into which architectural instructions of one or more FBlks are decoded. The PRU detects a loop body ME within the program instruction stream, accumulates loop iteration count information about a series of instances of a loop on the loop body ME in the program instruction stream, updates a consistency counter of the loop body ME while accumulating the loop iteration count information, and in response to detecting that the consistency counter has reached a threshold, instructs the fusion engine to use F copies of the MOPs of the loop body ME to build in the MOC an unrolled loop multi-FBlk ME; F is a loop unroll factor that is at least two.

According to the SIMT architecture branch processing system and method based on the structured nodes, explicit node marks are inserted into branch codes through a compiler, accurate control over active masks of all threads in the program execution process is achieved, and part of branch codes, not needing to be executed currently, of the threads are shielded; a full-branch consistent detection unit is designed to judge three mask states of'all true / all false / divergence 'of current active masks of the same group of threads, so that the operation of instructions of irrelevant branches is directly skipped under a full-branch consistent scene (all true / all false), all instructions of all branches are normally executed under a divergence scene, and all the instructions of all the branches are normally executed under the divergence scene. The active masks control which instructions are executed by each thread, and the state of the active mask of each thread is accurately controlled through node marks.

An apparatus (10, 30, 50) comprising processing circuitry (51) to execute instructions, and threadlet execution circuitry (23, 49, 52) to execute tasks under control of the processing circuitry. The threadlet execution circuitry is configured to operate asynchronously with respect to the processing circuitry. The threadlet execution circuitry is responsive to a start command issued by the processing circuitry to begin execution of a threadlet comprising at least one delegated task. The processing circuitry is responsive to a threadlet-start instruction, the threadlet-start instruction indicating a request to issue the start command to the threadlet execution circuitry, to determine, in dependence on at least one parameter, whether to trigger execution, by the processing circuitry, of an alternative function instead of issuing the start command to the threadlet execution circuitry.

This invention relates to the field of data processing technology, and in particular to a method, apparatus, device, and medium for processing multi-dimensional data. The method instantiates a template based on input tensor parameters to obtain an offset calculation instance. The offset calculation instance is initialized to determine the step size and shape of each input array in each output dimension, and these are recorded in a designated storage space. The offset calculation instance is then started to perform index calculations on the step size and shape of each input array recorded in the storage space in each output dimension to obtain the offset corresponding to the output array. The data corresponding to the offset is then processed according to a set calculation rule to obtain the output result. By pre-calculating the step size and shape of each input array in each output dimension, unnecessary memory accesses can be reduced. Constructing offset calculation instances simplifies the index calculation process, enabling efficient and accurate data storage, retrieval, and calculation.

An apparatus comprising storage, an execution unit and a handling unit. The handling unit is configured to obtain task data that describes a task to be executed. The task comprises a plurality of operations representable as a directed graph of operations. The task data comprises task-specific variable data representative of a task-specific variable for use in executing an operation of the plurality of operations. The handling unit is configured to obtain a data move instruction and, based on the data move instruction, move the task-specific variable data into a physical storage location of the storage. The handling unit is configured to dispatch invocation data, based on the task data and the physical storage location, to the execution unit to cause the execution unit to execute the operation.

A system comprising a plurality of memory devices, as well as a processing device, operatively coupled with the plurality of memory devices. The processing device detects a write operation error during a write operation on a memory segment of the plurality of memory devices, wherein the memory segment comprises respective memory cells from each of the plurality of memory devices. The processing device determines that a back-to-back (B2B) count satisfies a B2B threshold criterion, wherein the B2B count corresponds to one of the plurality of memory devices. Responsive to determining that the B2B count satisfies the B2B threshold criterion, the processing device prevents, for a threshold duration of time, any subsequent write operations from being performed on the one of the plurality of memory devices, wherein a length of the threshold duration of time is determined by a period during which the B2B count continuously satisfies the B2B threshold criterion.

Techniques and mechanisms for determining an enablement state of a prefetch functionality based on a history of accesses to a memory region. In an embodiment, an access history record, which corresponds to a page of a cache or other memory, is accessed to determine whether a detected address, in a demand memory access, is numerically adjacent to any of multiple most recently accessed addresses of the page. A metric of a confidence in adjacent-line prefetches for the page is updated based on a numerical adjacency of accessed addresses. The metric is evaluated to determine whether adjacent-line prefetches for the page are to be enabled or disabled. In another embodiment, the enabling or disabling of a prefetches for a given page is determined based on a determination as to whether or not said page was subject to a prefetch access and, subsequently, to a corresponding demand memory access.

The invention provides a processor system and an interrupt response method. In the processor system, an interrupt controller is used for setting the state of a control register, receiving an interrupt request signal which is sent from the outside and is used for requesting to execute an interrupt service program, setting the state of the control register to be a first state value when the interrupt request signal is received, and executing the interrupt service program after the interrupt server program is executed. Setting the state of the control register as a second state value; the multiplexer is used for reading the state value of the control register, when the read state value of the control register is a first state value, the multiplexer is communicated with the shadow register group and the arithmetic unit, and when the read state value of the control register is a second state value, the multiplexer is communicated with the main register group and the arithmetic unit; the main register group is used for storing data when the main program is operated; and the shadow register group is used for storing data when the interrupt server program runs. The delay in the interrupt response process can be reduced, and the system performance is improved.

The invention relates to a program analysis method and device, electronic equipment, a storage medium and a computer program product, and the method comprises the steps that before a target program runs, a sampling buffer area is allocated to the target program, and the sampling buffer area comprises sampling buffer partitions allocated for each instruction in the target program; when any sampling moment is reached in the running process of the target program, instruction counter sampling is carried out, a sampling instruction of this time is determined, and a sampling counter in a target sampling buffer partition corresponding to the sampling instruction of this time is updated through atomic operation; after the operation of the target program is finished, determining the total sampling frequency of each instruction in the target program according to the sampling buffer area; and according to the total sampling frequency of each instruction in the target program, performing performance analysis on the target program to obtain a performance analysis result. According to the embodiment of the invention, the operation of the target program is not influenced under the condition that the sampling precision is ensured, and the performance analysis of the target program is effectively realized.

Systems and methods are disclosed for a configurable interconnect address remapper with event detection. For example, an integrated circuit can include a processor core configured to execute instructions. The processor core includes region registers defined by a From Address range and a To Address, a register storing a number of regions defined in the integrated circuit, interrupt enable registers associated with each pair of region registers, and event flags associated with each pair of region registers; an interconnection system handling transactions from the processor core; an interconnect address remapper translating an address associated with a transaction using the one or more pair of region registers; and an interrupt controller receiving an interrupt signal from the interconnect address remapper when the interrupt enable registers are enabled and at least one raised event flags when at least one of the one or more pair of region registers matches the transaction address.

A processor comprising storage, execution circuitry and a handling unit. The handling unit is configured to obtain task data that describes a task to be executed. The task comprises a plurality of operations representable as a directed graph of operations comprising operations connected by connections corresponding to respective logical storage locations. In executing the task, the execution circuitry is configured to operate over a multi-dimensional nested loop. The task data comprises operation-specific control data for an operation of the operations, the operation-specific control data providing an indication, for each respective dimension of a plurality of dimensions of the multi-dimensional nested loop on a per-dimension basis, of whether the operation is to be executed for each iteration of a plurality of iterations over the respective dimension. The handling unit manages execution of the operation, using the execution circuitry, based on the operation- specific control data.

Aspects of the disclosure are directed to an adaptive cache memory buffer register reassignment. In accordance with one aspect, the disclosure includes incrementing a write hit-miss state based on a write address validation state and a write data validation state; incrementing a read hit-miss state based on a read address validation state and a read data validation state; computing a net mode count based on the write hit-miss state and the read hit-miss state; comparing the net mode count to a mode threshold value to update a plurality of mode toggle states; and generating an adaptive cache memory buffer register reassignment based on the plurality of mode toggle states.

An integrated circuit includes a memory bus coupled to a random access memory (RAM). A plurality of ports enable hardware logic to access the RAM over the memory bus. A central processing unit (CPU) is coupled to the memory bus. A first hardware logic module is coupled to a first port, of the plurality of ports, to share access to the memory bus with the CPU. A plurality of hardware registers, coupled to the plurality of ports, include a first hardware register to store a number of accesses, by the first hardware logic module, to the memory bus over the first port.

A data processing apparatus is provided in which receive circuitry receives a memory access instruction containing an indication of a target address. The target address is associated with one of a plurality of memory targets. Prediction circuitry performs a prediction of one of the plurality of memory targets to which the memory access instruction is associated, based on an address associated with the memory access instruction and forward circuitry forwards a memory access request based on the memory access instruction to the one of the plurality of memory targets.

Provided is a processor enabling assembly code of a direct-addressing conditional-jump subroutine to be reduced. The processor includes a logic circuit executing a conditional-jump instruction of assembly code, and logically configured to: store, into an index register, an index register number that is an index to a jump-destination effective address; store jump-destination effective addresses differing from one another, or address offsets to jump-destination effective addresses differing from one another, into plural reference registers, respectively; fetch and decode a conditional jump instruction that is one instruction that quotes the index register; and then execute (S1) acquiring a jump-destination effective address or an address offset from the reference register corresponding to the index register number of the content of the index register and (S2) setting the acquired jump-destination effective address, or a jump-destination effective address calculated from the address offset, to a register serving as the program counter.

A processor of an aspect includes a decode unit to decode an indirect control flow transfer instruction, the instruction to indicate a register that is to store information to indicate an instruction pointer of a target instruction. An execution unit is to perform operations corresponding to the instruction, including to determine whether at least a first set of bits of an instruction pointer of the indirect control flow transfer instruction are compatible with at least a second set of bits of the instruction pointer of the target instruction. The operations also include to either store the instruction pointer of the target instruction in an instruction pointer storage if the first and second sets of bits are determined to be compatible, or to not store the instruction pointer of the target instruction in the instruction pointer storage if the first and second sets of bits are determined to not be compatible.

To solve the problem that it is impossible to increase the speed of vector instruction processing.SOLUTION: A vector instruction processing apparatus 100 of the present invention comprises: a writing unit 101 which writes a vector instruction included in loops to be executed repeatedly to mutually different reservation stations 110 corresponding to the respective loops; and a vector execution unit 102 which executes the vector instruction issued from the individual reservation stations 110.SELECTED DRAWING: Figure 10

This invention discloses a hardware-accelerated loop processing system, relating to the field of digital signal processing technology, to address the technical problem that the loop control overhead of existing loop structures accounts for too high a proportion of the total execution time, leading to a decrease in system performance. The hardware-accelerated loop processing system of this invention connects an instruction decoding unit, an instruction receiving unit, and a branch prediction unit, and includes a control module, a storage module, a loop counting module, and an instruction fetch address calculation module. The control module is configured as a hardware loop controller to coordinate the other modules and make decisions based on the current processor state. The storage module stores the boundary address of the current loop. The hardware loop controller optimizes instruction fetching through a loop buffer or cache. During the first execution of the loop, the instruction is fetched and stored in the loop buffer or cache. In subsequent iterations, when it is determined that the loop will continue, the instruction fetch address calculation module is instructed to read instructions from the loop buffer or cache.

[Problem] To provide more useful techniques. [Solution] One aspect of the present invention provides an information processing method based on a command system. The command system in the information processing method includes a command in which a relative position referring to a past execution result serves as an operand. The information processing method comprises the following steps. In an acquisition step, an operand related to a repeat command included in the command system is acquired. In an execution step, an operation corresponding to a predetermined command is repeatedly executed on the basis of the acquired operand. The operand includes a first operand indicating the number of repetitions of the predetermined command, and a second operand indicating a stride of a register of the predetermined command.

Techniques are provided for performing an instruction fetch operation, including determining an instruction address of a primary branch prediction path, requesting a level 0 translation lookaside buffer (TLB) to cache an address translation of the primary branch prediction path, determining one or both of an alternate control flow path instruction address and a lookahead control flow path instruction address, and requesting the level 0 TLB or an alternate level TLB to cache address translations of one or both of the alternate control flow path instruction address and the lookahead control flow path instruction address.

The invention provides a dynamic instruction replacement method and device, equipment and a storage medium, and the method comprises the steps: determining a to-be-optimized instruction group according to instruction operation information of a plurality of instruction groups, and obtaining a replacement instruction group corresponding to the to-be-optimized instruction group, the performance of the replacement instruction group is better than that of the to-be-optimized instruction group, and the performance of the replacement instruction group is better than that of the to-be-optimized instruction group; and storing the replacement instruction group to a pre-occupied virtual address field, if the to-be-processed current instruction stream comprises the to-be-optimized instruction group, skipping to the virtual address field to execute the replacement instruction group when executing to the to-be-optimized instruction group in the current instruction stream, and skipping to the current instruction stream after the execution of the replacement instruction group is finished, and executing instructions behind the instruction group to be optimized. According to the method and the device, function-level instruction replacement is realized, the program optimization cost is reduced, and the program running efficiency can be effectively improved.

The application discloses an IP event counting device, method, equipment and storage medium. The device comprises an IP function module and a power management module; the IP function module comprises a counting register; the power management module comprises a counting mirror register and a base register; the counting register and the counting mirror register are connected through hardware wiring; when the IP function module is powered off, the IP function module reads a first counting value from the counting register and a third counting value from the base register, adds the first counting value and the third counting value, and writes the addition result into the base register as a new third counting value; when the IP function module is in a power-on state, the power management module reads a second counting value from the counting mirror register every set time length, adds the read second counting value and the third counting value through an adder, and determines the addition result as a target counting value of a preset IP event. The application reduces the occupation of software and hardware resources of the power management system.

The invention discloses a method for realizing timeout completion of a PCIe (Peripheral Component Interconnect Express) transaction layer, and relates to the technical field of PCIe. The method comprises the following steps: configuring a step length control module by system management software, setting a time unit of timeout calculation, and determining a register value; allocating a storage entry Entry for the PCIe request message, and generating a corresponding index identifier Entry ID; periodically accumulatively timing according to a step value through an internal timer, and updating timing information corresponding to the Entry when the accumulatively counted number reaches a preset threshold value of software; when detecting that the request transaction corresponding to the Entry receives a normal completion message, clearing the request information, the timing information and the effective mark in the storage entry Entry; and when the timing information of the storage entry Entry reaches the maximum value, judging that the request is overtime, and triggering an interrupt message to notify HOST software. According to the invention, a completion timeout hardware mechanism of the PCIe transaction layer is provided, and the reliability and the debugging capability are improved.

This invention relates to integrated circuits. The integrated circuit includes: a processor core including a pipeline configured to execute instructions; an indirect jump target predictor circuit configured to generate a prediction of the target address of an extracted indirect jump instruction; and an immediate jump handler circuit configured to: detect an instruction sequence extracted by the processor core, wherein the instruction sequence includes a first instruction followed by a second instruction as an indirect jump instruction, the first instruction having a result depending on an immediate digital field and a program counter value of the first instruction; prevent the indirect jump target predictor circuit from generating a target address prediction for the second instruction in response to detecting the instruction sequence; and determine the target address of the second instruction based on the immediate digital field and the program counter value of the first instruction before issuing the first instruction to an execution stage of the pipeline.

A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.