315results about "Next instruction address formation" patented technology

Techniques are described for efficient replication and maintaining snapshot data consistency during file storage replication between file systems in different cloud infrastructure regions. In certain embodiments, provenance IDs are used to efficiently identify a starting point (e.g., a base snapshot) for a cross-region replication process, conserve cloud resources while reducing network and IO traffic.

The invention discloses an IP event counting device and method, equipment and a storage medium. Comprising an IP function module and a power management module. The IP function module comprises a counting register; the power management module comprises a counting mirror image register and a cardinal number register; the counting register is connected with the counting mirror image register through a hardware connection line; when the IP function module is powered off, the IP function module reads the first count value from the count register and reads the third count value from the cardinal number register, the first count value and the third count value are accumulated, and an accumulation result is written into the cardinal number register to serve as a new third count value; and when the IP function module is in a power-on state, the power management module reads the second count value from the counting mirror image register every set duration, accumulates the read second count value and the third count value through the adder, and determines an accumulation result as a target count value of the preset IP event. And occupation of software and hardware resources of the power management system is reduced.

Modifications to existing computer hardware, compiler changes or source-to-source transforms performed during the software build process, and a collection of libraries and modifications to existing standard system software and libraries. The invention allows a program author to enforce various kinds of locality of causality in software to provide enforcement of boundaries for the following aspects of a computer program: control, space, time, modularity, reference, initialization, and mutability. Where these properties do not suffice to guarantee a property at static time, dynamic checks may be added and the constraints on control flow prevent such dynamic checks from being avoided by the program.

The invention provides a multi-discontinuous register reading method for improving Modbus protocol communication rate and a function code. The multi-discontinuous register reading method comprises the following steps: defining a function code 43H in a Modbus protocol; the method comprises the following steps: determining the type, address list and number of discontinuous registers to be read through a master device, assembling a request frame, and sending the request frame to a slave device; after the slave device receives the request frame, address matching and verification are carried out on the request frame, and if the address is not matched or verification fails, the frame is discarded; if the address is matched and the verification is passed, analyzing, judging whether abnormity exists or not, and executing related operation based on a judgment result; the master device receives the response frame returned by the slave device, verifies the response frame, and analyzes a data list in the response frame to obtain data of each register if the response frame passes the verification and is a normal response frame; if verification fails or the frame is responded abnormally, error processing is carried out, and the multi-discontinuous register reading method which can improve the communication rate, reduce the communication overhead and enhance the real-time performance and is high in compatibility is provided.

A differential matching prefetcher for coping with irregular memory access includes: an access index table, an access target table, a differential matching module, an index queue, an indirect memory access candidate scoreboard, an address generator, an indirect memory access relationship table, a prefetch status handling register, a repetition filter, a continuous address filter, and a range prefetch table. The differential matching prefetcher is configured to monitor events of access requests and data responses between a computing core and a first level of cache, as well as between the first level of cache and a second level of cache. The differential matching prefetcher may be applied in various general-purpose computing architectures adopting a hierarchical storage design to realize mode capture and data prefetch for irregular indirect memory access, reduce long-delay storage access overhead caused by the irregular memory access, and increase instructions per cycle (IPC) of the computing architectures.

An embodiment of an integrated circuit may comprise a processor with one or more cores and circuitry coupled to the one or more cores, the circuitry to control one or more interrupts based on an interrupt expansion data structure, and report information derived from the interrupt expansion data structure to a software interrupt handler. Other embodiments are disclosed and claimed.

The invention belongs to the technical field of integrated circuit simulation verification, particularly relates to an RISC-V simulation resource dynamic generation method and system, and solves the problems of instruction consistency and variable-length instruction truncation through a metadata double-table structure and a cross-boundary instruction splicing mechanism. Virtualized two-stage translation support and abnormal injection are realized through a recursive multiple hit detection and dynamic attribute bit modification mechanism. According to the method, complete storage is replaced with lightweight metadata, memory occupation is remarkably reduced, the problem that memory occupation is linearly increased along with time is solved, simulation efficiency and consistency are improved, and the method is suitable for full-system verification of a high-performance RISC-V processor.

The invention discloses a command processing method and device, equipment and a medium, and relates to the technical field of computers, and the command processing method comprises the following steps: extracting a plurality of first logic block address ranges from a logic block address range queue; the first logic block address range is a logic block address range which needs to be accessed, and the second access logic block address range is a logic block address range which does not need to be accessed; writing a logic block initial address determined based on the first first logic block address range and the number of logic blocks corresponding to each logic block address range into a target field in a submission queue entry corresponding to the to-be-processed command; setting a target length flag value in the target field; sending a submission queue entry carrying the current target field to a controller, so that the controller determines a plurality of first logic block address ranges based on information in the current target field; and obtaining a command processing result corresponding to the to-be-processed command generated after the controller accesses the plurality of first logic block address ranges. According to the invention, the transmission efficiency is improved.

The invention is suitable for the technical field of processors, and particularly relates to a memory access dependency prediction method and system for a processor and a storage medium. The memory access dependency prediction system comprises a loading and storage dependency predictor used for predicting whether address dependency exists in a loading instruction and a storage instruction; the loading and storage dependency predictor comprises a loading instruction reordering cache, a storage instruction reordering cache, an index generator, a loading and storage dependency historical record table and a storage execution record table; the storage execution record table is used for recording a storage instruction reordering cache index value and a reordering cache age value of the storage instruction. Compared with the prior art, the method has the advantages that the address dependency prediction accuracy and efficiency of the loading instruction and the storage instruction are higher, and the performance of the processor is better.

A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.

The invention provides a cyclic branch prediction instruction fetching device, a processor and electronic equipment. A reference unit generates a reference address according to acquired address data; the instruction storage unit reads a historical reference address to pre-fetch an instruction, and when the instruction storage unit is hit, after K clock cycles, a target instruction corresponding to the historical reference address is transmitted to the first branch predictor; the first branch predictor is used for reading a historical reference address, performing address prediction according to the historical reference address and a target instruction corresponding to the historical reference address, and providing a predicted address to the reference unit; and the second branch predictor is used for reading the historical reference address, and providing the stored cycle start address to the reference unit under the condition that the historical reference address is the same as the cycle end address stored in the historical reference address and the number of to-be-cycled times is greater than 0. The instructions are reduced to maintain cyclic variables and judgment conditions, so that the complexity and maintenance difficulty of codes can be reduced, the acquisition efficiency of the instructions is improved, and the performance potential of a processor is fully exerted.

The invention discloses an instruction scheduling system and method and electronic equipment, and relates to the technical field of computers, a dispatch module writes a to-be-scheduled instruction and a renamed register index combination into a dispatch queue, and a dependency check module constructs a dependency linked list according to the dispatch queue so as to determine an instruction execution sequence and send the instruction according to the instruction execution sequence; according to the method, the sending sequence and the execution sequence of the instruction with RAW dependency are ensured to be matched, so that the technical problems of low RAW dependency processing efficiency, long instruction waiting time and waste of pipeline instruction storage resources in the instruction scheduling of the superscale out-of-order processor can be solved, and the execution delay of the instruction is reduced.

The embodiment of the invention provides a binary translation method and device, electronic equipment and a readable storage medium, in the process of performing binary translation on a binary file of a source platform, if a current instruction is a memory access instruction, based on corresponding target address information after performing binary translation on the current instruction, the memory access instruction is accessed to the source platform; determining a target access address corresponding to the target platform; based on the target memory access address, generating a binary translated target check instruction corresponding to the current instruction; executing the target checking instruction to perform address checking on the target memory access address, and executing a target memory access operation corresponding to the current instruction under the condition that the target memory access address does not belong to a preset address constraint range; the preset address constraint range comprises a memory area which does not allow the target check instruction to access in the target platform. On the premise of ensuring the binary translation performance, the security of the binary translation process and the security and isolation of the resource data in the target platform are improved.

A verified stack trace can be generated by utilizing information contained in a shadow stack, such as a hardware protected duplicate stack implemented for malware prevention and computer security. The shadow stack contains return addresses which are obtainable without requiring an unwinding of the traditional call stack. As such, triaging based on return address information can be performed more quickly and more efficiently, and with a reduced utilization of processing resources. Additionally, the generation of a verified stack trace can be performed, with such a verified stack trace containing return addresses that are known to be correct and not corrupted. The return addresses can either be read from the traditional call stack, or derived therefrom, and then verified by comparison to corresponding return addresses from the shadow stack, or they can be read directly from the shadow stack.

An analysis function providing method executed by an analysis function providing device includes first analyzing a virtual machine of a script engine and acquiring a virtual program counter that is a variable indicating an instruction of the virtual machine to be executed next and a conditional branch flag that is an area for holding a flag as to whether or not branch is made at a time of conditional branch in an execution state, and providing an analysis function to the script engine by applying a hook including processing of detecting an instruction sequence a number of times of repeated execution of which is greater than or equal to a threshold and stopping execution of the instruction sequence by rewriting a condition related to a conditional branch at an end of the instruction sequence on a basis of the virtual program counter and the conditional branch flag.

A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), a fusion engine. An ME holds MOPs into which architectural instructions of one or more FBlks are decoded. The PRU detects a loop body ME within the program instruction stream, accumulates loop iteration count information about a series of instances of a loop on the loop body ME in the program instruction stream, updates a consistency counter of the loop body ME while accumulating the loop iteration count information, and in response to detecting that the consistency counter has reached a threshold, instructs the fusion engine to use F copies of the MOPs of the loop body ME to build in the MOC an unrolled loop multi-FBlk ME; F is a loop unroll factor that is at least two.

According to the SIMT architecture branch processing system and method based on the structured nodes, explicit node marks are inserted into branch codes through a compiler, accurate control over active masks of all threads in the program execution process is achieved, and part of branch codes, not needing to be executed currently, of the threads are shielded; a full-branch consistent detection unit is designed to judge three mask states of'all true / all false / divergence 'of current active masks of the same group of threads, so that the operation of instructions of irrelevant branches is directly skipped under a full-branch consistent scene (all true / all false), all instructions of all branches are normally executed under a divergence scene, and all the instructions of all the branches are normally executed under the divergence scene. The active masks control which instructions are executed by each thread, and the state of the active mask of each thread is accurately controlled through node marks.

Disclosed in the present application is a tensor processing unit. The tensor processing unit comprises: an instruction sequence module, which is configured to generate a first instruction sequence and / or a second instruction sequence on the basis of a tensor operation instruction and preset configuration information, wherein the first instruction sequence comprises a plurality of first operation instructions, the second instruction sequence comprises a plurality of second operation instructions, and the preset configuration information comprises first configuration information and / or second configuration information; a data loading module, which is configured to sequentially load, on the basis of the first instruction sequence or the second instruction sequence, into corresponding registers data to be operated; a first computing module, which is configured to sequentially read, on the basis of the first instruction sequence, data from the registers, so as to perform in-memory computing; and a second computing module, which is configured to sequentially read, on the basis of the second instruction sequence, data from the registers, so as to perform non-in-memory computing. Further provided in the present application is a tensor processing method. A unified macro instruction is used to call different computing modules for in-memory computing or non-in-memory computing, thereby reducing the programming complexity and improving the computing efficiency.

Modifications to existing computer hardware, compiler changes or source-to-source transforms performed during the software build process, and a collection of libraries and modifications to existing standard system software and libraries. The invention allows a program author to enforce various kinds of locality of causality in software to provide enforcement of boundaries for the following aspects of a computer program: control, space, time, modularity, reference, initialization, and mutability. Where these properties do not suffice to guarantee a property at static time, dynamic checks may be added and the constraints on control flow prevent such dynamic checks from being avoided by the program.

The invention relates to an IR voltage drop method and device of a control chip, a storage medium and a program product. The method comprises the steps of determining predicted power of a chip according to information of a to-be-executed instruction of the chip; determining a current-resistance IR voltage drop prediction value of the chip according to the prediction power; according to the IR voltage drop prediction value and the maximum instantaneous allowable voltage drop, determining an IR voltage drop exceeding prediction quantity of the chip; and performing power control on the chip according to the IR voltage drop standard exceeding predictive quantity. The power change of the chip is pre-judged in advance through instruction level analysis instead of passively responding to voltage fluctuation, an optimized power control strategy can be generated in advance, the working state of the chip is actively adjusted before the IR voltage drop is caused by current abrupt change, and therefore the IR voltage drop can be dynamically restrained on the premise that hardware design is not changed, and the reliability of the chip is improved. And the performance loss caused by the IR voltage drop is further reduced.

A string operation method, string operation device, and storage medium are disclosed. The method comprises: obtaining a unit operation width corresponding to the type of string operation; obtaining a processing data width for the target data to be operated; obtaining a number of repeated operations of the string operation on the target data; determining mask information based on the unit operation width, the processing data width, and the number of repeated operations; and writing the operation portion to a target address based on the mask information. This method effectively improves the execution speed of string operation instructions, reduces the number of micro-operations during the execution of string operation instructions, and increases the utilization of processor hardware resources.

This invention relates to a processor pipeline system, a long-distance jump processing method, and related equipment. The system is optimized for long-distance jump scenarios. During the instruction fetch stage, long-distance jump detection is designed for the jump address, and an L0 instruction cache is added to the cache system. When a long-distance jump occurs, the instruction fetch timing is optimized by simultaneously querying multiple levels of cache, thereby saving additional cache read time caused by potential cache misses. Furthermore, based on the fast read / write performance of the L0 instruction cache, this invention designs a pre-fetch instruction method, which can further reduce instruction read latency and optimize processor performance.

A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.

The embodiment of the invention provides an instruction processing method, a processor, a chip and electronic equipment. The method comprises the steps of obtaining a to-be-pushed return address corresponding to a currently predicted and hit calling instruction; determining whether the to-be-pushed return address is the same as a return address pointed by a return pointer in a return address stack or not; the return address stack is used for storing the return addresses in sequence, and the return pointer is used for pointing to the return address newly stored to the return address stack; if yes, the positions pointed by a return pointer and a call pointer of the return address stack are kept, and a recursive call record table is updated, so that the number of read times of a return address pointed by the return pointer recorded in the recursive call record table is increased by 1; the recursive call record table is used for recording the number of times of reading the return instruction corresponding to each return address in the return address stack. The method can reduce the overhead of instruction processing.

An apparatus (10, 30, 50) comprising processing circuitry (51) to execute instructions, and threadlet execution circuitry (23, 49, 52) to execute tasks under control of the processing circuitry. The threadlet execution circuitry is configured to operate asynchronously with respect to the processing circuitry. The threadlet execution circuitry is responsive to a start command issued by the processing circuitry to begin execution of a threadlet comprising at least one delegated task. The processing circuitry is responsive to a threadlet-start instruction, the threadlet-start instruction indicating a request to issue the start command to the threadlet execution circuitry, to determine, in dependence on at least one parameter, whether to trigger execution, by the processing circuitry, of an alternative function instead of issuing the start command to the threadlet execution circuitry.

This invention relates to the field of data processing technology, and in particular to a method, apparatus, device, and medium for processing multi-dimensional data. The method instantiates a template based on input tensor parameters to obtain an offset calculation instance. The offset calculation instance is initialized to determine the step size and shape of each input array in each output dimension, and these are recorded in a designated storage space. The offset calculation instance is then started to perform index calculations on the step size and shape of each input array recorded in the storage space in each output dimension to obtain the offset corresponding to the output array. The data corresponding to the offset is then processed according to a set calculation rule to obtain the output result. By pre-calculating the step size and shape of each input array in each output dimension, unnecessary memory accesses can be reduced. Constructing offset calculation instances simplifies the index calculation process, enabling efficient and accurate data storage, retrieval, and calculation.

A processor and a vector sort instruction for the processor to execute are provided, in which the vector sort instructions includes instructions for comparing a first element of a set of vector elements of a vector to a remainder of the set of vector elements; determining, based on the comparing, a control vector that specifies a respective sorted position for each element of the set of vector elements; and reordering the set of vector elements based on the control vector.

Provided is a processor controlling pipeline processing to avoid the occurrence of pipeline bubbles as much as possible even when executing jump instruction. The present processor executes pipeline processing in which: an instruction fetcher fetching a machine-language instruction based on a memory address set in a program counter; a decoder decoding the machine-language instruction output from the instruction fetcher into control information; and an executer executing the control information output from the decoder, are connected, and the present processor comprises: a table describing a head address and a head machine-language instruction for each destination of jump; and a pipeline controller setting, when the executer executing a control information of a jump, an address specifying a second machine-language instruction at a destination of the jump into the program counter by using the table, while to input a head machine-language instruction at the destination of the jump to the decoder.

An instruction prediction method and apparatus, a system, and a computer-readable storage medium relate to the field of computer technologies. The method includes: a processor obtains a plurality of to-be-executed first IBs, where any first IB includes at least one instruction to be sequentially executed, and the at least one instruction includes one branch instruction; searches, based on branch instructions included in the plurality of first IBs, at least one candidate execution path for a candidate execution path corresponding to the plurality of first IBs, where any candidate execution path indicates a jump relationship between a plurality of second IBs, and a jump relationship indicated by the candidate execution path corresponding to the plurality of first IBs includes a jump relationship between the plurality of first IBs; and predicts, based on the jump relationship between the first IBs, a next instruction corresponding to a branch instruction in each first IB.