389results about "Next instruction address formation" patented technology

Techniques are described for efficient replication and maintaining snapshot data consistency during file storage replication between file systems in different cloud infrastructure regions. In certain embodiments, provenance IDs are used to efficiently identify a starting point (e.g., a base snapshot) for a cross-region replication process, conserve cloud resources while reducing network and IO traffic.

A data processing apparatus includes pointer storage configured to store pointer values for pointers. Increment circuitry, responsive to one or more increment events, increments each of the pointer values in dependence on a corresponding live pointer value update condition from corresponding live pointer value update conditions. The corresponding live pointer value update condition is different for each of the pointers. History storage circuitry stores resolved behaviours of instances of a control flow instruction, each of the resolved behaviours being associated with one of the pointers. At least one of the live pointer value update conditions is changeable at runtime. Consequently, storage can be reduced as compared to a situation where all pointer value update conditions are active.

The invention discloses an IP event counting device and method, equipment and a storage medium. Comprising an IP function module and a power management module. The IP function module comprises a counting register; the power management module comprises a counting mirror image register and a cardinal number register; the counting register is connected with the counting mirror image register through a hardware connection line; when the IP function module is powered off, the IP function module reads the first count value from the count register and reads the third count value from the cardinal number register, the first count value and the third count value are accumulated, and an accumulation result is written into the cardinal number register to serve as a new third count value; and when the IP function module is in a power-on state, the power management module reads the second count value from the counting mirror image register every set duration, accumulates the read second count value and the third count value through the adder, and determines an accumulation result as a target count value of the preset IP event. And occupation of software and hardware resources of the power management system is reduced.

The invention relates to the technical field of interrupt control, and discloses a simplified interrupt control method and device, equipment and a medium. The method comprises the following steps: judging whether an interrupt vector is enabled or not, wherein the interrupt vector comprises a plurality of ITRs; under the condition that the interrupt vector is successfully enabled, the priority of the interrupt event is obtained, the timing requirement of a first ITR is determined based on the priority, the first ITR is the ITR associated with the interrupt event, and the timing requirement is used for adjusting the bit width of the first ITR; adjusting a timer based on the timing demand of each ITR in the interrupt vector; and after timing of the timer is finished, sending the interrupt vector to the host so as to trigger the interrupt vector. According to the invention, the requirement of the interrupt vector for hardware resources can be reduced.

The invention relates to a user mode interruption processing method and device, equipment and a program product. Through the interrupt information carried by the user mode interrupt request, the operating system can quickly and accurately determine the source and the processing path of the target user mode interrupt in numerous possible interrupt situations. Meanwhile, the context switching time in the interrupt processing process can be effectively shortened by obtaining the current process and the current stack frame thereof, matching the current process and the current stack frame thereof with the target process and determining a mechanism of the target stack frame in combination with the interrupt address information, so that the context switching time in the interrupt processing process can be effectively shortened when the interrupt occurs. The target stack frame can be quickly determined to provide an accurate execution environment recovery basis for subsequent switching between the kernel mode and the user mode and execution of the interrupt service program, and the interrupt processing speed can be increased by switching the kernel mode to the user mode to run the interrupt service program of the user mode. And the overall performance and resource utilization rate of the operating system are improved.

An embodiment of an integrated circuit may comprise a return stack buffer (RSB), a speculative return stack buffer (SRSB), and circuitry coupled to the RSB and the SRSB, the circuitry to track a count until the SRSB is empty at a time of a prediction by a branch prediction unit, and return an output from the branch prediction unit that corresponds to one of the RSB and the SRSB based at least in part on the count until the SRSB is empty. Other embodiments are disclosed and claimed.

Modifications to existing computer hardware, compiler changes or source-to-source transforms performed during the software build process, and a collection of libraries and modifications to existing standard system software and libraries. The invention allows a program author to enforce various kinds of locality of causality in software to provide enforcement of boundaries for the following aspects of a computer program: control, space, time, modularity, reference, initialization, and mutability. Where these properties do not suffice to guarantee a property at static time, dynamic checks may be added and the constraints on control flow prevent such dynamic checks from being avoided by the program.

The invention provides a jump instruction jump address selection method and device, electronic equipment and a computer readable storage medium, and the method comprises the steps: generating an instruction stream, determining instruction information of a jump instruction in the instruction stream, determining a first difference value between addresses of adjacent instructions in the instruction stream, and according to the first difference value and the instruction information of the jump instruction, selecting a jump address of the jump instruction, determining candidate jump addresses of the jump instructions and constraint conditions for the jump addresses of all the jump instructions according to the instruction information of the jump instructions and the number of the instructions in the instruction stream, and when the candidate jump addresses of the jump instructions do not conform to the constraint conditions, determining a jump address range according to the first difference value, the instruction information of the jump instructions and the number of the instructions in the instruction stream, and determining a target jump address of the jump instruction from the jump address range, and performing instruction jump according to the target jump address when the jump instruction is executed. The probability that the jump instruction jumps to a reasonable range can be improved, and verification covers all modules of the processor as much as possible.

The invention provides a multi-discontinuous register reading method for improving Modbus protocol communication rate and a function code. The multi-discontinuous register reading method comprises the following steps: defining a function code 43H in a Modbus protocol; the method comprises the following steps: determining the type, address list and number of discontinuous registers to be read through a master device, assembling a request frame, and sending the request frame to a slave device; after the slave device receives the request frame, address matching and verification are carried out on the request frame, and if the address is not matched or verification fails, the frame is discarded; if the address is matched and the verification is passed, analyzing, judging whether abnormity exists or not, and executing related operation based on a judgment result; the master device receives the response frame returned by the slave device, verifies the response frame, and analyzes a data list in the response frame to obtain data of each register if the response frame passes the verification and is a normal response frame; if verification fails or the frame is responded abnormally, error processing is carried out, and the multi-discontinuous register reading method which can improve the communication rate, reduce the communication overhead and enhance the real-time performance and is high in compatibility is provided.

A differential matching prefetcher for coping with irregular memory access includes: an access index table, an access target table, a differential matching module, an index queue, an indirect memory access candidate scoreboard, an address generator, an indirect memory access relationship table, a prefetch status handling register, a repetition filter, a continuous address filter, and a range prefetch table. The differential matching prefetcher is configured to monitor events of access requests and data responses between a computing core and a first level of cache, as well as between the first level of cache and a second level of cache. The differential matching prefetcher may be applied in various general-purpose computing architectures adopting a hierarchical storage design to realize mode capture and data prefetch for irregular indirect memory access, reduce long-delay storage access overhead caused by the irregular memory access, and increase instructions per cycle (IPC) of the computing architectures.

An embodiment of an integrated circuit may comprise a processor with one or more cores and circuitry coupled to the one or more cores, the circuitry to control one or more interrupts based on an interrupt expansion data structure, and report information derived from the interrupt expansion data structure to a software interrupt handler. Other embodiments are disclosed and claimed.

The invention belongs to the technical field of integrated circuit simulation verification, particularly relates to an RISC-V simulation resource dynamic generation method and system, and solves the problems of instruction consistency and variable-length instruction truncation through a metadata double-table structure and a cross-boundary instruction splicing mechanism. Virtualized two-stage translation support and abnormal injection are realized through a recursive multiple hit detection and dynamic attribute bit modification mechanism. According to the method, complete storage is replaced with lightweight metadata, memory occupation is remarkably reduced, the problem that memory occupation is linearly increased along with time is solved, simulation efficiency and consistency are improved, and the method is suitable for full-system verification of a high-performance RISC-V processor.

A compute channel having a compute pipeline of compute stages can be configured using a configuration pipeline with a control table and a datapath table. The control table stores control entries corresponding to respective microoperations, and each control entry includes control information for the compute channel. A datapath table stores datapath configuration entries corresponding to respective microoperations, and each datapath configuration entry has a datapath configuration that includes computational circuit block configurations to configure respective computational circuit blocks in the compute pipeline of the compute channel. Control logic can issue a microoperation to the compute channel by configuring the compute channel according to the control information of the microoperation obtained from the control table, and by inputting the datapath configuration of the microoperation obtained from the datapath table into the configuration pipeline of the compute channel.

Prediction circuitry predicts a number of iterations of a fetching process to be performed to control fetching of data / instructions for processing operations that are predicted to be performed by processing circuitry. The processing circuitry can tolerate performing unnecessary iterations of the fetching process following an over-prediction of the number of iterations. In response to the processing circuitry resolving an actual number of iterations, the prediction circuitry adjusts the prediction state information used to predict the number of iterations, based on whether a first predicted number of iterations, predicted based on a first iteration prediction parameter, provides a good prediction (when the first predicted number of iterations is in a range i_cnt to i_cnt+N, where i_cnt is the actual number of iterations and N≥1), or a misprediction (when the first predicted number of iterations is outside the range i_cnt to i_cnt+N).

The invention discloses a command processing method and device, equipment and a medium, and relates to the technical field of computers, and the command processing method comprises the following steps: extracting a plurality of first logic block address ranges from a logic block address range queue; the first logic block address range is a logic block address range which needs to be accessed, and the second access logic block address range is a logic block address range which does not need to be accessed; writing a logic block initial address determined based on the first first logic block address range and the number of logic blocks corresponding to each logic block address range into a target field in a submission queue entry corresponding to the to-be-processed command; setting a target length flag value in the target field; sending a submission queue entry carrying the current target field to a controller, so that the controller determines a plurality of first logic block address ranges based on information in the current target field; and obtaining a command processing result corresponding to the to-be-processed command generated after the controller accesses the plurality of first logic block address ranges. According to the invention, the transmission efficiency is improved.

The invention is suitable for the technical field of processors, and particularly relates to a memory access dependency prediction method and system for a processor and a storage medium. The memory access dependency prediction system comprises a loading and storage dependency predictor used for predicting whether address dependency exists in a loading instruction and a storage instruction; the loading and storage dependency predictor comprises a loading instruction reordering cache, a storage instruction reordering cache, an index generator, a loading and storage dependency historical record table and a storage execution record table; the storage execution record table is used for recording a storage instruction reordering cache index value and a reordering cache age value of the storage instruction. Compared with the prior art, the method has the advantages that the address dependency prediction accuracy and efficiency of the loading instruction and the storage instruction are higher, and the performance of the processor is better.

The invention provides an intra-core instruction concurrent out-of-order execution system, method and device and a medium, and belongs to the technical field of instruction scheduling. The system comprises a thread beam scheduling module used for managing thread beam slot positions and switching calculation core tasks through a program counter; the instruction fetch module is used for reading the instruction from the L1 cache to the intra-core cache; the instruction decoding module is used for decoding the instruction into register information and then sending the register information to the decoding identification module; the decoding identification module is used for dividing the instructions into five types, namely jump, memory access, barrier, dependency and disorder, generating identification instructions and storing the identification instructions into corresponding cache groups of the transmitting cache module; the operand collection module is used for reading data from the register according to the instruction; the calculation execution module comprises a shaping unit, a floating point unit, a special function unit and a memory access unit and synchronously executes various calculation tasks; and the result write-back module is used for writing the result data back to the operand collection module. According to the method, concurrent out-of-order execution of the instructions is realized, and the calculation efficiency and the resource utilization rate are improved.

A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.

The invention relates to the field of chip design, in particular to an instruction generation method, electronic equipment and a storage medium. The instruction generator generates a plurality of instructions com according to the instruction description file ISA; acquiring an instruction data conflict scene list, searching for the instruction data conflict scene list when instruction data conflict exists between the current instruction and the previous instruction, and when the current instruction meets constraint conditions of the current instruction in the kth conflict processing entry hazk in the instruction data conflict scene list, performing instruction data conflict processing on the kth conflict processing entry hazk in the instruction data conflict scene list; and when the current instruction meets the constraint condition prk of the previous instruction of the hazk and the previous instruction meets the constraint condition prk of the previous instruction of the hazk, adding the current instruction into the instruction stream after the clock cycle number specified by the previous instruction is later than the clock cycle number specified by the previous instruction according to the hazk. The method does not depend on the completeness degree of a compiler, the problem of instruction data conflict is not needed to be solved through the compiler in the middle and later periods of a project, and the verification time duration is shortened.

The invention provides a cyclic branch prediction instruction fetching device, a processor and electronic equipment. A reference unit generates a reference address according to acquired address data; the instruction storage unit reads a historical reference address to pre-fetch an instruction, and when the instruction storage unit is hit, after K clock cycles, a target instruction corresponding to the historical reference address is transmitted to the first branch predictor; the first branch predictor is used for reading a historical reference address, performing address prediction according to the historical reference address and a target instruction corresponding to the historical reference address, and providing a predicted address to the reference unit; and the second branch predictor is used for reading the historical reference address, and providing the stored cycle start address to the reference unit under the condition that the historical reference address is the same as the cycle end address stored in the historical reference address and the number of to-be-cycled times is greater than 0. The instructions are reduced to maintain cyclic variables and judgment conditions, so that the complexity and maintenance difficulty of codes can be reduced, the acquisition efficiency of the instructions is improved, and the performance potential of a processor is fully exerted.

The invention discloses an instruction scheduling system and method and electronic equipment, and relates to the technical field of computers, a dispatch module writes a to-be-scheduled instruction and a renamed register index combination into a dispatch queue, and a dependency check module constructs a dependency linked list according to the dispatch queue so as to determine an instruction execution sequence and send the instruction according to the instruction execution sequence; according to the method, the sending sequence and the execution sequence of the instruction with RAW dependency are ensured to be matched, so that the technical problems of low RAW dependency processing efficiency, long instruction waiting time and waste of pipeline instruction storage resources in the instruction scheduling of the superscale out-of-order processor can be solved, and the execution delay of the instruction is reduced.

The embodiment of the invention provides a binary translation method and device, electronic equipment and a readable storage medium, in the process of performing binary translation on a binary file of a source platform, if a current instruction is a memory access instruction, based on corresponding target address information after performing binary translation on the current instruction, the memory access instruction is accessed to the source platform; determining a target access address corresponding to the target platform; based on the target memory access address, generating a binary translated target check instruction corresponding to the current instruction; executing the target checking instruction to perform address checking on the target memory access address, and executing a target memory access operation corresponding to the current instruction under the condition that the target memory access address does not belong to a preset address constraint range; the preset address constraint range comprises a memory area which does not allow the target check instruction to access in the target platform. On the premise of ensuring the binary translation performance, the security of the binary translation process and the security and isolation of the resource data in the target platform are improved.

A verified stack trace can be generated by utilizing information contained in a shadow stack, such as a hardware protected duplicate stack implemented for malware prevention and computer security. The shadow stack contains return addresses which are obtainable without requiring an unwinding of the traditional call stack. As such, triaging based on return address information can be performed more quickly and more efficiently, and with a reduced utilization of processing resources. Additionally, the generation of a verified stack trace can be performed, with such a verified stack trace containing return addresses that are known to be correct and not corrupted. The return addresses can either be read from the traditional call stack, or derived therefrom, and then verified by comparison to corresponding return addresses from the shadow stack, or they can be read directly from the shadow stack.

An analysis function providing method executed by an analysis function providing device includes first analyzing a virtual machine of a script engine and acquiring a virtual program counter that is a variable indicating an instruction of the virtual machine to be executed next and a conditional branch flag that is an area for holding a flag as to whether or not branch is made at a time of conditional branch in an execution state, and providing an analysis function to the script engine by applying a hook including processing of detecting an instruction sequence a number of times of repeated execution of which is greater than or equal to a threshold and stopping execution of the instruction sequence by rewriting a condition related to a conditional branch at an end of the instruction sequence on a basis of the virtual program counter and the conditional branch flag.

A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), a fusion engine. An ME holds MOPs into which architectural instructions of one or more FBlks are decoded. The PRU detects a loop body ME within the program instruction stream, accumulates loop iteration count information about a series of instances of a loop on the loop body ME in the program instruction stream, updates a consistency counter of the loop body ME while accumulating the loop iteration count information, and in response to detecting that the consistency counter has reached a threshold, instructs the fusion engine to use F copies of the MOPs of the loop body ME to build in the MOC an unrolled loop multi-FBlk ME; F is a loop unroll factor that is at least two.

According to the SIMT architecture branch processing system and method based on the structured nodes, explicit node marks are inserted into branch codes through a compiler, accurate control over active masks of all threads in the program execution process is achieved, and part of branch codes, not needing to be executed currently, of the threads are shielded; a full-branch consistent detection unit is designed to judge three mask states of'all true / all false / divergence 'of current active masks of the same group of threads, so that the operation of instructions of irrelevant branches is directly skipped under a full-branch consistent scene (all true / all false), all instructions of all branches are normally executed under a divergence scene, and all the instructions of all the branches are normally executed under the divergence scene. The active masks control which instructions are executed by each thread, and the state of the active mask of each thread is accurately controlled through node marks.

Disclosed in the present application is a tensor processing unit. The tensor processing unit comprises: an instruction sequence module, which is configured to generate a first instruction sequence and / or a second instruction sequence on the basis of a tensor operation instruction and preset configuration information, wherein the first instruction sequence comprises a plurality of first operation instructions, the second instruction sequence comprises a plurality of second operation instructions, and the preset configuration information comprises first configuration information and / or second configuration information; a data loading module, which is configured to sequentially load, on the basis of the first instruction sequence or the second instruction sequence, into corresponding registers data to be operated; a first computing module, which is configured to sequentially read, on the basis of the first instruction sequence, data from the registers, so as to perform in-memory computing; and a second computing module, which is configured to sequentially read, on the basis of the second instruction sequence, data from the registers, so as to perform non-in-memory computing. Further provided in the present application is a tensor processing method. A unified macro instruction is used to call different computing modules for in-memory computing or non-in-memory computing, thereby reducing the programming complexity and improving the computing efficiency.

Modifications to existing computer hardware, compiler changes or source-to-source transforms performed during the software build process, and a collection of libraries and modifications to existing standard system software and libraries. The invention allows a program author to enforce various kinds of locality of causality in software to provide enforcement of boundaries for the following aspects of a computer program: control, space, time, modularity, reference, initialization, and mutability. Where these properties do not suffice to guarantee a property at static time, dynamic checks may be added and the constraints on control flow prevent such dynamic checks from being avoided by the program.

The embodiment of the invention provides an instruction obtaining method, a processor, a system on chip and computing equipment, the instruction obtaining method is applied to an instruction fetching unit of the processor, the processor further comprises a cache unit, a tight coupling storage unit and a program counter, and the instruction obtaining method comprises the steps that branch prediction information for a current jump instruction is received; based on the branch prediction information, determining a current storage unit where the current jump instruction is located from a cache unit and a tight coupling storage unit; based on the offset of the current program count value recorded by the program counter, the current jump instruction is taken out from the current storage unit, so that the time sequence pressure is reduced, the dominant frequency of the processor is improved, and meanwhile, the additional dynamic power consumption caused by simultaneously acquiring the jump instruction by double branches is effectively avoided; according to the method, the performance and the product endurance of the processor in processing discontinuous instructions are improved, more efficient and energy-saving instruction acquisition is realized on the premise of not sacrificing the processing speed, and the method is suitable for application scenes with higher requirements on the real-time performance and the product endurance.

The invention relates to an IR voltage drop method and device of a control chip, a storage medium and a program product. The method comprises the steps of determining predicted power of a chip according to information of a to-be-executed instruction of the chip; determining a current-resistance IR voltage drop prediction value of the chip according to the prediction power; according to the IR voltage drop prediction value and the maximum instantaneous allowable voltage drop, determining an IR voltage drop exceeding prediction quantity of the chip; and performing power control on the chip according to the IR voltage drop standard exceeding predictive quantity. The power change of the chip is pre-judged in advance through instruction level analysis instead of passively responding to voltage fluctuation, an optimized power control strategy can be generated in advance, the working state of the chip is actively adjusted before the IR voltage drop is caused by current abrupt change, and therefore the IR voltage drop can be dynamically restrained on the premise that hardware design is not changed, and the reliability of the chip is improved. And the performance loss caused by the IR voltage drop is further reduced.