13 results about "Free list" patented technology

The invention provides a memory block management method and a controller. The method comprises the following steps: acquiring a configuration file in a Linux kernel, analyzing the configuration file to obtain a memory size interval, determining a use state of a memory block in the memory size interval, and setting a bit flag of the use state in a flag bit corresponding to each memory block; whether the memory size of a target memory block of the current allocation request is in a memory size interval or not is judged, if yes, whether a first idle linked list in the SLUB allocator is empty or not is judged, and the first idle linked list is used for storing the flag bit of the memory block with the bit marked as idle; and if not, sequentially selecting a flag bit of a target memory block of a linked list from a first idle linked list of the SLUB allocator, and determining the target memory block for the current allocation request according to the flag bit of the target memory block. According to the method and the device, the problems of too high memory block metadata occupation and low allocation efficiency in the SLUB allocator can be solved.

The invention relates to the field of memory management, in particular to a concurrent management method of a multi-thread memory pool. A plurality of independent memory pools are maintained, each memory pool corresponds to a preset memory block size, an idle linked list composed of idle memory blocks is maintained in each memory pool, and each idle linked list is provided with a head pointer used for memory block allocation and capacity expansion and a tail pointer used for memory block recovery. Memory block allocation is realized only by operating a head pointer from the head of an idle linked list, and memory block recovery is realized only by inserting the tail of the idle linked list, so that memory block allocation and recovery operations are executed concurrently under a lock-free condition; and setting a first mutual exclusion lock and a second mutual exclusion lock which are separated for each memory pool, wherein the first mutual exclusion lock and the second mutual exclusion lock respectively protect concurrent modification of the head pointer and the tail pointer. The method is simple in structure and low in cost, the number of times of lock competition and the memory fragmentation rate are remarkably reduced, and the memory allocation efficiency and the system throughput under the multi-thread environment are improved.

The application discloses a front-end code-free database table generation method and relates to the technical field of data processing. The method comprises the following steps: S1, data writing; S2, database table generation; S3, front-end code processing; S4, code association establishment; and S5, database table updating and maintenance. The method classifies the written data, integrates the classified data, forms free tables, adds the free tables to a database, converts the free tables into database tables through a database system, sequentially performs modularization processing and set processing on the front-end codes of the data in the database tables, removes the front-end codes of all the data in the database tables through code association, forms the front-end code-free database tables, and improves the database table generation method. The data in the database tables generated by the improved database table generation method is free of front-end codes, the database table content is convenient to retrieve and update, the front-end code redundancy in the database is avoided, and the code reusability is improved.

Consistent with the present disclosure, a switch is provided that has a memory which temporarily stores packets to be selectively directed toward one or more destination egress ports. A method and apparatus are disclosed for efficiently managing the memory to support high data rate throughput by parallel processing and distributing memory management tasks across multiple packet buffer manager circuits. In one example, the apparatus includes a memory system divided into portions, with each portion managed by individual packet buffer managers operating in parallel. The packet buffer managers maintain a first plurality of memory addresses as a dedicated free list for storing incoming packets. As the free list of a particular packet buffer manager drops below a certain threshold, a weighted randomizer circuit adjusts the allocation of memory addresses among other packet buffer managers based calculated weights, which are inversely related to the number of memory addresses available to receive packets.

Embodiments of the present application provide a shared memory pool management method, device, equipment, medium and program product, the method comprising: when initializing the shared memory pool, establishing an empty free list for each unit pool; when receiving a memory application request of a service module, determining a target memory pool block from the shared memory pool; if the free list of the target unit pool is not empty, selecting a memory block from the free list of the target unit pool and allocating the memory block to the service module, otherwise allocating a memory block from the unused memory of the target unit pool; when the service module releases a used memory block, adding the released memory block to the corresponding free list. The method establishes an empty free list during initialization, avoids allocating physical memory for the memory block during initialization, and allocates physical memory only when the memory block is called, and preferentially allocates the used free memory block in the free list, thereby improving the use efficiency of the physical memory.

This application provides a return address prediction stack management method, apparatus, device, and program product. The method mainly manages the free status of each entry in the physical storage space by providing a free list, and updates the status of the corresponding entry to free when the return instruction retires, thereby realizing the accurate release and dynamic reclamation of prediction stack entries, thus avoiding the loss of effective information due to sequential overwriting and improving the utilization rate of return address prediction stack entries.

Disclosed herein are a garbage collection method and apparatus. The garbage collection method includes when an area dynamically allocated through a malloc( ) function or a new operator of a standard C library is deallocated through a free( ) function or a delete operator, inserting the deallocated area into a quarantine list, recording a base address and an end address of each of areas inserted into the quarantine list in a CSR_quarantined_chunks register, finding a physical address of a memory page used by a processor and searching data in the memory page for a value included in a quarantined area of the CSR_quarantined_chunks register, when a value included in the quarantined area is not present, setting a state flag bit of the register to 0, and deleting an area which the state flag bit is 0 from the quarantine list, and inserting the area into a free list.

Systems and methods include storage of a plurality of encrypted data pages of a row store database table in a persistent storage system, determination of a first encryption key associated with one of the plurality of encrypted data pages based on a header of the one of the plurality of encrypted data pages, determination of whether the first encryption key has been revoked, and, if it is determined that the first encryption key has been revoked, adding of a portion of volatile memory allocated to the one of the plurality of data pages to a free list.

The application discloses a core-to-core communication method of a multi-core processor and electronic equipment. The communication method is configured in each core and comprises the following steps: a sending side sends buffer application information to apply for a buffer from a buffer free list; it is judged whether the buffer free list is empty; if yes, available indexes in a recycling ring queue are used as first index values; if not, a head index of the buffer free list is obtained as the first index value; the first index value is written into a sending ring queue and the write index thereof is updated, and a core-to-core interrupt or a mailbox is triggered to inform a receiving side; so that the receiving side reads the first index value through the sending ring queue, writes the first index value into a recycling ring queue and updates the write index of the recycling ring queue after corresponding data processing. Through independent operation of the two ring queues by the sending side and the receiving side, communication data is transmitted based on the index value, zero-copy transmission is realized, and the data transmission efficiency is improved.

A processing system includes a host processor and a co-processor. The host processor can be coupled to a memory subsystem having at least one memory and operates to execute system software that employs memory address translations based on one or more page tables stored in the memory subsystem. The co-processor likewise can be coupled to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to perform one or more page management operations on behalf of the system software based on the iterations of the page table walk. The page management operations performed by the co-processor include analysis data aggregation, free list management, and page allocation, page migration management, page table error detection, etc.

The embodiment of the invention provides an SSD cache space management method and device, electronic equipment and a storage medium. According to the method and the device, the multi-level FREE LIST is constructed and the SSD cache space is managed in a level-to-level manner according to the UNIT group size, so that the first node on the first FREE LIST of which the matched UNIT group size is greater than and closest to the size of the data to be written is allocated to the write request, and the single write request is ensured to be stored on the continuous UNIT as far as possible; multiple split writing caused by discrete UNIT distribution in the prior art is avoided, and the number of times of writing is prevented from being increased as much as possible. Besides, after data writing succeeds, the remaining N idle UNITs are finely split and sunk into at least one target FREE LIST lower than the first level, it is ensured that the system can still keep ordered management of UNIT groups of different sizes after long-term operation, the defect that in the related technology, the UNIT sequence is disordered along with the increase of operation time of the FREE LIST is overcome, split writing is reduced, and the reliability of the system is improved. Write-in frequency amplification is reduced, and system performance is improved.

This application discloses a memory manager power-off recovery method and electronic device, relating to the computer field. It achieves exclusive access to memory resources by initiating the process with a persistent trigger signal and combining it with a global mutex lock, ensuring the consistency of core data acquisition. The acquired data is structured and written to a dump file to construct a verifiable persistent carrier. During power-off recovery, the verification results of the dump file are used as a prerequisite to extract data and complete state reconstruction. This solves the technical problems of traditional power-off recovery, such as memory data acquisition being susceptible to concurrent interference, insufficient reliability of dump data, and low accuracy of the recovery process. It provides a structured, highly reliable persistent data source for memory manager power-off recovery, achieving accurate reconstruction of virtual memory regions, free lists, and allocated physical pages, ensuring the integrity of memory data and the normal operation of the memory manager after a power outage.

Memory free list latency bounding techniques may optimize the performance of parallel storage devices. In one example, a memory controller includes one or more registers that include pointers to free lists that include addresses of free locations in the memory devices. In various example, each free list corresponds to a memory device, memory module, or pseudo channel. The memory controller receives data to store in memory. The memory controller splits the data into data chunks, where a data chunk has a size that is greater than a memory access size. The memory controller then determines which free lists include addresses to free locations and selects one or more memory devices to store the data chunks based on the free lists. In one example, at least one of the memory devices is selected to store data chunks based on how recently the memory device was selected.