26 results about "Free list" patented technology

The invention provides a memory block management method and a controller. The method comprises the following steps: acquiring a configuration file in a Linux kernel, analyzing the configuration file to obtain a memory size interval, determining a use state of a memory block in the memory size interval, and setting a bit flag of the use state in a flag bit corresponding to each memory block; whether the memory size of a target memory block of the current allocation request is in a memory size interval or not is judged, if yes, whether a first idle linked list in the SLUB allocator is empty or not is judged, and the first idle linked list is used for storing the flag bit of the memory block with the bit marked as idle; and if not, sequentially selecting a flag bit of a target memory block of a linked list from a first idle linked list of the SLUB allocator, and determining the target memory block for the current allocation request according to the flag bit of the target memory block. According to the method and the device, the problems of too high memory block metadata occupation and low allocation efficiency in the SLUB allocator can be solved.

The invention provides a memory management method and device, a storage medium and an electronic device.The method comprises the steps that a heap memory of a process is applied from a system memory, and the process comprises a plurality of threads; aiming at a first thread of the process, the heap memory is adopted to construct a first local free table of the first thread, and the first local free table is used for locally storing an object pool of the first thread by adopting a thread local storage structure; and in response to a memory allocation request, allocating a first object for the first thread from the first local free table. Through the embodiment of the invention, the technical problem that memory fragments occur in dynamic memory allocation in related technologies is solved, and the memory management efficiency and performance are improved.

Systems and methods for an eBPF general allocator for an eBPF program is provided. The method includes receiving, by a first eBPF program, a first entry based on an atomic operation. The first entry is from a number of entries in a free list that indicates available space in a buffer. The available space is indexed by the number of entries in the free list. The method further includes identifying, based on the first entry, a pointer to the buffer. The pointer is associated with an allocation of the available space in the buffer based on the first entry. The allocation of the available space is to the first eBPF program. The method further includes executing, by a processing device, the first eBPF program with exclusive access to the allocation of the available space in the buffer during an execution instance of the first eBPF program.

A computer program product, system, and computer implemented method for fast reuse of locking data structures prior movement of entries to a cache free list. The approach disclosed herein enables management of lock management structures. Specifically, the approaches provided herein are directed towards use of lock management structures where items are managed using at least a recycle list. A recycle list and a resource list pair associated with the recycle list are controlled using a single latch, where there are any number of buckets that each include a recycle list and a resource list pair. In addition, in some embodiments, a free list is also maintained, whereas resource lists and recycle lists have a one-to-one relationship with each other, the free list has a one-to-many relationship with the buckets and lists therein.

This invention relates to a lock-free update method for conflict detection rules in network security access control policies, belonging to the field of network security technology. This invention can reclaim memory promptly while minimizing read thread latency, without requiring a dedicated write thread reclamation phase or a dedicated garbage collection thread. By pre-allocating a cache block in memory and defining it as a space table structure, this invention avoids the overhead of frequent memory allocation and release, allocating memory in a general available space table, the free list. Unused memory blocks can be used directly. If a cache block is fully occupied by threads, it is then allocated from the system. After use, the memory block is not directly released but instead stored in the free list. This invention aims to achieve a fast, secure, and stable access control rule update algorithm through a lock-free mechanism, avoiding the inefficiencies and significant concurrency impacts associated with using locks.

The invention relates to the field of memory management, in particular to a concurrent management method of a multi-thread memory pool. A plurality of independent memory pools are maintained, each memory pool corresponds to a preset memory block size, an idle linked list composed of idle memory blocks is maintained in each memory pool, and each idle linked list is provided with a head pointer used for memory block allocation and capacity expansion and a tail pointer used for memory block recovery. Memory block allocation is realized only by operating a head pointer from the head of an idle linked list, and memory block recovery is realized only by inserting the tail of the idle linked list, so that memory block allocation and recovery operations are executed concurrently under a lock-free condition; and setting a first mutual exclusion lock and a second mutual exclusion lock which are separated for each memory pool, wherein the first mutual exclusion lock and the second mutual exclusion lock respectively protect concurrent modification of the head pointer and the tail pointer. The method is simple in structure and low in cost, the number of times of lock competition and the memory fragmentation rate are remarkably reduced, and the memory allocation efficiency and the system throughput under the multi-thread environment are improved.

The application discloses a front-end code-free database table generation method and relates to the technical field of data processing. The method comprises the following steps: S1, data writing; S2, database table generation; S3, front-end code processing; S4, code association establishment; and S5, database table updating and maintenance. The method classifies the written data, integrates the classified data, forms free tables, adds the free tables to a database, converts the free tables into database tables through a database system, sequentially performs modularization processing and set processing on the front-end codes of the data in the database tables, removes the front-end codes of all the data in the database tables through code association, forms the front-end code-free database tables, and improves the database table generation method. The data in the database tables generated by the improved database table generation method is free of front-end codes, the database table content is convenient to retrieve and update, the front-end code redundancy in the database is avoided, and the code reusability is improved.

Consistent with the present disclosure, a switch is provided that has a memory which temporarily stores packets to be selectively directed toward one or more destination egress ports. A method and apparatus are disclosed for efficiently managing the memory to support high data rate throughput by parallel processing and distributing memory management tasks across multiple packet buffer manager circuits. In one example, the apparatus includes a memory system divided into portions, with each portion managed by individual packet buffer managers operating in parallel. The packet buffer managers maintain a first plurality of memory addresses as a dedicated free list for storing incoming packets. As the free list of a particular packet buffer manager drops below a certain threshold, a weighted randomizer circuit adjusts the allocation of memory addresses among other packet buffer managers based calculated weights, which are inversely related to the number of memory addresses available to receive packets.

Embodiments of the present application provide a shared memory pool management method, device, equipment, medium and program product, the method comprising: when initializing the shared memory pool, establishing an empty free list for each unit pool; when receiving a memory application request of a service module, determining a target memory pool block from the shared memory pool; if the free list of the target unit pool is not empty, selecting a memory block from the free list of the target unit pool and allocating the memory block to the service module, otherwise allocating a memory block from the unused memory of the target unit pool; when the service module releases a used memory block, adding the released memory block to the corresponding free list. The method establishes an empty free list during initialization, avoids allocating physical memory for the memory block during initialization, and allocates physical memory only when the memory block is called, and preferentially allocates the used free memory block in the free list, thereby improving the use efficiency of the physical memory.

This application provides a return address prediction stack management method, apparatus, device, and program product. The method mainly manages the free status of each entry in the physical storage space by providing a free list, and updates the status of the corresponding entry to free when the return instruction retires, thereby realizing the accurate release and dynamic reclamation of prediction stack entries, thus avoiding the loss of effective information due to sequential overwriting and improving the utilization rate of return address prediction stack entries.

The invention relates to a method for storing data (114, 115, 116) in a data storage device (104), wherein the method comprises:receiving (202) raw data (112) or access addresses for the raw data by a data processing and search system—DPS system (102);parsing (204) the raw data by a plurality of different parsers in order to ascertain data objects each having one or more data values, and an object ID of each of the data objects, wherein one semantic concept is assigned to each of at least some of the data values;automatically importing (206) the parsing results by the DPS system;automatically storing (208) all of the parsing results in the form of redundancy-free data value lists (114, 115, 116) in the data storage device by the DPS system, wherein the redundancy-free lists comprise:one or more concept lists (116), wherein each of the concept lists represents a particular semantic concept, and a non-redundant list selectively includes those of the imported data values to which the semantic concept of this concept list was assigned during parsing;a concept-free list (115), wherein the concept-free list selectively includes those of the imported data values to which no semantic concept was assigned during parsing; andproviding (210) the redundancy-free lists (114, 115, 116) by the DPS system in order to respond to a search request and / or to perform a data analysis.

A processing system includes a primary processor and a co-processor. The primary processor is couplable to a memory subsystem having at least one memory and operating to execute system software employing memory address translations based on one or more page tables stored in the memory subsystem. The co-processor is likewise couplable to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to perform one or more page management operations on behalf of the system software based the iterations of the page table walk. The page management operations performed by the co-processor include analytic data aggregation, free list management and page allocation, page migration management, page table error detection, and the like.

Techniques for lazy compression are disclosed, including: selecting, by a garbage collector, a plurality of regions of memory to be included in a relocation set; populating, by the garbage collector, a lazy-free list (LFL) with the plurality of regions selected to be included in the relocation set; after filling the LFL: determining, by the allocator, that a common free list managed by the garbage collector has been depleted; in response to determining that the normal idle list is depleted: selecting a region in the LFL; executing one or more loading barriers respectively associated with the one or more objects marked as live in the region, each respective loading barrier configured to relocate an associated object from the region if the associated object remains live; after executing the one or more loading barriers: assigning the region.

Disclosed herein are a garbage collection method and apparatus. The garbage collection method includes when an area dynamically allocated through a malloc( ) function or a new operator of a standard C library is deallocated through a free( ) function or a delete operator, inserting the deallocated area into a quarantine list, recording a base address and an end address of each of areas inserted into the quarantine list in a CSR_quarantined_chunks register, finding a physical address of a memory page used by a processor and searching data in the memory page for a value included in a quarantined area of the CSR_quarantined_chunks register, when a value included in the quarantined area is not present, setting a state flag bit of the register to 0, and deleting an area which the state flag bit is 0 from the quarantine list, and inserting the area into a free list.

Apparatuses, systems, and techniques for dynamic memory allocation using a shared free list. A user tag is received, and a hashed user tag is generated. A first reference to an entry in a second data structure is identified in a first data structure using the hashed user tag. The entry includes multiple user tags. Responsive to determining that the multiple user tags do not include the user tag, a memory address is identified in a third data structure. The memory address is removed from the third data structure. Memory is allocated for a user context associated with the user tag at the memory address. The user tag is added to the second data structure.

A system includes a memory device and a command manager configured to reorder read requests. The command manager is configured to receive a read response associated with a transaction identifier for the read request. A free list entry for the read request is allocated from a free list. The free list entry is associated with a transaction identifier of the read request. A tail index of a reordering queue is written to a remapping queue based on the free list entry. The tail index is configured to provide a write address of the reordering queue that is allocated for the read request. A read response associated with the transaction identifier for the read request is received. The read response is written to the allocated entry of the reordering queue.

The invention provides a memory allocation method and device for a many-core processor and electronic equipment, and the method comprises the steps: obtaining a plurality of memory allocation requests sent by a plurality of application programs, and determining a plurality of idle lists corresponding to a plurality of Banks of the many-core processor; matching the plurality of memory allocation requests with a plurality of Banks, and determining a plurality of target idle lists from a plurality of idle lists according to a matching result; performing feature extraction on the plurality of memory allocation requests to obtain feature vectors of the plurality of memory allocation requests, and performing feature extraction on the plurality of target idle lists to obtain feature vectors of the plurality of target idle lists; and inputting the feature vectors of the plurality of memory allocation requests and the feature vectors of the plurality of target idle lists into a pre-constructed memory allocation model to obtain a memory allocation strategy. According to the method, the multiple Banks are combined with the idle list, and the memory allocation strategy is predicted by adopting the memory allocation model, so that the memory allocation efficiency of the many-core processor is improved.

Systems and methods include storage of a plurality of encrypted data pages of a row store database table in a persistent storage system, determination of a first encryption key associated with one of the plurality of encrypted data pages based on a header of the one of the plurality of encrypted data pages, determination of whether the first encryption key has been revoked, and, if it is determined that the first encryption key has been revoked, adding of a portion of volatile memory allocated to the one of the plurality of data pages to a free list.

The invention relates to a conflict detection rule lock-free updating method for a network security access control strategy, and belongs to the technical field of network security. According to the method, the memory can be recycled in time under the condition that the lowest delay of the read thread is guaranteed to the greatest extent, and a special write thread recycling stage or a special garbage recycling thread is not needed. According to the method, the cache block is applied in the memory in advance and is defined as the structure of the space table, so that the overhead of the system caused by frequent application and release of the memory can be avoided, and the memory can be allocated in a universal available space table free list. The memory blocks which are not used can be directly used, if the cache blocks are all occupied by the threads, distribution is applied from a system, and the memory blocks are not directly released after being used and are stored by a free list. According to the method, a quick, safe and stable access control rule updating algorithm is realized through a lock-free mechanism, and the problems of low efficiency and large influence on concurrency under the condition of using a lock are avoided.

A computer program product, system, and computer implemented method for fast reuse of locking data structures prior movement of entries to a cache free list. The approach disclosed herein enables management of lock management structures. Specifically, the approaches provided herein are directed towards use of lock management structures where items are managed using at least a recycle list. A recycle list and a resource list pair associated with the recycle list are controlled using a single latch, where there are any number of buckets that each include a recycle list and a resource list pair. In addition, in some embodiments, a free list is also maintained, whereas resource lists and recycle lists have a one-to-one relationship with each other, the free list has a one-to-many relationship with the buckets and lists therein.

The application discloses a core-to-core communication method of a multi-core processor and electronic equipment. The communication method is configured in each core and comprises the following steps: a sending side sends buffer application information to apply for a buffer from a buffer free list; it is judged whether the buffer free list is empty; if yes, available indexes in a recycling ring queue are used as first index values; if not, a head index of the buffer free list is obtained as the first index value; the first index value is written into a sending ring queue and the write index thereof is updated, and a core-to-core interrupt or a mailbox is triggered to inform a receiving side; so that the receiving side reads the first index value through the sending ring queue, writes the first index value into a recycling ring queue and updates the write index of the recycling ring queue after corresponding data processing. Through independent operation of the two ring queues by the sending side and the receiving side, communication data is transmitted based on the index value, zero-copy transmission is realized, and the data transmission efficiency is improved.

A processing system includes a host processor and a co-processor. The host processor can be coupled to a memory subsystem having at least one memory and operates to execute system software that employs memory address translations based on one or more page tables stored in the memory subsystem. The co-processor likewise can be coupled to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to perform one or more page management operations on behalf of the system software based on the iterations of the page table walk. The page management operations performed by the co-processor include analysis data aggregation, free list management, and page allocation, page migration management, page table error detection, etc.

The embodiment of the invention provides an SSD cache space management method and device, electronic equipment and a storage medium. According to the method and the device, the multi-level FREE LIST is constructed and the SSD cache space is managed in a level-to-level manner according to the UNIT group size, so that the first node on the first FREE LIST of which the matched UNIT group size is greater than and closest to the size of the data to be written is allocated to the write request, and the single write request is ensured to be stored on the continuous UNIT as far as possible; multiple split writing caused by discrete UNIT distribution in the prior art is avoided, and the number of times of writing is prevented from being increased as much as possible. Besides, after data writing succeeds, the remaining N idle UNITs are finely split and sunk into at least one target FREE LIST lower than the first level, it is ensured that the system can still keep ordered management of UNIT groups of different sizes after long-term operation, the defect that in the related technology, the UNIT sequence is disordered along with the increase of operation time of the FREE LIST is overcome, split writing is reduced, and the reliability of the system is improved. Write-in frequency amplification is reduced, and system performance is improved.

The present application discloses a method, device, and related products for processing task mutual exclusion in a heterogeneous network. The method comprises: obtaining multiple requests for accessing a shared storage resource; determining a free list and an allocated list of the shared storage resource, wherein the free list includes unallocated shared storage resources, and the allocated list includes releasable shared storage resources; matching shared storage resources in the free list and the allocated list of the shared storage resource to respond to the multiple requests for accessing the shared storage resource, thereby avoiding conflicts between the requests and effectively achieving effective response to the requests.

This application discloses a memory manager power-off recovery method and electronic device, relating to the computer field. It achieves exclusive access to memory resources by initiating the process with a persistent trigger signal and combining it with a global mutex lock, ensuring the consistency of core data acquisition. The acquired data is structured and written to a dump file to construct a verifiable persistent carrier. During power-off recovery, the verification results of the dump file are used as a prerequisite to extract data and complete state reconstruction. This solves the technical problems of traditional power-off recovery, such as memory data acquisition being susceptible to concurrent interference, insufficient reliability of dump data, and low accuracy of the recovery process. It provides a structured, highly reliable persistent data source for memory manager power-off recovery, achieving accurate reconstruction of virtual memory regions, free lists, and allocated physical pages, ensuring the integrity of memory data and the normal operation of the memory manager after a power outage.

Memory free list latency bounding techniques may optimize the performance of parallel storage devices. In one example, a memory controller includes one or more registers that include pointers to free lists that include addresses of free locations in the memory devices. In various example, each free list corresponds to a memory device, memory module, or pseudo channel. The memory controller receives data to store in memory. The memory controller splits the data into data chunks, where a data chunk has a size that is greater than a memory access size. The memory controller then determines which free lists include addresses to free locations and selects one or more memory devices to store the data chunks based on the free lists. In one example, at least one of the memory devices is selected to store data chunks based on how recently the memory device was selected.