17 results about "Longest prefix match" patented technology

The invention discloses a large language model reasoning acceleration method and device based on two-stage speculative decoding and a storage medium, and the method comprises the steps: constructing and initializing a Trie tree, and inserting a historical corpus, and phrase sequences in a document library or a code library into the Trie tree one by one; in the reasoning process, longest prefix matching is carried out based on a Trie tree, and a candidate draft sequence is generated by adopting branch backtracking and recursive search; performing confidence evaluation on the candidate draft sequence, calculating a joint confidence score of the sequence through probability multiplication and a Top-K screening mechanism, and judging whether the joint confidence score reaches a confidence threshold; if the accumulated confidence of the candidate sequence reaches a threshold value, skipping a small model generation stage, and directly entering large model verification; otherwise, entering a small model draft completion stage; and the final large model takes the replaced and updated draft sequence as final output. According to the method, adaptive acceleration of the decoding process can be realized, and the long text reasoning delay of the large language model is remarkably reduced while the generation quality is ensured.

A network device uses prefix compression to program routes in a forwarding information base (FIB) in a longest prefix match (LPM) table or an exact match (EM) table. The network device compresses routes of a certain prefix length in the FIB into a single entry in the EM table. For a compressed prefix that does not correspond to a route in the FIB (hole), the network device associates the hole with a special value rather than the prefix of a covering route. When the network device receives a packet that matches a hole, the lookup performed on the exact match table results in the special value. In response, the network device uses the result of the lookup performed on the LPM table to determine how to forward the packet.

The examples described herein involve configuring a device to perform a longest prefix match (LPM) of rules associated with nodes to identify an action to be performed on a packet. The rules can be stored in a memory and a ternary content-addressable memory (TCAM) based on the available memory capacity of the TCAM.

The application discloses a prefix caching method and device suitable for a mixed attention model architecture. In view of the heterogeneous management problem of key-value caching and state snapshot, a unified prefix index mechanism based on chain hashing is proposed, so that the two types of caches share a hash space. The method determines the boundary of the two types of caches consistent and effective through the longest prefix matching and forward traversal verification, combines local snapshot query and remote confirmation, realizes the collaborative recovery and reuse of key-value caching and linear attention snapshot, and reduces the heterogeneous state step-out risk. In the reasoning process, the two types of states are captured synchronously and unified hash index is adopted, and a bidirectional mapping between cache block identification and snapshot hash is established through a double cache coordination manager; when the expulsion condition is met, the linkage cleaning of the two types of caches is realized based on the mapping. The application realizes the unified storage and life cycle collaborative management of heterogeneous caches under the mixed attention architecture, guarantees the whole process consistency, and improves the reasoning performance and system robustness.

The application discloses a longest prefix matching storage device, method and chip based on TCAM, and relates to the technical field of data communication. The device comprises a TCAM and an AD SRAM, the TCAM comprises a plurality of memory banks and is virtually divided into a non-tail sub-table and a tail sub-table; the non-tail sub-table stores non-tail sub-sections in the LPM common prefix which are not masked and need to be accurately matched with full memory bank bit width; the tail sub-table stores tail sub-sections in the LPM common prefix with masks; each non-tail sub-section of the same common prefix is stored in an independent entry; and the AD SRAM corresponding to the tail sub-section stores a non-common prefix subset pointer. The application solves the problems of TCAM resource waste and limited LPM rule storage capacity in the prior art, improves the TCAM resource utilization rate and the chip LPM capacity specification through sub-table division and sub-section sharing.

The application belongs to the technical field of Ethernet routing and discloses a TCAM-based LPM routing search device and method, which comprises a soft table recording module, a soft table sorting module and a TCAM table management module; the soft table recording module is used for maintaining the routing table information configured by a user through a soft table; the soft table is used for recording the position of the routing table information in the TCAM; the soft table sorting module is used for managing the front and back order of the routing table in the TCAM and ensuring that the routing tables with the same prefix length mask are arranged on the low address; and the TCAM table management module is used for guiding the message forwarding according to the longest prefix matching rule. The application ensures that the routing table with the longest prefix matching can be sorted in the position with high priority, and realizes the routing table search algorithm with the longest prefix matching.

The application provides a network table query method and data packet processing method of a switch and related devices. A plurality of binary classifiers are set in the on-chip memory of a switch processor. According to the output values of the exact match table, the longest prefix match table and the access control list, the pre-operation results corresponding to the output values are generated through hash operation, and the pre-operation results are pre-stored in the plurality of binary classifiers corresponding to the exact match table, the longest prefix match table and the access control list. When the network table query of the switch is performed, the plurality of binary classifiers can be used to output the output values of the switch network table in parallel based on the pre-operation results. The scheme realizes the isomorphism of the storage structures of the exact match table, the longest prefix match table and the access control list, and can dynamically allocate the storage resources of the on-chip memory when the network table query is performed, so as to adapt to the network table query in different time and different scenes.

The application discloses a longest prefix matching storage device, method and chip based on TCAM, and relates to the technical field of data communication. The device comprises a TCAM and an AD SRAM, the TCAM comprises a plurality of memory banks and is virtually divided into a non-tail sub-table and a tail sub-table; the non-tail sub-table stores non-tail sub-sections in the LPM common prefix which are not masked and need to be accurately matched with full memory bank bit width; the tail sub-table stores tail sub-sections in the LPM common prefix with masks; each non-tail sub-section of the same common prefix is stored in an independent entry; and the AD SRAM corresponding to the tail sub-section stores a non-common prefix subset pointer. The application solves the problems of TCAM resource waste and limited LPM rule storage capacity in the prior art, improves the TCAM resource utilization rate and the chip LPM capacity specification through sub-table division and sub-section sharing.

The application discloses a fast rule matching method and device for flow analysis, and the method comprises the following steps: obtaining the corresponding code of each IP network segment according to the IP network segment in the address group in the rule set; determining the code set corresponding to each IP network segment according to the mask length of the IP network segment and the containing relationship between the network segments; storing all the code sets into a memory area to obtain the mapping relationship between the IP network segment and the memory offset; constructing a longest prefix matching (LPM) table; in response to the received flow information, querying the LPM table for the source IP address and the destination IP address of the flow information respectively to obtain the memory offset; reading the memory area indicated by the memory offset to obtain the code set matched by the source IP address and the destination IP address respectively; and determining the rule in the rule set matched by the flow information according to the code set. The application can accurately classify the data packet into the corresponding rule, avoid the wrong classification of the data packet, improve the accuracy and effectiveness of the network data processing, and further improve the network management and operation efficiency.

Aspects of the present disclosure involve systems, methods, for encoding a firewall ruleset into one or more bit arrays for fast determination of processing of a received communication packet by a firewall device associated with a network. Through this bitmap, a number of computation operations needed to determine a processing rule for a received packet is significantly reduced compared to the traditional approach of using a hash or a longest prefix match technique. Rather, determining a processing rule for a received packet may include determining a bit value within one or more arrays. In one implementation, a firewall rule may be encoded into a 64-bit array of bit values in which each bit of the array corresponds to a particular processing rule for a particular network address. The firewall rule may be encoded into a bitmap array of bit values by asserting a particular bit within the array.

The application discloses a fast rule matching method and device for flow analysis, and the method comprises the following steps: obtaining the corresponding code of each IP network segment according to the IP network segment in the address group in the rule set; determining the code set corresponding to each IP network segment according to the mask length of the IP network segment and the containing relationship between the network segments; storing all the code sets into a memory area to obtain the mapping relationship between the IP network segment and the memory offset; constructing a longest prefix matching (LPM) table; in response to the received flow information, querying the LPM table for the source IP address and the destination IP address of the flow information respectively to obtain the memory offset; reading the memory area indicated by the memory offset to obtain the code set matched by the source IP address and the destination IP address respectively; and determining the rule in the rule set matched by the flow information according to the code set. The application can accurately classify the data packet into the corresponding rule, avoid the wrong classification of the data packet, improve the accuracy and effectiveness of the network data processing, and further improve the network management and operation efficiency.

The application discloses an address matching method and device, a storage medium and a program product, and belongs to the technical field of communication. In the method, the address to be matched is matched with a hash table corresponding to a first node in a binary search tree. If the address matches a target prefix mark in the hash table corresponding to the first node, heuristic information corresponding to the target prefix mark is obtained. The heuristic information refers to information associated with at least one heuristic information node. The at least one heuristic information node is a node corresponding to a hash table in which a prefix of the target prefix mark is projected. A longest prefix matched with the address is found based on the heuristic information corresponding to the target prefix mark. Since the target prefix mark corresponds to heuristic information, the search range can be reduced based on the heuristic information, and it is not necessary to traverse all nodes on a right subtree of a node corresponding to the hash table in which the target prefix mark is located. Therefore, the number of traversed nodes can be reduced, and the routing search efficiency is improved.

The invention discloses a longest prefix matching method based on an RAM and a communication chip, and belongs to the technical field of network communication, the method comprises the following steps: configuring a plurality of storage units with preset depths and widths, each storage unit comprising a plurality of storage entries, the storage entry is used for storing a step length data structure, a matching list data structure or a partial list data structure; after the routing frame containing the key value to be searched is received, searching is sequentially initiated in the storage unit from left to right; longest prefix matching is achieved by dynamically combining a step size data structure, a list data structure and a matching list data structure in a storage unit. The method can be used for remarkably reducing the circuit scale, the chip area and the manufacturing cost, and meanwhile, the power consumption is effectively controlled.

This invention discloses a prefix caching method and apparatus suitable for hybrid attention model architectures. Addressing the heterogeneous management problem of key-value caches and state snapshots, a unified prefix indexing mechanism based on chained hashing is proposed, enabling both types of caches to share a hash space. The method determines the consistent and valid boundary of both types of caches through longest prefix matching and forward traversal verification, combined with local snapshot queries and remote confirmation, achieving collaborative recovery and reuse of key-value caches and linear attention snapshots, reducing the risk of heterogeneous state synchronization failures. During inference, both types of states are captured synchronously and a unified hash index is used. A bidirectional mapping between cache block identifiers and snapshot hashes is established through a dual-cache coordinator; when eviction conditions are met, the two types of caches are cleaned up in conjunction based on the mapping. This invention achieves unified storage and collaborative lifecycle management of heterogeneous caches under a hybrid attention architecture, ensuring consistency throughout the process and improving inference performance and system robustness.

Systems and methods for coverage of network addresses in a network enables a network end point to provide communication in the network based in part on a virtual arrangement of the network that includes a root node with a root counter and includes one or more sub-nodes with respective sub-node counters, where the virtual arrangement can be used to provide at least one network address that may be associated with a representative longest prefix match (LPM) having a prefix from the root node to a representative node and using a suffix that is based in part on a node level of the representative node with respect to the root node, and where the representative node can be a lower absent sub-node relative to a subnet node in the virtual arrangement.

The embodiment of the invention provides an MAC address storage method and device, electronic equipment and a storage medium, and relates to the technical field of communication. The method comprises the following steps: receiving a to-be-stored MAC address, performing prefix comparison on the to-be-stored MAC address and each stored MAC address in a prefix table, extracting a public prefix meeting a longest prefix matching condition, if the public prefix exists, obtaining a target suffix storage block corresponding to the public prefix, storing the suffix of the MAC address into the target suffix storage block, and if the public prefix does not exist, storing the suffix of the MAC address into the target suffix storage block. And splitting the to-be-stored MAC address into a to-be-stored prefix and a to-be-stored suffix according to a preset rule, and respectively storing the to-be-stored prefix and the to-be-stored suffix into the prefix table and the suffix table. Therefore, the density and efficiency of MAC address storage can be improved, and performance reduction caused by hash conflicts is avoided.

Aspects of the present disclosure involve systems, methods, for encoding a firewall ruleset into one or more bit arrays for fast determination of processing of a received communication packet by a firewall device associated with a network. Through this bitmap, a number of computation operations needed to determine a processing rule for a received packet is significantly reduced compared to the traditional approach of using a hash or a longest prefix match technique. Rather, determining a processing rule for a received packet may include determining a bit value within one or more arrays. In one implementation, a firewall rule may be encoded into a 64-bit array of bit values in which each bit of the array corresponds to a particular processing rule for a particular network address. The firewall rule may be encoded into a bitmap array of bit values by asserting a particular bit within the array.