64 results about "Ternary content addressable memory" patented technology

The invention discloses a method, a device and equipment for realizing a large-scale hybrid strategy. The method comprises the following steps of: receiving a message and analyzing the message to extract a field representing a data stream feature; generating intermediate state information according to an entry number, a port attribute and the field obtained through analysis, and obtaining a label through table look-up operation; fields, intermediate state information and labels of the messages are combined according to strategy rules defined by different storage blocks and compared with strategy entries in the storage blocks; and implementing a corresponding processing behavior on the message according to a comparison result. According to the method, parallel searching and processing behaviors of large-scale mixed policies can be realized, the method is suitable for more than hundreds of thousands of policy routing deployment and access control lists of various matching field combinations, and high-power-consumption and high-cost TCAM (Ternary Content Addressable Memory) storage can be avoided.

The invention relates to the technical field of image processing and computer vision, in particular to a text-guided multi-view Mars topographic feature image segmentation method based on SAM, and the method comprises the steps: constructing and training an MTSNet model, inputting a to-be-segmented Mars image and a topographic prompt text into the trained MTSNet model, and obtaining a segmentation result; the MTSNet model comprises an MTG-SAM branch, an LTE (Long Term Evolution Network) branch, a feature fusion module, a text prompt encoder and a Mask Decoder; the MTG-SAM branch is formed by cascading a plurality of Transform Blocks, and a TCAM (Ternary Content Addressable Memory) module is introduced into each Transform Block; the text prompt encoder comprises a CLIP text encoder, a text affine layer and a prompt encoder; according to the method, the accuracy and convenience of terrain segmentation of the Mars image are effectively improved.

Devices, networks, systems, methods, and processes for facilitating parallel processing in ternary content addressable memory (TCAM) systems are described herein. A TCAM system including two physical TCAM blocks may detect a key-type associated with a key entry. The TCAM system can be operated in a wide search mode or a narrow search mode based on the detected key-type. In the narrow search mode, the key entry, being a narrow key, is inputted to the two physical TCAM blocks for associated data look-up. In the wide search mode, the key entry, being a wide key, is split into two segments, and one segment is inputted to one TCAM block and the other segment is inputted to the other TCAM block. The TCAM system may implement multiple logical TCAMs using the physical TCAM blocks. Thus, integrating a hybrid architecture of hardwired logic followed by programmable logic configuration, enhanced by parallel processing.

The present invention provides a TCAM unit, belonging to the field of semiconductor integrated circuit design. The TCAM unit of the present invention includes: a CMOS field-effect transistor; a complementary CMOS field-effect transistor; a diode; a complementary diode; a memory cell, whose first end is electrically connected to the drain of the CMOS field-effect transistor and the cathode of the diode and can be in a high resistance state and a low resistance state; a complementary memory cell, whose first end is electrically connected to the drain of the complementary CMOS field-effect transistor and the cathode of the complementary diode; a bit / select line, which is electrically connected to the second end of the memory cell; a complementary bit / select line, which is electrically connected to the second end of the complementary memory cell; a match line, which is electrically connected to the diode and the anode of the complementary diode; a word line, which is electrically connected to the gates of the CMOS field-effect transistor and the complementary CMOS field-effect transistor; and a ground line, which is electrically connected to the source of the CMOS field-effect transistor and the complementary CMOS field-effect transistor. The TCAM unit of the present invention has low leakage current, low power consumption in operation and standby mode, fewer connection lines, and high storage density.

Ferroelectric diodes comprising materials such as aluminum scandium nitride (AlScN) or hafnium zirconium oxide (HfZrO2) may be formed atop semiconductor structures such as CMOS wafers to create storage memory cells, search Ternary Content Addressable Memory (TCAM) cells, and / neural circuitry. The diodes are non-volatile and field programmable via pulsing to a pulse-number-dependent analog state, with high on / off and self-rectifying ratios. Cells may be formed, for example, with two diodes that are oppositely polarized, and may be achieved without transistors to form, for example, 0T-2R structures.

The invention provides a method and device for improving multi-stage TCAM verification efficiency, and the method comprises the steps: generating randomized TCAM configuration based on byte matching number constraints N1-N5 defined by a user and an effective entry number constraint M; synchronizing the configuration to a DUT and a reference model through an atomization operation; generating multi-dimensional excitation and injecting the multi-dimensional excitation into a DUT and a reference model; and performing multi-level comparison on the DUT output and the reference model result. According to the technical scheme, through dynamic configuration of the TCAM table item, constraint excitation generation and a multi-level conflict detection mechanism, the problems of low hit rate and complex collaboration in multi-level TCAM verification are effectively solved, the verification efficiency and coverage rate are remarkably improved, and the method is suitable for high-reliability verification of the TCAM module in high-complexity chip design.

The application discloses a reconfigurable ternary content addressable memory unit, the memory unit utilizes the combination of three or more than three different states of the ternary content addressable memory and applies different gate control voltages to the memory unit to realize the reconfiguration of the unit, so as to realize the switching and working of the ternary content addressable memory unit between the parallel type and the serial type. The different states of the ternary content addressable memory refer to the states of the flash memory unit whose threshold voltage is controlled to different ranges. The application combines the advantages of the parallel type content addressable memory and the serial type content addressable memory, realizes the reconfigurable content addressable memory at a low area cost, and the array composed of the reconfigurable unit not only can realize the functions of the arrays composed of the above two types, but also provides the possibility of mixing the two types in the same array.

The present invention discloses a ternary content addressable memory, which includes a search line and a match line connected to a TCAM cell; the match line is equipped with a charge sharing circuit; the charge sharing circuit includes: a metal line disposed on one side of the match line, and a charge sharing control unit for controlling the connection and disconnection between the metal line and the match line; the charge sharing control unit connects the metal line and the match line after the match line is precharged to a high level and before the search line is activated, so that charge sharing occurs between the match line and the metal line, and the voltage of the match line is reduced through charge sharing. The present invention can reduce the voltage of the match line through charge sharing before the search line is activated. After the voltage of the match line is reduced, the evaluation speed of the match line can be increased, the efficiency of the search operation can be improved, and thus the working frequency and performance of the ternary content addressable memory can be improved.

Systems and methods are provided for implementing a low power and area ternary content addressable memory (TCAM). An example of a TCAM comprises a match line, and a plurality of TCAM cells connected along the match line. Each TCAM cell stores a state of a threshold value. The TCAM cells are configured to pull down a signal over the match line in response to inequality between an input search and the threshold value. The plurality of TCAM cells comprises a number of TCAM cells that is less than the threshold value. The input values can be encoded according to a first encoding scheme and the threshold value can be encoded according to one of a second and a third encoding scheme based on an inequality check mapped to the plurality of TCAM cells.

The present disclosure provides a ternary content addressable memory, which includes a first memory unit and a second memory unit, and the second memory unit is electrically connected to the first memory unit. The first memory unit includes a control transistor and a first variable impedance passive component. One end of the first variable impedance passive component is electrically connected to the gate of the control transistor. The second memory unit includes a data transistor and a second variable impedance passive component. The data transistor is connected in series with the control transistor, and one end of the second variable impedance passive component is electrically connected to the gate of the data transistor.

The present application discloses a range information encoding and matching method and a computer storage medium. The method comprises: obtaining a new basic range, wherein the new basic range is used to decompose the range information of entries stored in a ternary content addressable memory (TCAM); performing an expansion operation on the new basic range based on pre-stored basic ranges to obtain an expansion result, wherein each pre-stored basic range has its own encoding information; and determining the encoding information corresponding to the new basic range based on the expansion result.

The application discloses a self-test structure and a self-test method of a ternary content addressable memory (TCAM), and belongs to the technical field of integrated circuit testability design. The self-test structure comprises peripheral selection logic connected to the input and output ends of the TCAM array, a control end of the peripheral selection logic being connected to a test start signal, and being used for switching the TCAM array to a test mode under the control of the test start signal; a controller electrically connected with the peripheral selection logic, the controller comprising a test vector generator and a comparator; the test vector generator is used for generating a test vector in the test mode, the test vector comprising an address signal, a data signal and a mode control signal, the test vector being loaded into the TCAM array via the peripheral selection logic; and a first input end of the comparator being connected to the output end of the TCAM array via the peripheral selection logic, and a second input end of the comparator being connected to an expected value output end of the test vector generator.

The invention discloses a routing device, a routing management method and a computer readable storage medium, and relates to the technical field of routing. The device comprises at least one processor, a ternary content addressable memory (TCAM), a result register, a decoder and a priority selector, the TCAM is divided into at least two storage partitions, and the sizes of the at least two storage partitions are adjusted according to the flow table occupancy rates of the at least two storage partitions, so that the difference value between the flow table occupancy rates of any two storage partitions is lower than a first threshold value. And after the destination IP address of the data packet is obtained, querying the plurality of storage partitions for matching, and outputting a matched flow table item through the result register, the decoder and the priority selector. Besides, the computer readable storage medium is used for storing a computer program and executing the route management method, the updating of the flow table item in the TCAM can ensure the longest prefix matching, and the route updating time delay is reduced.

The invention belongs to the technical field of digital circuit design, and particularly relates to a TCAM (ternary content addressable memory)-based quick matching search method, which comprises the following steps of: combining a block RAM (random access memory) and a distributed RAM to construct a TCAM; according to the length of the search word, dividing the search word into a plurality of search sub-words according to bits; according to the length of a search sub-word, inputting the search sub-word into a sub-block RAM or a sub-distributed RAM, processing results of a plurality of sub-RAMs, inputting the processed results into an encoder, and outputting a matching address by the encoder; and searching a corresponding operation in the RAM of the matched address and executing the operation. Compared with the prior art, the method has the advantages that the Block RAM (BRAM) and the LUTRAM in the FPGA are comprehensively utilized to optimize the method for dividing the search words, the BRAM and the LUTRAM are flexibly combined, the optimized composite TCAM (OC-TCAM) which is closer to or even fits the number of bits of the search words is achieved, and consumption of storage resources is greatly reduced.

This application relates to a dynamic scheduling method and apparatus for a three-state content-addressable memory (TRM). The method includes: acquiring operational status information corresponding to a network device, the operational status information including network traffic information and rule hit information of the TRM; determining current hotspot rules and hotspot sub-blocks in the TRM based on the operational status information; generating a scheduling policy according to the hotspot rules and the hotspot sub-blocks, the scheduling policy including a sub-block power control policy and a matching field control policy; and distributing the scheduling policy to the TRM for dynamic scheduling operations. This application enables the TRM to operate on demand while meeting current service processing requirements, thereby effectively reducing the overall power consumption of the TRM and improving the energy efficiency of network devices while ensuring matching performance and service continuity.

The invention provides a ternary content addressable memory which comprises a first memory unit and a second memory unit, and the second memory unit is electrically connected with the first memory unit. The first memory unit comprises a control transistor and a first impedance variable passive element, and one end of the first impedance variable passive element is electrically connected with a grid electrode of the control transistor. The second memory unit comprises a data transistor and a second impedance variable passive element, the data transistor is connected in series with the control transistor, and one end of the second impedance variable passive element is electrically connected with the grid electrode of the data transistor. Through the technical scheme of the invention, the ternary content addressable memory is a non-volatile ternary content addressable memory, the stability is high, the memory window is wider, and the energy consumption is reduced.

The embodiment of the invention provides a semiconductor structure and a preparation method thereof, a memory and electronic equipment. The semiconductor structure comprises a substrate, a source electrode, a drain electrode, a semiconductor layer, a ferroelectric gate dielectric layer and a grid electrode, the source electrode and the drain electrode are respectively in contact with the semiconductor layer, and the work functions of the source electrode and the drain electrode are intermediate forbidden band work functions; the ferroelectric gate dielectric layer is located between the gate and the semiconductor layer, and the ferroelectric gate dielectric layer comprises a ferroelectric material. According to the invention, the source electrode and the channel are Schottky junctions, and the channel and the drain electrode are Schottky junctions, and formed electron barriers and hole barriers are basically equal. The bipolar current characteristic of the Schottky source-drain field effect transistor is utilized, the polarization characteristic of the ferroelectric gate medium is combined, bipolar channel conductance controlled by gate voltage and ferroelectric polarization intensity at the same time is obtained, the complete function of the ternary content addressable memory can be achieved, and the ternary content addressable memory is simple in structure and low in cost. The three-state content addressable memory is more compact in structure and simple to operate.

A PTP transparent clock with inter-VLAN forwarding includes a layer two switch and a PTP module. The switch includes a first port associated with a first VLAN and a second port associated with a second VLAN. The switch detects a PTP frame at the first port and the PTP module receives the PTP frame. In response to the PTP module determining that the PTP frame is a forwardable frame, the switch forwards the PTP frame to the second port. For another embodiment, the switch includes a ternary content addressable memory ("TCAM") and the PTP module configures the TCAM to include forwarding rules. The layer two switch forwards the PTP frame to the second port in response to identifying a particular forwarding rule associated with forwarding the PTP frame.

A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory. The ternary content addressable memory is disposed on the substrate and includes a plurality of ternary content addressable memory bit cells, and at least two of the ternary content addressable memory bit cells are mirror-symmetrical along a symmetry axis. Each ternary content addressable memory bit cell includes two memory cells electrically connected to two word lines, respectively, and a logic circuit electrically connected to the memory cells. The logic circuit includes two first read transistors and two second read transistors. Each second read transistor includes a gate and two source / drain regions. The source / drain regions of the second read transistor are electrically connected to two match lines and a first read transistor, respectively. The word lines are disposed parallel to the match lines.

The application provides a 3D NAND flash memory system, relating to the technical field of integrated circuit structure design. By integrating MAC computation macros, local sensitive hash computation macros, and ternary content addressable memory macros in layered data storage arrays, a high degree of fusion of computation and storage is achieved, enabling parallel execution of feature extraction, hash code generation, and vector query update operations within the same physical location, significantly improving data processing speed and efficiency. Since the functional modules are distributed in different layered data storage arrays, the system can flexibly adjust the use of each functional module according to the needs of specific application scenarios, such as increasing or decreasing the number or type of specific functional modules, to adapt to different data processing tasks and data volumes, thereby improving the scalability and flexibility of the system.

The present disclosure provides a ternary content addressable memory including a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings, and one or more current sensing units. The memory cell string includes a plurality of memory cells, each of which is coupled to one of the plurality of first search lines and one of the plurality of second search lines. The current sensing unit is coupled to the plurality of memory cell strings. During a search operation, it is determined whether the data stored in the plurality of memory cell strings matches a data string to be searched, based on whether the one or more current sensing units detect current from the plurality of memory cell strings or based on the magnitude of the current flowing out of the one or more current sensing units from the plurality of memory cell strings.

The application discloses a training method of a graph neural network using a ternary content addressable memory and a memory device applying the same. The training method of the graph neural network using the ternary content addressable memory comprises the following steps. Data is extracted from a data set. The graph neural network is trained according to the data of the data set. The step of training the graph neural network comprises a feature collection stage, an aggregation stage and an update stage. In the aggregation stage, a TCAM crossbar matrix stores a plurality of edges corresponding to a vertex and outputs a hit vector to select part of the edges, and a product-sum crossbar matrix stores a plurality of features of the edges to perform a product-sum operation according to the hit vector.

A network device may include memory circuitry such as a ternary content addressable memory (TCAM) for implementing a memory profile having qualifiers based on which flow entries are defined for network traffic matching. To facilitate the implementation of a custom memory profile on the TCAM, the controller may obtain support information for the TCAM, may obtain user configuration information indicative of a network policy, and may identify qualifiers for a memory profile customized based on the TCAM support information and the user configuration information. The network device may receive the identified qualifiers from the controller and configure the custom memory profile on the TCAM.

A ternary content addressable memory is provided in a stacked memory device including a first memory cell string and a second memory cell string. The first memory cell string is coupled between a match line and a first source line and receives a plurality of first word line signals. The first memory cell string has a first memory cell string select switch. The first memory cell string select switch is controlled by a first search signal. The second memory cell string is coupled between the match line and the first source line and receives a plurality of second word line signals. The second memory cell string has a second memory cell string select switch. The second memory cell string select switch is controlled by a second search signal.

The application relates to a ternary content addressable memory, comprising a first nonvolatile reconfigurable transistor, a second nonvolatile reconfigurable transistor, a match line, a first write line, a second write line, a first search line and a second search line, wherein the match line is connected with the source of the first nonvolatile reconfigurable transistor and the drain of the second nonvolatile reconfigurable transistor; the first write line is connected with the drain of the first nonvolatile reconfigurable transistor; the second write line is connected with the source of the second nonvolatile reconfigurable transistor and the first write line; the first search line is connected with the gate of the first nonvolatile reconfigurable transistor; and the second search line is connected with the gate of the second nonvolatile reconfigurable transistor; the writing operation is realized by controlling the voltage of the first write line and the voltage of the second write line; and the addressing operation is realized by controlling the voltage of the first search line and the voltage of the second search line; the ternary content addressable memory has the advantages of small device quantity, low energy consumption and the like.

The invention relates to an SDN flow rule batch updating method and device, and the method comprises the steps: determining a candidate address range of each first SDN flow rule in a main rule table of a tri-state content addressable memory based on a rule dependency graph under the condition that a plurality of first SDN flow rules are temporarily stored in a temporary rule table of the tri-state content addressable memory, searching available flow table items in the main rule table; solving the maximum matching problem of the bipartite graph to obtain a matching result; and according to a matching result, updating the plurality of first SDN flow rules in the main rule table. A candidate address range of the SDN flow rule in the main rule table is determined based on the rule dependency graph, available flow table entries in the range are retrieved, a rule-available table entry bipartite graph to be updated is constructed, the maximum matching of the bipartite graph is solved, and zero-movement updating is achieved; according to the method and the device, frequent change of the main rule table of the TCAM can be reduced, the TCAM storage efficiency is improved, and the updating cost is reduced as much as possible.

An efficient FeFET-based CAM is disclosed which is capable of performing normal read, write but has the ability to match input data with don't-care. More specifically, a Ferroelectric FET Based Ternary Content Addressable Memory is disclosed. The design in some examples utilizes two FeFETs and four MOSFETs per cell. The CAM can be written in columns through multi-phase writes. It can be used a normal memory with indexing read. It also has the ability for ternary content-based search. The don't-care values can be either the input or the stored data.

The present disclosure provides a 4T ternary content addressable memory (TCAM) cell in which one cell is composed of four oxide semiconductor transistors by utilizing oxide semiconductor transistors having a dual-gate structure, a 4T TCAM cell array, and a method for writing information to the 4T TCAM cell. The 4T TCAM cell is connected to one word line, one match line, a bit line, a reverse bit line, a search line, and a reverse search line, and includes: a first write transistor that is a single-gate transistor; a second write transistor that is a single-gate transistor; a first read transistor that is a dual-gate transistor; and a second read transistor that is a dual-gate transistor, wherein the first read transistor, the second read transistor, the first write transistor and the second write transistor are implemented as oxide semiconductors.

The present invention discloses a control circuit for a ternary content addressable memory (TCAM). The control circuit includes a first logic unit and a second logic unit. The first logic unit is coupled to a first storage unit, a second storage unit, a first search line, a second search line, a reference voltage terminal, and a match line. The second logic unit is coupled to the first storage unit, the second storage unit, the first search line, the second search line, a first power supply line, and a second power supply line. When the voltages of the first search line and the second search line match the voltages of the first storage unit and the second storage unit, the second logic unit provides a path to electrically connect the first power supply line to the second power supply line.

The present disclosure provides a ternary content addressable memory, which includes a first memory unit and a second memory unit, and the second memory unit is electrically connected to the first memory unit. The first memory unit includes a control transistor and a first variable impedance passive component. One end of the first variable impedance passive component is electrically connected to the gate of the control transistor. The second memory unit includes a data transistor and a second variable impedance passive component. The data transistor is connected in series with the control transistor, and one end of the second variable impedance passive component is electrically connected to the gate of the data transistor.