28 results about "Ternary content addressable memory" patented technology

The invention discloses a method, a device and equipment for realizing a large-scale hybrid strategy. The method comprises the following steps of: receiving a message and analyzing the message to extract a field representing a data stream feature; generating intermediate state information according to an entry number, a port attribute and the field obtained through analysis, and obtaining a label through table look-up operation; fields, intermediate state information and labels of the messages are combined according to strategy rules defined by different storage blocks and compared with strategy entries in the storage blocks; and implementing a corresponding processing behavior on the message according to a comparison result. According to the method, parallel searching and processing behaviors of large-scale mixed policies can be realized, the method is suitable for more than hundreds of thousands of policy routing deployment and access control lists of various matching field combinations, and high-power-consumption and high-cost TCAM (Ternary Content Addressable Memory) storage can be avoided.

Devices, networks, systems, methods, and processes for facilitating parallel processing in ternary content addressable memory (TCAM) systems are described herein. A TCAM system including two physical TCAM blocks may detect a key-type associated with a key entry. The TCAM system can be operated in a wide search mode or a narrow search mode based on the detected key-type. In the narrow search mode, the key entry, being a narrow key, is inputted to the two physical TCAM blocks for associated data look-up. In the wide search mode, the key entry, being a wide key, is split into two segments, and one segment is inputted to one TCAM block and the other segment is inputted to the other TCAM block. The TCAM system may implement multiple logical TCAMs using the physical TCAM blocks. Thus, integrating a hybrid architecture of hardwired logic followed by programmable logic configuration, enhanced by parallel processing.

The present invention provides a TCAM unit, belonging to the field of semiconductor integrated circuit design. The TCAM unit of the present invention includes: a CMOS field-effect transistor; a complementary CMOS field-effect transistor; a diode; a complementary diode; a memory cell, whose first end is electrically connected to the drain of the CMOS field-effect transistor and the cathode of the diode and can be in a high resistance state and a low resistance state; a complementary memory cell, whose first end is electrically connected to the drain of the complementary CMOS field-effect transistor and the cathode of the complementary diode; a bit / select line, which is electrically connected to the second end of the memory cell; a complementary bit / select line, which is electrically connected to the second end of the complementary memory cell; a match line, which is electrically connected to the diode and the anode of the complementary diode; a word line, which is electrically connected to the gates of the CMOS field-effect transistor and the complementary CMOS field-effect transistor; and a ground line, which is electrically connected to the source of the CMOS field-effect transistor and the complementary CMOS field-effect transistor. The TCAM unit of the present invention has low leakage current, low power consumption in operation and standby mode, fewer connection lines, and high storage density.

Ferroelectric diodes comprising materials such as aluminum scandium nitride (AlScN) or hafnium zirconium oxide (HfZrO2) may be formed atop semiconductor structures such as CMOS wafers to create storage memory cells, search Ternary Content Addressable Memory (TCAM) cells, and / neural circuitry. The diodes are non-volatile and field programmable via pulsing to a pulse-number-dependent analog state, with high on / off and self-rectifying ratios. Cells may be formed, for example, with two diodes that are oppositely polarized, and may be achieved without transistors to form, for example, 0T-2R structures.

The application discloses a reconfigurable ternary content addressable memory unit, the memory unit utilizes the combination of three or more than three different states of the ternary content addressable memory and applies different gate control voltages to the memory unit to realize the reconfiguration of the unit, so as to realize the switching and working of the ternary content addressable memory unit between the parallel type and the serial type. The different states of the ternary content addressable memory refer to the states of the flash memory unit whose threshold voltage is controlled to different ranges. The application combines the advantages of the parallel type content addressable memory and the serial type content addressable memory, realizes the reconfigurable content addressable memory at a low area cost, and the array composed of the reconfigurable unit not only can realize the functions of the arrays composed of the above two types, but also provides the possibility of mixing the two types in the same array.

The present invention discloses a ternary content addressable memory, which includes a search line and a match line connected to a TCAM cell; the match line is equipped with a charge sharing circuit; the charge sharing circuit includes: a metal line disposed on one side of the match line, and a charge sharing control unit for controlling the connection and disconnection between the metal line and the match line; the charge sharing control unit connects the metal line and the match line after the match line is precharged to a high level and before the search line is activated, so that charge sharing occurs between the match line and the metal line, and the voltage of the match line is reduced through charge sharing. The present invention can reduce the voltage of the match line through charge sharing before the search line is activated. After the voltage of the match line is reduced, the evaluation speed of the match line can be increased, the efficiency of the search operation can be improved, and thus the working frequency and performance of the ternary content addressable memory can be improved.

The present disclosure provides a ternary content addressable memory, which includes a first memory unit and a second memory unit, and the second memory unit is electrically connected to the first memory unit. The first memory unit includes a control transistor and a first variable impedance passive component. One end of the first variable impedance passive component is electrically connected to the gate of the control transistor. The second memory unit includes a data transistor and a second variable impedance passive component. The data transistor is connected in series with the control transistor, and one end of the second variable impedance passive component is electrically connected to the gate of the data transistor.

The present application discloses a range information encoding and matching method and a computer storage medium. The method comprises: obtaining a new basic range, wherein the new basic range is used to decompose the range information of entries stored in a ternary content addressable memory (TCAM); performing an expansion operation on the new basic range based on pre-stored basic ranges to obtain an expansion result, wherein each pre-stored basic range has its own encoding information; and determining the encoding information corresponding to the new basic range based on the expansion result.

The invention discloses a routing device, a routing management method and a computer readable storage medium, and relates to the technical field of routing. The device comprises at least one processor, a ternary content addressable memory (TCAM), a result register, a decoder and a priority selector, the TCAM is divided into at least two storage partitions, and the sizes of the at least two storage partitions are adjusted according to the flow table occupancy rates of the at least two storage partitions, so that the difference value between the flow table occupancy rates of any two storage partitions is lower than a first threshold value. And after the destination IP address of the data packet is obtained, querying the plurality of storage partitions for matching, and outputting a matched flow table item through the result register, the decoder and the priority selector. Besides, the computer readable storage medium is used for storing a computer program and executing the route management method, the updating of the flow table item in the TCAM can ensure the longest prefix matching, and the route updating time delay is reduced.

The invention belongs to the technical field of digital circuit design, and particularly relates to a TCAM (ternary content addressable memory)-based quick matching search method, which comprises the following steps of: combining a block RAM (random access memory) and a distributed RAM to construct a TCAM; according to the length of the search word, dividing the search word into a plurality of search sub-words according to bits; according to the length of a search sub-word, inputting the search sub-word into a sub-block RAM or a sub-distributed RAM, processing results of a plurality of sub-RAMs, inputting the processed results into an encoder, and outputting a matching address by the encoder; and searching a corresponding operation in the RAM of the matched address and executing the operation. Compared with the prior art, the method has the advantages that the Block RAM (BRAM) and the LUTRAM in the FPGA are comprehensively utilized to optimize the method for dividing the search words, the BRAM and the LUTRAM are flexibly combined, the optimized composite TCAM (OC-TCAM) which is closer to or even fits the number of bits of the search words is achieved, and consumption of storage resources is greatly reduced.

This application relates to a dynamic scheduling method and apparatus for a three-state content-addressable memory (TRM). The method includes: acquiring operational status information corresponding to a network device, the operational status information including network traffic information and rule hit information of the TRM; determining current hotspot rules and hotspot sub-blocks in the TRM based on the operational status information; generating a scheduling policy according to the hotspot rules and the hotspot sub-blocks, the scheduling policy including a sub-block power control policy and a matching field control policy; and distributing the scheduling policy to the TRM for dynamic scheduling operations. This application enables the TRM to operate on demand while meeting current service processing requirements, thereby effectively reducing the overall power consumption of the TRM and improving the energy efficiency of network devices while ensuring matching performance and service continuity.

A PTP transparent clock with inter-VLAN forwarding includes a layer two switch and a PTP module. The switch includes a first port associated with a first VLAN and a second port associated with a second VLAN. The switch detects a PTP frame at the first port and the PTP module receives the PTP frame. In response to the PTP module determining that the PTP frame is a forwardable frame, the switch forwards the PTP frame to the second port. For another embodiment, the switch includes a ternary content addressable memory ("TCAM") and the PTP module configures the TCAM to include forwarding rules. The layer two switch forwards the PTP frame to the second port in response to identifying a particular forwarding rule associated with forwarding the PTP frame.

A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory. The ternary content addressable memory is disposed on the substrate and includes a plurality of ternary content addressable memory bit cells, and at least two of the ternary content addressable memory bit cells are mirror-symmetrical along a symmetry axis. Each ternary content addressable memory bit cell includes two memory cells electrically connected to two word lines, respectively, and a logic circuit electrically connected to the memory cells. The logic circuit includes two first read transistors and two second read transistors. Each second read transistor includes a gate and two source / drain regions. The source / drain regions of the second read transistor are electrically connected to two match lines and a first read transistor, respectively. The word lines are disposed parallel to the match lines.

The application provides a 3D NAND flash memory system, relating to the technical field of integrated circuit structure design. By integrating MAC computation macros, local sensitive hash computation macros, and ternary content addressable memory macros in layered data storage arrays, a high degree of fusion of computation and storage is achieved, enabling parallel execution of feature extraction, hash code generation, and vector query update operations within the same physical location, significantly improving data processing speed and efficiency. Since the functional modules are distributed in different layered data storage arrays, the system can flexibly adjust the use of each functional module according to the needs of specific application scenarios, such as increasing or decreasing the number or type of specific functional modules, to adapt to different data processing tasks and data volumes, thereby improving the scalability and flexibility of the system.

The application discloses a training method of a graph neural network using a ternary content addressable memory and a memory device applying the same. The training method of the graph neural network using the ternary content addressable memory comprises the following steps. Data is extracted from a data set. The graph neural network is trained according to the data of the data set. The step of training the graph neural network comprises a feature collection stage, an aggregation stage and an update stage. In the aggregation stage, a TCAM crossbar matrix stores a plurality of edges corresponding to a vertex and outputs a hit vector to select part of the edges, and a product-sum crossbar matrix stores a plurality of features of the edges to perform a product-sum operation according to the hit vector.

A network device may include memory circuitry such as a ternary content addressable memory (TCAM) for implementing a memory profile having qualifiers based on which flow entries are defined for network traffic matching. To facilitate the implementation of a custom memory profile on the TCAM, the controller may obtain support information for the TCAM, may obtain user configuration information indicative of a network policy, and may identify qualifiers for a memory profile customized based on the TCAM support information and the user configuration information. The network device may receive the identified qualifiers from the controller and configure the custom memory profile on the TCAM.

A ternary content addressable memory is provided in a stacked memory device including a first memory cell string and a second memory cell string. The first memory cell string is coupled between a match line and a first source line and receives a plurality of first word line signals. The first memory cell string has a first memory cell string select switch. The first memory cell string select switch is controlled by a first search signal. The second memory cell string is coupled between the match line and the first source line and receives a plurality of second word line signals. The second memory cell string has a second memory cell string select switch. The second memory cell string select switch is controlled by a second search signal.

The application relates to a ternary content addressable memory, comprising a first nonvolatile reconfigurable transistor, a second nonvolatile reconfigurable transistor, a match line, a first write line, a second write line, a first search line and a second search line, wherein the match line is connected with the source of the first nonvolatile reconfigurable transistor and the drain of the second nonvolatile reconfigurable transistor; the first write line is connected with the drain of the first nonvolatile reconfigurable transistor; the second write line is connected with the source of the second nonvolatile reconfigurable transistor and the first write line; the first search line is connected with the gate of the first nonvolatile reconfigurable transistor; and the second search line is connected with the gate of the second nonvolatile reconfigurable transistor; the writing operation is realized by controlling the voltage of the first write line and the voltage of the second write line; and the addressing operation is realized by controlling the voltage of the first search line and the voltage of the second search line; the ternary content addressable memory has the advantages of small device quantity, low energy consumption and the like.

The invention relates to an SDN flow rule batch updating method and device, and the method comprises the steps: determining a candidate address range of each first SDN flow rule in a main rule table of a tri-state content addressable memory based on a rule dependency graph under the condition that a plurality of first SDN flow rules are temporarily stored in a temporary rule table of the tri-state content addressable memory, searching available flow table items in the main rule table; solving the maximum matching problem of the bipartite graph to obtain a matching result; and according to a matching result, updating the plurality of first SDN flow rules in the main rule table. A candidate address range of the SDN flow rule in the main rule table is determined based on the rule dependency graph, available flow table entries in the range are retrieved, a rule-available table entry bipartite graph to be updated is constructed, the maximum matching of the bipartite graph is solved, and zero-movement updating is achieved; according to the method and the device, frequent change of the main rule table of the TCAM can be reduced, the TCAM storage efficiency is improved, and the updating cost is reduced as much as possible.

An efficient FeFET-based CAM is disclosed which is capable of performing normal read, write but has the ability to match input data with don't-care. More specifically, a Ferroelectric FET Based Ternary Content Addressable Memory is disclosed. The design in some examples utilizes two FeFETs and four MOSFETs per cell. The CAM can be written in columns through multi-phase writes. It can be used a normal memory with indexing read. It also has the ability for ternary content-based search. The don't-care values can be either the input or the stored data.

The present disclosure provides a 4T ternary content addressable memory (TCAM) cell in which one cell is composed of four oxide semiconductor transistors by utilizing oxide semiconductor transistors having a dual-gate structure, a 4T TCAM cell array, and a method for writing information to the 4T TCAM cell. The 4T TCAM cell is connected to one word line, one match line, a bit line, a reverse bit line, a search line, and a reverse search line, and includes: a first write transistor that is a single-gate transistor; a second write transistor that is a single-gate transistor; a first read transistor that is a dual-gate transistor; and a second read transistor that is a dual-gate transistor, wherein the first read transistor, the second read transistor, the first write transistor and the second write transistor are implemented as oxide semiconductors.

The present invention discloses a control circuit for a ternary content addressable memory (TCAM). The control circuit includes a first logic unit and a second logic unit. The first logic unit is coupled to a first storage unit, a second storage unit, a first search line, a second search line, a reference voltage terminal, and a match line. The second logic unit is coupled to the first storage unit, the second storage unit, the first search line, the second search line, a first power supply line, and a second power supply line. When the voltages of the first search line and the second search line match the voltages of the first storage unit and the second storage unit, the second logic unit provides a path to electrically connect the first power supply line to the second power supply line.

The application relates to a data processing device, method and chip. The device stores the correspondence between the service type and the index address in the first storage unit, so that when the control unit searches for data, the first target index address of the ternary content addressable memory can be obtained by searching in the first storage unit according to the obtained target service type. This is equivalent to screening the entries stored in the ternary content addressable memory. When the control unit subsequently performs entry matching in the ternary content addressable memory according to the obtained target key, the target key can only be matched with the entry stored at the first target index address, and other entries can be directly skipped. Therefore, the situation that the matched entry is not the entry suitable for the target service type due to the fact that the entries are not distinguished between service types can be improved, and the matching precision is improved.

The application relates to an SDN flow rule batch updating method and device, which comprises the following steps: in the case that multiple first SDN flow rules are temporarily stored in a temporary rule table of a ternary content addressable memory, determining a candidate address range of each first SDN flow rule in a main rule table of the ternary content addressable memory based on a rule dependency graph, and searching for available flow table entries in the main rule table; solving a maximum matching problem of a bipartite graph to obtain a matching result; and updating the multiple first SDN flow rules in the main rule table according to the matching result. The candidate address range of the SDN flow rule in the main rule table is determined based on the rule dependency graph, available flow table entries in the range are searched, a to-be-updated rule-available table entry bipartite graph is constructed and a maximum matching thereof is solved, and zero movement updating is realized; the application can reduce frequent changes to the main rule table of the TCAM, improve the storage efficiency of the TCAM, and reduce the updating cost as much as possible.

A method includes forming a ternary content addressable memory (TCAM) cell in a device layer, wherein the TCAM comprises a first static random access memory (SRAM) cell, a second SRAM cell, and a match cell, the first SRAM cell comprises a first pull-down transistor and a second pull-down transistor, and the second SRAM cell comprises a third pull-down transistor and a fourth pull-down transistor; forming a match line over a front-side of the device layer, wherein the match line is electrically coupled to the match cell; forming a first power supply voltage line over a back-side of the device layer, wherein the first power supply voltage line is electrically coupled to the first and third pull-down transistors of the first and second SRAM cells.

In a malware detection device, first characters in a network traffic flow are compared with a plurality of entries within a ternary content addressable memory (TCAM), the plurality of entries including a first entry that constitutes a first segment of a malware signature. In response to an output from the first TCAM indicating that the first characters match the first entry, a variable-character expression engine determines whether second characters in the network traffic flow match a first variable-length regular expression, the variable-length regular expression corresponding to a second segment of the malware signature. A comparand value is generated that includes third characters in the network traffic flow and an expression-match value that indicates whether the second characters match the first variable-length regular expression. The TCAM compares the first comparand value with the plurality of entries therein as part of a determination whether the network traffic flow contains the malware signature.

The utility model provides a device structure comprising a four-transistor ternary content addressable memory cell, which comprises a first series connection part of a first non-hysteresis transistor (e.g., a thin film transistor) and a first memory transistor (e.g., a thin film transistor), and a second series connection part of a second non-hysteresis transistor (e.g., a thin film transistor). The first memory transistor includes a first memory component configured to store a first binary bit; and a second series connection of a second non-hysteresis transistor and a second memory transistor, the second memory transistor including a second memory component configured to store a second binary bit. The first series connection portion and the second series connection portion are connected in parallel between the match line and the word line.

Embodiments of the present disclosure relate to a memory and a semiconductor device including the same. A TCAM (ternary content addressable memory) according to an embodiment includes a repeater in a delay path, the repeater being used to control timing in a replication circuit, which defines timing of a match. According to the above configuration, a TCAM that consumes low power and operates at high speed can be implemented.