9 results about "Content-addressable storage" patented technology

A recursive Analog Content Addressable Memory (ACAM) device includes a first comparison stage and a second comparison stage. The first comparison stage includes a first match line, a first base segment comparator connected between the first match line and a reference node, a first incremented segment comparator, and a first pass transistor. The first pass transistor and the first incremented segment comparator are connected in series between the first match line and the reference node. The second comparison stage includes a first inverter connected to the first pass transistor, a second match line connected to the first inverter, and a second base segment comparator connected between the second match line and the reference node. The device enables efficient comparison of multi-bit values.

Provided is a content addressable storage (CAS) system that allows a user to request, either through an application server or directly to one or more CAS servers, files and content related to a query. In some embodiments, the content can be discovered by searching previously-stored metadata related to each file at the content addressable storage server. The search can also be replicated across multiple content addressable storage servers in order to obtain varied results and redundant results. Duplicate results may be flagged or omitted, ˜d the results are returned to the requester.

The invention relates to a system for caching compiler transformations. A compilation system uses a parameterized hash in the form of a parameterized content addressable storage identifier (parameterized CAS ID) to store operator regions and any transformations to any operation of a compiler intermediate representation (IR). The parameterized CAS ID includes: a hash of the content of the region of operation; and a parameter set comprising a set of symbol references to objects used and / or referenced within the region of the operator.

The present application relates to a kind of multifunctional storage computing unit based on ferroelectric transistor, array and its fault-tolerant method.The unit is composed of two N-type FeFET and two NMOS transistor, by configuring peripheral control signal / circuit can realize three kinds of working mode: memory mode supports the non-volatile storage and read-write operation of data;Memory logic computing mode supports the Boolean logic operation to the storage word;Three-state content addressable memory mode supports high-speed parallel search and "irrelevant" bit matching operation.Further, the present application proposes a kind of anti-radiation reinforced three-state content addressable memory unit.The unit is based on the original multifunctional unit, access single-cycle storage module DICE and four storage transistors, realizes single node flip recovery.The present application integrates storage, computing and search function in single compact unit structure, improves energy efficiency and functional density, and the anti-radiation reinforced unit has good soft error tolerance ability and process robustness.

A method is performed by a device of a group of devices in a distributed data replication system. The method includes storing an index of objects in the distributed data replication system, the index being replicated while the objects are stored locally by the plurality of devices in the distributed data replication system. The method also includes conducting a scan of at least a portion of the index and identifying a redundant replica(s) of the at least one of the objects based on the scan of the index. The method further includes de-duplicating the redundant replica(s), and updating the index to reflect the status of the redundant replica.

The present disclosure relates to a content addressable memory device, a memory and an electronic device, the device comprising: a plurality of memory cells, each memory cell comprising a read-only memory device, a capacitor, the read-only memory device comprising a first input terminal, a second input terminal and an output terminal, the output terminal of the read-only memory device being connected to a first terminal of the capacitor, the read-only memory device storing data through a connection relationship between the first input terminal, the second input terminal and the output terminal; and a control module connected to each memory cell, configured to: control voltages of the first input terminal and the second input terminal of the read-only memory device of each memory cell to perform a target operation; and determine an operation result of the target operation according to a voltage of a second terminal of the capacitor. The embodiments of the present disclosure implement a content addressable memory device based on a read-only memory device, which can improve the area efficiency of the content addressable memory device, reduce or even eliminate unnecessary energy consumption caused by memory access, and reduce energy consumption.

The invention provides a semiconductor layout pattern, which comprises a substrate, wherein two content addressable memory cells are disposed on the substrate and arranged on two sides of a symmetry axis, and a first matching line conductive layer and a second matching line conductive layer are located on the substrate, wherein from a top view, the first matching line conductive layer and the second matching line conductive layer overlap the symmetry axis between the two content addressable memory cells and are arranged along the direction of the symmetry axis.

A method is performed by a device of a group of devices in a distributed data replication system. The method includes storing an index of objects in the distributed data replication system, the index being replicated while the objects are stored locally by the plurality of devices in the distributed data replication system. The method also includes conducting a scan of at least a portion of the index and identifying a redundant replica(s) of the at least one of the objects based on the scan of the index. The method further includes de-duplicating the redundant replica(s), and updating the index to reflect the status of the redundant replica.

A SDT computation system is provided. The SDT computation system includes a SDT module, an ACAM array, and a mapping module. The SDT module is for outputting a final probability and configured to provide a SDT structure with a root node and deeper inner nodes for calculating probability, in which the final probability of each leaf node of the SDT structure is a product of all of node probabilities along a path from the root node to each leaf node, and wherein a final output of the SDT module is from a leaf with the highest probability. The mapping module is configured to map the SDT structure into the ACAM array, such that each of the ACAM cells in the ACAM array has a threshold programmed to be a parameter for a node in a path leading towards the leaf node of the SDT structure.