22 results about "Content-addressable storage" patented technology

In an implementation, a device includes: a first inverter; a first sense amplifier connected to the first inverter; a first match line connected to the first sense amplifier; a first analog content addressable memory cell including: a first pull-down transistor; a second pull-down transistor, the first pull-down transistor and the second pull-down transistor being connected in series between the first match line and a reference node; a first memory circuit configured to store a first upper bound of a first range and to activate the first pull-down transistor when an analog input value is less than the first upper bound of the first range; and a second memory circuit configured to store a first lower bound of the first range and to activate the second pull-down transistor when the analog input value is greater than the first lower bound of the first range.

The present invention provides a method and system for executing a scheduling task of an automatic guided vehicle, belonging to the technical field of scheduling control. The method includes: determining a task instruction specified by a task issuing system, where the task instruction includes the content address of a task information file, and the content address is obtained after the task issuing system writes the task information file into a content addressable storage system; querying the content address, obtaining the task information file from the content addressable storage system, and determining a bidding rule file; based on the task information file, determining that the status information in the status log file of the transport vehicle reaches the bidding threshold in the bidding rule file; and executing a scheduling task corresponding to the task information file. The present invention is used for the autonomous completion of scheduling of an AGV.

The present invention provides a TCAM unit, belonging to the field of semiconductor integrated circuit design. The TCAM unit of the present invention includes: a CMOS field-effect transistor; a complementary CMOS field-effect transistor; a diode; a complementary diode; a memory cell, whose first end is electrically connected to the drain of the CMOS field-effect transistor and the cathode of the diode and can be in a high resistance state and a low resistance state; a complementary memory cell, whose first end is electrically connected to the drain of the complementary CMOS field-effect transistor and the cathode of the complementary diode; a bit / select line, which is electrically connected to the second end of the memory cell; a complementary bit / select line, which is electrically connected to the second end of the complementary memory cell; a match line, which is electrically connected to the diode and the anode of the complementary diode; a word line, which is electrically connected to the gates of the CMOS field-effect transistor and the complementary CMOS field-effect transistor; and a ground line, which is electrically connected to the source of the CMOS field-effect transistor and the complementary CMOS field-effect transistor. The TCAM unit of the present invention has low leakage current, low power consumption in operation and standby mode, fewer connection lines, and high storage density.

A recursive Analog Content Addressable Memory (ACAM) device includes a first comparison stage and a second comparison stage. The first comparison stage includes a first match line, a first base segment comparator connected between the first match line and a reference node, a first incremented segment comparator, and a first pass transistor. The first pass transistor and the first incremented segment comparator are connected in series between the first match line and the reference node. The second comparison stage includes a first inverter connected to the first pass transistor, a second match line connected to the first inverter, and a second base segment comparator connected between the second match line and the reference node. The device enables efficient comparison of multi-bit values.

Provided is a content addressable storage (CAS) system that allows a user to request, either through an application server or directly to one or more CAS servers, files and content related to a query. In some embodiments, the content can be discovered by searching previously-stored metadata related to each file at the content addressable storage server. The search can also be replicated across multiple content addressable storage servers in order to obtain varied results and redundant results. Duplicate results may be flagged or omitted, ˜d the results are returned to the requester.

Some of the embodiments herein provide a seamless cloud of storage. This storage may be content-addressable storage. An end application may or may not be exposed to the fact that content-addressable storage is used. Various embodiments herein provide event notification, which may allow applications or users to subscribe to particular events (such as storage of an X-ray by a particular entity). Some embodiments provide for a shared archive. A shared archive may provide homogeneous access to medical data, etc. that was previously stored into the CAS cloud by heterogeneous applications, varied data types, etc. Additionally, embodiments herein allow for the creation and distribution of virtual packages. For example, a user may create a virtual package for all images related to a patient so that she may have a virtual package of all of her medical data to present to a referring physician.

The present disclosure provides a three-dimensional memory device and a ternary content-addressable memory cell thereof. The ternary content-addressable memory cell includes a first memory cell, a second memory cell, a first search switch, and a second search switch. The first memory cell is disposed in a first AND-type flash memory cell row. The second memory cell is disposed in a second AND-type flash memory cell row. The first search switch is coupled between a first bit line and a match line corresponding to the first AND-type flash memory cell row, and the first search switch is controlled by a first search signal to be turned on or off. The second search switch is coupled between a second bit line and a match line corresponding to the second AND-type flash memory cell row, and the second search switch is controlled by a second search signal to be turned on or off.

The invention relates to a system for caching compiler transformations. A compilation system uses a parameterized hash in the form of a parameterized content addressable storage identifier (parameterized CAS ID) to store operator regions and any transformations to any operation of a compiler intermediate representation (IR). The parameterized CAS ID includes: a hash of the content of the region of operation; and a parameter set comprising a set of symbol references to objects used and / or referenced within the region of the operator.

The application belongs to the technical field of optical fiber devices for optical storage, and particularly relates to a content addressable memory based on a phase change material, which comprises a single-wavelength continuous light detection laser module, a wide-spectrum light detection laser module, a pulsed light pumping light source module, an electric pulse generating device, a 2*2 optical fiber coupler input array, a multi-core optical fiber fan-in module, a content addressable memory unit group, a multi-core optical fiber fan-out module, a 2*2 optical fiber coupler output array, a filter group, a photodetector group, a multi-channel detection spectrometer, a 1*n coupler, a photodetector, and a data acquisition module; the output ends of the single-wavelength continuous light detection laser module and the wide-spectrum light detection laser module are connected with the input ends of the 2*2 optical fiber coupler input array. The application can realize an exclusive OR comparison operation in the mode of building a Mach-Zehnder (MZ) interferometer, and provide a new paradigm for high-speed and high-density applications.

The present application relates to a kind of multifunctional storage computing unit based on ferroelectric transistor, array and its fault-tolerant method.The unit is composed of two N-type FeFET and two NMOS transistor, by configuring peripheral control signal / circuit can realize three kinds of working mode: memory mode supports the non-volatile storage and read-write operation of data;Memory logic computing mode supports the Boolean logic operation to the storage word;Three-state content addressable memory mode supports high-speed parallel search and "irrelevant" bit matching operation.Further, the present application proposes a kind of anti-radiation reinforced three-state content addressable memory unit.The unit is based on the original multifunctional unit, access single-cycle storage module DICE and four storage transistors, realizes single node flip recovery.The present application integrates storage, computing and search function in single compact unit structure, improves energy efficiency and functional density, and the anti-radiation reinforced unit has good soft error tolerance ability and process robustness.

Disclosed is a CAM device including a memory cell array, a voltage generator that respectively provides input signals to rows of the memory cell array, a driver circuit that respectively provides search signals to columns of the memory cell array and respectively provides complementary search signals to the columns, and a priority encoder connected to the rows. A first row includes first to M-th memory transistors respectively connected to the columns. The first memory transistor includes a first source terminal receiving the first complementary search signal, a first gate terminal receiving the first input signal, a first drain terminal receiving the first search signal, and a first electrical element. When a codeword corresponding to the first search signal and the first complementary search signal corresponds to a programmed state of the first electrical element, a capacitance value of the first memory transistor is smaller than a threshold value.

A multi-level content addressable memory device is provided. Some embodiments relate to a memory device including a plurality of rows of memory cells, a plurality of match lines, and a plurality of precharge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first segment includes a first subset of the memory cells of the first row, and the second segment includes a second subset of the memory cells of the first row. A first match line is coupled to the memory cells of the first subset, and a second match line is coupled to the memory cells of the second subset. A first precharge circuit is configured to precharge the first match line to a first precharge voltage, and a second precharge circuit is configured to precharge the second match line to a second precharge voltage different from (e.g., greater than) the first precharge voltage.

A method is performed by a device of a group of devices in a distributed data replication system. The method includes storing an index of objects in the distributed data replication system, the index being replicated while the objects are stored locally by the plurality of devices in the distributed data replication system. The method also includes conducting a scan of at least a portion of the index and identifying a redundant replica(s) of the at least one of the objects based on the scan of the index. The method further includes de-duplicating the redundant replica(s), and updating the index to reflect the status of the redundant replica.

The present disclosure provides a content-addressable storage device and a content-addressable storage controller, relating to the field of semiconductor technology. The device includes: N address registers, each for storing different address information; N counter circuits, each for storing the count value of the corresponding address register; N address comparison circuits, each for matching an input address with the address information stored in its corresponding address register; wherein, when the input address does not match the address information stored in any of the N address registers, and all of the N address registers store address information, the first counter circuit and its corresponding first address register are reset, the first address register stores the input address, the first counter circuit increases its count value, and the other unreset counter circuits decrease their count values. According to the embodiments of the present disclosure, accurate statistics can be performed on each address information in the memory.

The present disclosure relates to a content addressable memory device, a memory and an electronic device, the device comprising: a plurality of memory cells, each memory cell comprising a read-only memory device, a capacitor, the read-only memory device comprising a first input terminal, a second input terminal and an output terminal, the output terminal of the read-only memory device being connected to a first terminal of the capacitor, the read-only memory device storing data through a connection relationship between the first input terminal, the second input terminal and the output terminal; and a control module connected to each memory cell, configured to: control voltages of the first input terminal and the second input terminal of the read-only memory device of each memory cell to perform a target operation; and determine an operation result of the target operation according to a voltage of a second terminal of the capacitor. The embodiments of the present disclosure implement a content addressable memory device based on a read-only memory device, which can improve the area efficiency of the content addressable memory device, reduce or even eliminate unnecessary energy consumption caused by memory access, and reduce energy consumption.

The embodiment of the present application discloses a content-addressable storage device, method and related equipment, wherein the content-addressable storage device may include: a memory for storing data to be matched; a comparator including N comparison units, the N comparison units are respectively coupled to the memory; a scheduler for acquiring K search data and scheduling the K search data to K target comparison units among the N comparison units, the target comparison units being comparison units in an idle state; a controller for controlling the memory to read out the data to be matched and send them to the K target comparison units respectively; each of the K target comparison units is used to compare the corresponding search data with the data to be matched, and output the corresponding matching result according to the comparison result. By adopting the present application, the low power consumption and flexibility of the content-addressable storage device can be guaranteed.

The invention provides a semiconductor layout pattern, which comprises a substrate, wherein two content addressable memory cells are disposed on the substrate and arranged on two sides of a symmetry axis, and a first matching line conductive layer and a second matching line conductive layer are located on the substrate, wherein from a top view, the first matching line conductive layer and the second matching line conductive layer overlap the symmetry axis between the two content addressable memory cells and are arranged along the direction of the symmetry axis.

A computerized system includes a generative large language model (LLM). The LLM includes an encoder configured to provide a vector input to a content addressable memory system and a decoder configured to receive a vector output from the content addressable memory system and generate a data output. The content addressable memory system is configured to receive the vector input and generate a vector output based on data contents of the content addressable memory system. The content addressable memory system is configured to respond to receiving at least one memory update command by updating the data contents of the content addressable memory system.

This invention provides a reconfigurable tri-state content-addressable memory cell and its matching entry lookup method, relating to the field of non-volatile memory circuit design technology. The reconfigurable tri-state content-addressable memory cell includes a data storage module, a write control module, a first comparison module, and a second comparison module. The matching entry lookup method implemented based on this reconfigurable tri-state content-addressable memory cell can achieve two different search modes according to external control instructions. The first search mode can realize the tri-state data matching and lookup function of TCAM, and the second search mode, based on the first search mode, can realize the lookup of precise matching entries. This invention adopts a reconfigurable reuse approach, using the same circuit structure to not only realize the basic matching and lookup function of TCAM, but also to directly look up precise matching entries, saving hardware resources.

A method is performed by a device of a group of devices in a distributed data replication system. The method includes storing an index of objects in the distributed data replication system, the index being replicated while the objects are stored locally by the plurality of devices in the distributed data replication system. The method also includes conducting a scan of at least a portion of the index and identifying a redundant replica(s) of the at least one of the objects based on the scan of the index. The method further includes de-duplicating the redundant replica(s), and updating the index to reflect the status of the redundant replica.

A SDT computation system is provided. The SDT computation system includes a SDT module, an ACAM array, and a mapping module. The SDT module is for outputting a final probability and configured to provide a SDT structure with a root node and deeper inner nodes for calculating probability, in which the final probability of each leaf node of the SDT structure is a product of all of node probabilities along a path from the root node to each leaf node, and wherein a final output of the SDT module is from a leaf with the highest probability. The mapping module is configured to map the SDT structure into the ACAM array, such that each of the ACAM cells in the ACAM array has a threshold programmed to be a parameter for a node in a path leading towards the leaf node of the SDT structure.