36 results about "Match line" patented technology

In an implementation, a device includes: a first inverter; a first sense amplifier connected to the first inverter; a first match line connected to the first sense amplifier; a first analog content addressable memory cell including: a first pull-down transistor; a second pull-down transistor, the first pull-down transistor and the second pull-down transistor being connected in series between the first match line and a reference node; a first memory circuit configured to store a first upper bound of a first range and to activate the first pull-down transistor when an analog input value is less than the first upper bound of the first range; and a second memory circuit configured to store a first lower bound of the first range and to activate the second pull-down transistor when the analog input value is greater than the first lower bound of the first range.

The invention relates to the technical field of computing resource scheduling, in particular to a GPU server resource dynamic allocation management method, device and equipment and a medium, the GPU server resource dynamic allocation management method comprises the steps of extracting a jump path to divide task migration segments, matching path repeated tasks in a thread, screening overlapped tasks in combination with scheduling and residence time, and performing dynamic allocation management on GPU server resources. And analyzing a resource access trend to identify scrambling stable combinations, and associating address frequencies to generate a dynamic allocation list. According to the method, the behavior similarity among multiple tasks is identified by extracting the jump path among the tasks and performing repetition analysis, the dense overlapping interval of task execution is accurately delimited by means of cross mapping of task scheduling time and path residence time, and the task performance of the multiple tasks is determined in combination with the derivative judgment mode of the change trend of the access frequency of the shared resources. And identifying a task combination with stable resource scrambling behavior distribution, and establishing a dynamic binding strategy between the task and the GPU address resource based on the joint sorting of the address access frequency and the residence duration.

A recursive Analog Content Addressable Memory (ACAM) device includes a first comparison stage and a second comparison stage. The first comparison stage includes a first match line, a first base segment comparator connected between the first match line and a reference node, a first incremented segment comparator, and a first pass transistor. The first pass transistor and the first incremented segment comparator are connected in series between the first match line and the reference node. The second comparison stage includes a first inverter connected to the first pass transistor, a second match line connected to the first inverter, and a second base segment comparator connected between the second match line and the reference node. The device enables efficient comparison of multi-bit values.

A graph cache (200) comprising the following: a content-addressable memory array, CAM array, (202) comprising CAM rows (210) and matching lines corresponding to the CAM rows, wherein the CAM array is configured to receive an identifier of a target node of a graph structure (300), search for the identifier in the CAM rows and activate those of the matching lines that correspond to the CAM rows which store the identifier; a random access memory (RAM) array (208) comprising RAM lines (214) and word lines corresponding to the RAM lines; and a multiple match resolver (206) connected to the CAM array and the RAM array, wherein the multiple match resolver is configured to serially activate the word lines of the RAM array corresponding to the activated match lines of the CAM array.

The present disclosure discloses a content addressable memory apparatus. A self-test control circuit generates self-test driving signals and control an external test pattern generation circuit generates search data and an address signal. A content addressable memory circuit includes a memory circuit, an internal test pattern generation circuit and an internal comparison circuit. The memory circuit receives the search data and the address signal from the external test pattern generation circuit to perform search operation to generate actual match signals corresponding to the match lines. The internal test pattern generation circuit receives the self-test driving signals from the self-test control circuit to generate expected match signals. The internal comparison circuit receives and compares the actual match signals and the expected match signals to generate match comparison results such that the self-test control circuit receives the match comparison results and performs verification accordingly.

A photonic content addressable memory (CAM) (100) is provided. The photonic CAM (100) comprises: N search lines (101) and a plurality of match lines (102), each match line comprising N photonic CAM cells (110). Each search line (101) is configured to receive a search optical signal and each search optical signal comprises a different wavelength encoding one of N parallel search symbols. Each match line (102) is configured to receive: a wavelength division multiplexed content optical signal comprising a plurality of wavelengths, each wavelength encoding one of N parallel content symbols; and the N search optical signals from the N search lines (101). Each photonic CAM cell is configured to compare a respective search symbol with a respective content symbol and provide an output optical signal that is responsive to the comparison. Each match line (102) also comprises a content optical demultiplexer (120), configured to demultiplex the wavelength division multiplexed content optical signal and provide each CAM cell (110) with the respective content symbol.

The invention provides a gate controlled thyristor and a content addressable memory array. The grid control thyristor comprises a first transistor, a second transistor and a third transistor which are respectively provided with a control end, a first end and a second end. Control terminals of the first and third transistors are connected to a search line. The control end of the second transistor is connected to a fixed bias, and the second end is connected to the first end of the first transistor. The first end of the third transistor is connected to the matching line, and the second end is connected to the first end of the second transistor. A search bit is determined based on a search line voltage applied to the search line, and the search bit is compared with the data to determine whether the search bit is matched with the data. The architecture is suitable for a 3D NAND memory, and has the characteristics of high capacity and high performance.

The present disclosure provides a three-dimensional memory device and a ternary content-addressable memory cell thereof. The ternary content-addressable memory cell includes a first memory cell, a second memory cell, a first search switch, and a second search switch. The first memory cell is disposed in a first AND-type flash memory cell row. The second memory cell is disposed in a second AND-type flash memory cell row. The first search switch is coupled between a first bit line and a match line corresponding to the first AND-type flash memory cell row, and the first search switch is controlled by a first search signal to be turned on or off. The second search switch is coupled between a second bit line and a match line corresponding to the second AND-type flash memory cell row, and the second search switch is controlled by a second search signal to be turned on or off.

In an implementation, a device includes: a first inverter; a first sense amplifier connected to the first inverter; a first match line connected to the first sense amplifier; a first analog content addressable memory cell including: a first pull-down transistor; a second pull-down transistor, the first pull-down transistor and the second pull-down transistor being connected in series between the first match line and a reference node; a first memory circuit configured to store a first upper bound of a first range and to activate the first pull-down transistor when an analog input value is less than the first upper bound of the first range; and a second memory circuit configured to store a first lower bound of the first range and to activate the second pull-down transistor when the analog input value is greater than the first lower bound of the first range.

A gate-controlled thyristor (GCT) and CAM memory are provided. The GCT includes first, second and third transistors, each having a control end, first and second ends. The control ends of the first and second transistors are connected to a search line. The control end of the second transistor is applied with a fixed bias voltage, and the second end of the second transistor is connected to the first end of the first transistor. The second end of the third transistor is connected to the first end of the second transistor, and the first end is connected to a match line. Based on the search line voltage, a search bit is determined to compare the data and the search bit to determine whether the search bit matches the data. This configuration may be applied to 3D NAND memory, having a high capacity and performance.

The invention discloses an in-memory search matching line, method and system which can be applied to the technical field of analog circuits, and the matching line comprises a wire, a reading module, a power module, a node capacitor, a charging module, an MOS tube and a parasitic capacitor. Wherein one side of the wire is sequentially connected in series with the MOS tube and the reading module; at least one flash memory unit string is hung on the other side of the wire; the parasitic capacitor is mounted on the wire between the flash memory unit string and the MOS tube; and the charging module, the node capacitor and the power supply module are sequentially mounted on the wire between the MOS tube and the reading module. Therefore, the power supply module is additionally arranged on the matching line to charge the node capacitor, the current on the lead is quantified through the node voltage rising speed on the node capacitor read in the matching stage, the Hamming distance between different matching degrees is increased, and the accuracy of in-memory search is further improved.

A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory. The ternary content addressable memory is disposed on the substrate and includes a plurality of ternary content addressable memory bit cells, and at least two of the ternary content addressable memory bit cells are mirror-symmetrical along a symmetry axis. Each ternary content addressable memory bit cell includes two memory cells electrically connected to two word lines, respectively, and a logic circuit electrically connected to the memory cells. The logic circuit includes two first read transistors and two second read transistors. Each second read transistor includes a gate and two source / drain regions. The source / drain regions of the second read transistor are electrically connected to two match lines and a first read transistor, respectively. The word lines are disposed parallel to the match lines.

A Content-Addressable Memory (CAM) cell has a latch of cross-coupled inverters and transmission gates to bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing. A node in the latch is applied to a gate of a data transistor in series with a select transistor to discharge a match line when select and latch data mismatch. Second data and select transistors receive inverse data from the latch for a CAM but receive data from a second cell latch for a Ternary Content-Addressable Memory (TCAM) cell with two latches per pair of select lines. When mismatches occur, even cells discharge the match line using n-channel data and select transistors while odd cells charge a complement match line using p-channel data and select transistors. The total number of p-channel and n-channel transistors in the cell can be equal when using complementary match lines.

The present application provides a content addressable memory (CAM) device, a content addressable memory cell and a data search comparison method thereof. The content addressable memory device includes a plurality of content addressable memory strings and an electrical characteristic detection circuit coupled to the content addressable memory strings. When performing a data search, a search data is compared to a stored data stored in the content addressable memory strings. The content addressable memory strings generate a plurality of memory string currents. The electrical characteristic detection circuit detects the memory string currents or detects a plurality of match line voltages of a plurality of match lines coupled to the content addressable memory strings to generate a plurality of search results. The stored data and the search data are a range stored data and a single bit search data, or the stored data and the search data are a single bit stored data and a range search data.

Differential content-addressable memory, dCAM, array (1600), comprising: a plurality of rows (1610) and columns (1615) of dCAM cells (1500, 1605), each row of the dCAM cells containing a high-match line (1511) and a low-match line (1510); a detection circuit (1620) electrically connected to the high-match line and the low-match line, the detection circuit comprising: a transimpedance amplifier, TIA, (1730) configured to detect a match line current on the low-match line, and an analog-to-digital converter, ADC, (1720) configured to detect an output voltage of the TIA and a match line voltage of the high-match line; and a digital-to-analog converter, DAC, (1625), which is electrically connected to each column of the dCAM cells.

The invention discloses an MRAM (Magnetic Random Access Memory)-based content addressable memory circuit and a pipeline search method. The circuit comprises a first node; a second node; the differential comparison circuit is connected with the first node and the second node, is used for connecting a search line and a search complementary line and storing complementary data, and is also used for performing differential discharge on the first node and the second node according to the voltage of the search line and the voltage of the search complementary line and generating differential voltage; the input end of the inverter latch circuit is connected with the output end of the differential comparison circuit, and the inverter latch circuit is used for amplifying the differential voltage and then outputting the amplified differential voltage; the transmission matching circuit is used for being connected with a matching line, the input end of the transmission matching circuit is connected with the output end of the inverter latch circuit, and the transmission matching circuit is used for outputting a mismatch signal when it is detected that the complementary data is not matched with the search data according to the differential voltage. The content addressable memory circuit based on the MRAM solves the problem of high search error rate of the content addressable memory circuit based on the MRAM.

A ternary content addressable memory is provided in a stacked memory device including a first memory cell string and a second memory cell string. The first memory cell string is coupled between a match line and a first source line and receives a plurality of first word line signals. The first memory cell string has a first memory cell string select switch. The first memory cell string select switch is controlled by a first search signal. The second memory cell string is coupled between the match line and the first source line and receives a plurality of second word line signals. The second memory cell string has a second memory cell string select switch. The second memory cell string select switch is controlled by a second search signal.

The application relates to a ternary content addressable memory, comprising a first nonvolatile reconfigurable transistor, a second nonvolatile reconfigurable transistor, a match line, a first write line, a second write line, a first search line and a second search line, wherein the match line is connected with the source of the first nonvolatile reconfigurable transistor and the drain of the second nonvolatile reconfigurable transistor; the first write line is connected with the drain of the first nonvolatile reconfigurable transistor; the second write line is connected with the source of the second nonvolatile reconfigurable transistor and the first write line; the first search line is connected with the gate of the first nonvolatile reconfigurable transistor; and the second search line is connected with the gate of the second nonvolatile reconfigurable transistor; the writing operation is realized by controlling the voltage of the first write line and the voltage of the second write line; and the addressing operation is realized by controlling the voltage of the first search line and the voltage of the second search line; the ternary content addressable memory has the advantages of small device quantity, low energy consumption and the like.

A 3D search engine receives searches for application to word lines of a nonvolatile memory array. Features are stored and searched in accordance with a multi-level thermometer encoding enabling use of multi-bit cell NAND technology, such as MLC, TLC, and QLC. The engine uses two word lines per digit of information of the searches and two memory devices per digit of stored feature to search against. The engine uses respective bit lines of the nonvolatile memory array as respective match lines for searching. Respective memory strings (e.g., NAND memory strings) of the nonvolatile memory array are usable to store respective data words, e.g., corresponding to features to search for. Respective pluralities of the memory strings are coupled in parallel to respective shared bit lines. The engine determines matches according to degree of similarity, such as high to low. The engine is applicable to searching, comparing, and sorting.

A multi-level content addressable memory device is provided. Some embodiments relate to a memory device including a plurality of rows of memory cells, a plurality of match lines, and a plurality of precharge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first segment includes a first subset of the memory cells of the first row, and the second segment includes a second subset of the memory cells of the first row. A first match line is coupled to the memory cells of the first subset, and a second match line is coupled to the memory cells of the second subset. A first precharge circuit is configured to precharge the first match line to a first precharge voltage, and a second precharge circuit is configured to precharge the second match line to a second precharge voltage different from (e.g., greater than) the first precharge voltage.

The invention provides an operation system and an operation method with multi-order thermometer coding. The computing system includes a memory and a search encoder. A memory includes: a plurality of memory strings, each memory string coupled to a match line and a source line, the match line coupled to a sense amplifier, and each memory string including a plurality of series devices, each series device having and responsive to a configuration state and a corresponding control input, the configuration state being one of three or more mutually exclusive state values; and a plurality of word lines, each word line coupled to a corresponding one of the plurality of corresponding control inputs of the plurality of series devices. The search encoder is used for receiving a search and driving a plurality of word lines according to the search code. Each memory string is configured to couple a match line and a source line via an impedance, the impedance being responsive to an amount of match between a plurality of configuration states of the memory strings and a plurality of corresponding control inputs of the plurality of series devices, and the sense amplifier is configured to generate a corresponding indication of the amount of match, the corresponding indication being indicated by the impedance.

The present invention provides a content addressable memory cell, which includes a plurality of storage circuits and a comparison circuit. A first storage circuit of the plurality of storage circuits is configured to store a data, and a second storage circuit of the plurality of storage circuits is configured to store a status bit. The comparison circuit is configured to determine whether to adjust a level of a match line to a level of one of the data and the status bit in response to levels of a plurality of search bit lines and the other of the data and the status bit.

A method includes forming a ternary content addressable memory (TCAM) cell in a device layer, wherein the TCAM comprises a first static random access memory (SRAM) cell, a second SRAM cell, and a match cell, the first SRAM cell comprises a first pull-down transistor and a second pull-down transistor, and the second SRAM cell comprises a third pull-down transistor and a fourth pull-down transistor; forming a match line over a front-side of the device layer, wherein the match line is electrically coupled to the match cell; forming a first power supply voltage line over a back-side of the device layer, wherein the first power supply voltage line is electrically coupled to the first and third pull-down transistors of the first and second SRAM cells.

A memory cell device comprising: first and second tuneable inverter modules, wherein each inverter module comprises at least one tuneable load configured to set a threshold voltage for the inverter module, wherein each inverter module is configured to receive an input signal and output an output signal in dependence on the voltage of the input signal and the threshold voltage, wherein the threshold voltages of the first and second tuneable inverter modules define a matching window, wherein the device further comprises an output module configured to receive output signals from the first and second tuneable inverter modules and configured to output a match signal and / or a contribution to a match signal in response to the output signals representing or indicating that the input signal has a voltage in the matching window, wherein at least one of a) and b): a) the device comprises a tuning module configured to tune the load of the tuneable load of each of the first and second inverter modules thereby to set the matching window; b) wherein the output module comprises a pull up or pull down circuit for coupling a high voltage to a match line in response to the voltage of the input signal being in the matching window.

A memory device includes a plurality of memory cells and a plurality of sense amplifiers electrically connected to the one or more of plurality of memory cells and each of the plurality of sense amplifiers are configured to sense and amplify a bitline signal of a bitline to produce an amplified bitline signal. At least one of the plurality of sense amplifiers may be configured to perform operations which includes generating a matching signal, indicating whether a first bit value corresponding to the amplified bitline signal and a second bit value corresponding to a first input signal match, based on first and second input signals that are input through first and second input lines, respectively, where the first input signal and the second input signal are complementary to one another; and controlling a voltage on a match line, based on the matching signal.

The invention provides a content addressable memory matching line structure and a high-reliability search scheme thereof, and relates to the field of integrated circuit design. The matching line structure comprises n-bit CAM circuit units, matching lines, sampling transistors, phase inverters and discharging transistors, wherein the n-bit CAM circuit units are completely identical, and the phase inverters and the discharging transistors are used for connecting the CAM circuit units and the matching lines. The interiors of the n-bit CAM circuit units are respectively composed of a magnetic tunnel junction / CMOS hybrid logic network and a reading circuit, the output of the first-bit CAM circuit unit is connected with a matching line through a sampling transistor, and the matching line is charged when a search result is matching, so that the matching line is kept at a high level; the outputs of the rest n-1 CAM circuit units are connected with the input ends of n-1 phase inverters, and the outputs of the phase inverters control the grid electrodes of the corresponding discharge transistors so as to control whether the matching lines discharge or not. The latch structure of the reading circuit is effectively utilized, charges are supplemented for ML when the ML has an electric leakage trend, the ML is stably kept at a high level, and a correct result is output.

A shielding circuit for a content addressable memory includes a shielding control circuit and a level control circuit. The shielding control circuit generates a shielding signal based on a word line signal and a write enable signal. When the two signals correspond to a first level, the shielding signal is a first shielding signal. When the two signals correspond to different levels, the shielding signal is a second shielding signal. The two shielding signals are different. The level control circuit generates a level control signal based on the shielding signal to determine whether to pull a voltage level of an output terminal to a predetermined level. The output terminal is coupled to a match line of the content addressable memory. When the shielding signal is the first shielding signal, the level control circuit pulls the voltage level of the output terminal to the predetermined level. When the shielding signal is the second shielding signal, the level control circuit does not affect the voltage level of the output terminal.

A four transistor ternary content-addressable memory cell includes a first series connection of a first non-hysteretic transistor (e.g., a thin-film transistor) and a first memory transistor (e.g., a thin-film transistor) including a first memory element configured to store a first binary bit; and a second series connection of a second non-hysteretic transistor and a second memory transistor including a second memory element configured to store a second binary bit. The first series connection and the second series connection are connected in parallel between a match line and a word line.

The application relates to an intelligent side station supervision system and method for adaptive scheduling of computing power, wherein a hardware state sensing unit collects power, temperature and charging and discharging state data in real time and inputs the data into a mode control unit, the mode control unit matches a corresponding operation mode according to the hardware state and sets an upper limit of the occupancy rate threshold of global computing power resources in the mode, thereby realizing hierarchical matching of the hardware health state and the computing power demand; a thread pool management unit allocates independent inference thread pools to each algorithm model group for parallel processing of video frame data, a time delay monitoring unit acquires the single frame inference time consumption of each model group in real time and calculates a maximum difference value and inputs the maximum difference value into a scheduling unit, the scheduling unit dynamically adjusts the thread quota of each inference thread pool according to the maximum difference value and the hardware state parameter, under the premise of ensuring the timing synchronization of multi-algorithm concurrent inference, realizes real-time linkage of computing power allocation and the hardware state, and ensures that the dynamic balance of computing power and power consumption can be maintained under different working conditions.

The invention provides a semiconductor layout pattern, which comprises a substrate, wherein two content addressable memory cells are disposed on the substrate and arranged on two sides of a symmetry axis, and a first matching line conductive layer and a second matching line conductive layer are located on the substrate, wherein from a top view, the first matching line conductive layer and the second matching line conductive layer overlap the symmetry axis between the two content addressable memory cells and are arranged along the direction of the symmetry axis.