16 results about "Match line" patented technology

A recursive Analog Content Addressable Memory (ACAM) device includes a first comparison stage and a second comparison stage. The first comparison stage includes a first match line, a first base segment comparator connected between the first match line and a reference node, a first incremented segment comparator, and a first pass transistor. The first pass transistor and the first incremented segment comparator are connected in series between the first match line and the reference node. The second comparison stage includes a first inverter connected to the first pass transistor, a second match line connected to the first inverter, and a second base segment comparator connected between the second match line and the reference node. The device enables efficient comparison of multi-bit values.

A graph cache (200) comprising the following: a content-addressable memory array, CAM array, (202) comprising CAM rows (210) and matching lines corresponding to the CAM rows, wherein the CAM array is configured to receive an identifier of a target node of a graph structure (300), search for the identifier in the CAM rows and activate those of the matching lines that correspond to the CAM rows which store the identifier; a random access memory (RAM) array (208) comprising RAM lines (214) and word lines corresponding to the RAM lines; and a multiple match resolver (206) connected to the CAM array and the RAM array, wherein the multiple match resolver is configured to serially activate the word lines of the RAM array corresponding to the activated match lines of the CAM array.

A Content-Addressable Memory (CAM) cell has a latch of cross-coupled inverters and transmission gates to bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing. A node in the latch is applied to a gate of a data transistor in series with a select transistor to discharge a match line when select and latch data mismatch. Second data and select transistors receive inverse data from the latch for a CAM but receive data from a second cell latch for a Ternary Content-Addressable Memory (TCAM) cell with two latches per pair of select lines. When mismatches occur, even cells discharge the match line using n-channel data and select transistors while odd cells charge a complement match line using p-channel data and select transistors. The total number of p-channel and n-channel transistors in the cell can be equal when using complementary match lines.

The present application provides a content addressable memory (CAM) device, a content addressable memory cell and a data search comparison method thereof. The content addressable memory device includes a plurality of content addressable memory strings and an electrical characteristic detection circuit coupled to the content addressable memory strings. When performing a data search, a search data is compared to a stored data stored in the content addressable memory strings. The content addressable memory strings generate a plurality of memory string currents. The electrical characteristic detection circuit detects the memory string currents or detects a plurality of match line voltages of a plurality of match lines coupled to the content addressable memory strings to generate a plurality of search results. The stored data and the search data are a range stored data and a single bit search data, or the stored data and the search data are a single bit stored data and a range search data.

Differential content-addressable memory, dCAM, array (1600), comprising: a plurality of rows (1610) and columns (1615) of dCAM cells (1500, 1605), each row of the dCAM cells containing a high-match line (1511) and a low-match line (1510); a detection circuit (1620) electrically connected to the high-match line and the low-match line, the detection circuit comprising: a transimpedance amplifier, TIA, (1730) configured to detect a match line current on the low-match line, and an analog-to-digital converter, ADC, (1720) configured to detect an output voltage of the TIA and a match line voltage of the high-match line; and a digital-to-analog converter, DAC, (1625), which is electrically connected to each column of the dCAM cells.

A ternary content addressable memory is provided in a stacked memory device including a first memory cell string and a second memory cell string. The first memory cell string is coupled between a match line and a first source line and receives a plurality of first word line signals. The first memory cell string has a first memory cell string select switch. The first memory cell string select switch is controlled by a first search signal. The second memory cell string is coupled between the match line and the first source line and receives a plurality of second word line signals. The second memory cell string has a second memory cell string select switch. The second memory cell string select switch is controlled by a second search signal.

The application relates to a ternary content addressable memory, comprising a first nonvolatile reconfigurable transistor, a second nonvolatile reconfigurable transistor, a match line, a first write line, a second write line, a first search line and a second search line, wherein the match line is connected with the source of the first nonvolatile reconfigurable transistor and the drain of the second nonvolatile reconfigurable transistor; the first write line is connected with the drain of the first nonvolatile reconfigurable transistor; the second write line is connected with the source of the second nonvolatile reconfigurable transistor and the first write line; the first search line is connected with the gate of the first nonvolatile reconfigurable transistor; and the second search line is connected with the gate of the second nonvolatile reconfigurable transistor; the writing operation is realized by controlling the voltage of the first write line and the voltage of the second write line; and the addressing operation is realized by controlling the voltage of the first search line and the voltage of the second search line; the ternary content addressable memory has the advantages of small device quantity, low energy consumption and the like.

The present invention provides a content addressable memory cell, which includes a plurality of storage circuits and a comparison circuit. A first storage circuit of the plurality of storage circuits is configured to store a data, and a second storage circuit of the plurality of storage circuits is configured to store a status bit. The comparison circuit is configured to determine whether to adjust a level of a match line to a level of one of the data and the status bit in response to levels of a plurality of search bit lines and the other of the data and the status bit.

A method includes forming a ternary content addressable memory (TCAM) cell in a device layer, wherein the TCAM comprises a first static random access memory (SRAM) cell, a second SRAM cell, and a match cell, the first SRAM cell comprises a first pull-down transistor and a second pull-down transistor, and the second SRAM cell comprises a third pull-down transistor and a fourth pull-down transistor; forming a match line over a front-side of the device layer, wherein the match line is electrically coupled to the match cell; forming a first power supply voltage line over a back-side of the device layer, wherein the first power supply voltage line is electrically coupled to the first and third pull-down transistors of the first and second SRAM cells.

A memory cell device comprising: first and second tuneable inverter modules, wherein each inverter module comprises at least one tuneable load configured to set a threshold voltage for the inverter module, wherein each inverter module is configured to receive an input signal and output an output signal in dependence on the voltage of the input signal and the threshold voltage, wherein the threshold voltages of the first and second tuneable inverter modules define a matching window, wherein the device further comprises an output module configured to receive output signals from the first and second tuneable inverter modules and configured to output a match signal and / or a contribution to a match signal in response to the output signals representing or indicating that the input signal has a voltage in the matching window, wherein at least one of a) and b): a) the device comprises a tuning module configured to tune the load of the tuneable load of each of the first and second inverter modules thereby to set the matching window; b) wherein the output module comprises a pull up or pull down circuit for coupling a high voltage to a match line in response to the voltage of the input signal being in the matching window.

The application relates to an intelligent side station supervision system and method for adaptive scheduling of computing power, wherein a hardware state sensing unit collects power, temperature and charging and discharging state data in real time and inputs the data into a mode control unit, the mode control unit matches a corresponding operation mode according to the hardware state and sets an upper limit of the occupancy rate threshold of global computing power resources in the mode, thereby realizing hierarchical matching of the hardware health state and the computing power demand; a thread pool management unit allocates independent inference thread pools to each algorithm model group for parallel processing of video frame data, a time delay monitoring unit acquires the single frame inference time consumption of each model group in real time and calculates a maximum difference value and inputs the maximum difference value into a scheduling unit, the scheduling unit dynamically adjusts the thread quota of each inference thread pool according to the maximum difference value and the hardware state parameter, under the premise of ensuring the timing synchronization of multi-algorithm concurrent inference, realizes real-time linkage of computing power allocation and the hardware state, and ensures that the dynamic balance of computing power and power consumption can be maintained under different working conditions.

The invention provides a semiconductor layout pattern, which comprises a substrate, wherein two content addressable memory cells are disposed on the substrate and arranged on two sides of a symmetry axis, and a first matching line conductive layer and a second matching line conductive layer are located on the substrate, wherein from a top view, the first matching line conductive layer and the second matching line conductive layer overlap the symmetry axis between the two content addressable memory cells and are arranged along the direction of the symmetry axis.

A gate-controlled thyristor (GCT) and CAM memory are provided. The GCT includes first, second and third transistors, each having a control end, first and second ends. The control ends of the first and second transistors are connected to a search line. The control end of the second transistor is applied with a fixed bias voltage, and the second end of the second transistor is connected to the first end of the first transistor. The second end of the third transistor is connected to the first end of the second transistor, and the first end is connected to a match line. Based on the search line voltage, a search bit is determined to compare the data and the search bit to determine whether the search bit matches the data. This configuration may be applied to 3D NAND memory, having a high capacity and performance.

A graph cache may be dynamically reconfigured to adapt to changes in a graph or access requirements. In an implementation, the graph cache includes a content addressable memory (CAM) array comprising CAM rows and match lines, configured to receive an identifier of a target node of a graph structure and a key associated with a user credential, search for a combination of the identifier and key, and activate match lines corresponding to matching CAM rows. A random-access memory (RAM) array comprises RAM rows and word lines. A multiple match resolver serially activates word lines of the RAM array corresponding to activated match lines. A management processor receives an encrypted input, decrypts it to obtain the identifier and key, and provides the combination to the CAM array.

A content addressable memory (CAM) device and method of operation thereof are provided. The CAM device includes a plurality of CAM sub-banks. Each CAM sub-bank includes an array of CAM cells arranged in rows and columns and partitioned along the column dimension into a first stage and a second stage. Each CAM sub-bank includes a plurality of first stage match lines (MLs), a plurality of first stage search line (SL) pairs, a plurality of second stage MLs, a plurality of second stage SL pairs. The first stage MLs indicate whether a first portion of a search key matches a first stage row segment. Each second stage SL pair is coupled to a column of CAM cells of the second stage and is gated by a SL enable signal. The SL enable signal is deasserted when none of the plurality of first stage MLs indicate a match, thereby preventing a second portion of the search key from being provided to the plurality of second stage SL pairs.

The invention discloses a ternary addressable memory array and a preparation method and a test method thereof, and relates to the technical field of transistor manufacturing. Comprising a plurality of ternary addressable memories which are arranged and interconnected in an array mode; each ternary addressable memory is composed of two reconfigurable double-gate field effect transistors which are connected with each other; a plurality of matching lines and grounding lines; the matching lines of the ternary addressable memories in the same row are connected with the same line, and the grounding lines are connected with the same line; a plurality of search lines; the search lines of the ternary addressable memories in the same column are connected with the same line; a plurality of first write lines and second write lines; the first write-in lines of the ternary addressable memories in the same column are connected with the same line, and the second write-in lines are connected with the same line. The memory array disclosed by the invention has the advantages of compact structure, strong reconfigurability, good compatibility and the like, obviously reduces the circuit area and power consumption, and is suitable for a high-energy-efficiency storage and calculation integrated system and a next-generation adaptive logic integrated circuit.